MC68HC908KX8 MC68HC908KX2 MC68HC08KX8. Technical Data M68HC08. Microcontrollers. MC68HC908KX8/D Rev. 1, 2/2002

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1 MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Technical Data M68HC08 Microcontrollers MC68HC908KX8/D Rev. 1, 2/2002

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3 MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Technical Data To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Motorola and are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. Motorola, Inc., 2002 MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA 3

4 Technical Data Date April, 2001 February, 2002 Revision Level Revision History Description Page Number(s) Label for pin 9 corrected in Figure 1-1 and Figure , 33 $FF is the erase state of the FLASH, not $00. 82, 252, 255 First bulleted paragraph under the subsection 16.5 Interrupts reworded for clarity Revision to the description of the CHxMAX bit and the note that follows that description Forced monitor mode information added to Table In Figure 18-1, resistor value for connection between V TST and IRQ1 changed from 10 kω to 1 kω. 7.3 Features Corrected third bullet ICG Trim Register Corrected description of the TRIM7:TRIM0 bits 15.3 Features Corrected divide by factors in first bullet 216 Figure Timebase Block Diagram Corrected divide-by-2 blocks Table Timebase Divider Selection Corrected last divider tap entry Section 16. Timer Interface Module (TIM) Timer discrepancies corrected throughout this section 20.5 Thermal Characteristics Corrected SOIC thermal resistance and maximum junction temperature Vdc DC Electrical Characteristics and Vdc DC Electrical Characteristics Corrected footnote for V DD supply current in stop mode Appendix B. MC68HC08KX8 Overview Added to supply exception information for the MC68HC08KX8 Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev and MOTOROLA

5 Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 List of Sections Section 1. General Description Section 2. Memory Map Section 3. Random-Access Memory (RAM) Section. FLASH Memory Section 5. Central Processor Unit (CPU) Section 6. System Integration Module (SIM) Section 7. Internal Clock Generator Module (ICG) Section 8. Low-Voltage Inhibit (LVI) Section 9. Configuration Register (CONFIG) Section 10. Input/Output (I/O) Ports Section 11. Computer Operating Properly Module (COP) Section 12. External Interrupt (IRQ) Section 13. Keyboard Interrupt Module (KBI) Section 1. Serial Communications Interface Module (SCI) Section 15. Timebase Module (TBM) Section 16. Timer Interface Module (TIM) Section 17. Analog-to-Digital Converter (ADC) MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA List of Sections 3

6 List of Sections Section 18. Monitor ROM (MON) Section 19. Break (BRK) Module Section 20. Electrical Specifications Section 21. Mechanical Specifications Section 22. Ordering Information Appendix A. MC68HC908KX2 Overview Appendix B. MC68HC08KX8 Overview Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 List of Sections MOTOROLA

7 Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Section 1. General Description Table of Contents 1.1 Contents Introduction Features MCU Block Diagram Pin Assignments Supply Pins (V DD and V SS ) Oscillator Pins (OSC1 and OSC2) External Interrupt Pin (IRQ1) Port A Input/Output (I/O) Pins (PTA/KBD PTA0/KBD0) Analog Reference Pin (V REFH ) Port B Input/Output (I/O) Pins (PTB7/(OSC2)/RST PTB0/AD0) Section 2. Memory Map 2.1 Contents Introduction I/O Registers Monitor ROM Section 3. Random-Access Memory (RAM) 3.1 Contents Introduction Functional Description MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA Table of Contents 7

8 Table of Contents Section. FLASH Memory.1 Contents Introduction Functional Description FLASH Control Register FLASH Page Erase Operation FLASH Mass Erase Operation FLASH Program/Read Operation FLASH Block Protection FLASH Block Protect Register Wait Mode Stop Mode Section 5. Central Processor Unit (CPU) 5.1 Contents Introduction Features CPU Registers Accumulator Index Register Stack Pointer Program Counter Condition Code Register Arithmetic/Logic Unit (ALU) Low-Power Modes Wait Mode Stop Mode Instruction Set Summary Opcode Map Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev Table of Contents MOTOROLA

9 Table of Contents Section 6. System Integration Module (SIM) 6.1 Contents Introduction SIM Bus Clock Control and Generation Bus Timing Clock Startup from POR or LVI Reset Clocks in Stop Mode and Wait Mode Reset and System Initialization Active Resets from Internal Sources Power-On Reset Computer Operating Properly (COP) Reset Illegal Opcode Reset Illegal Address Reset Forced Monitor Mode Entry Reset (MENRST) Low-Voltage Inhibit (LVI) Reset SIM Counter SIM Counter During Power-On Reset SIM Counter During Stop Mode Recovery SIM Counter and Reset States Program Exception Control Interrupts Hardware Interrupts SWI Instruction Reset Low-Power Modes Wait Mode Stop Mode SIM Registers SIM Reset Status Register Interrupt Status Registers Interrupt Status Register Interrupt Status Register Interrupt Status Register MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA Table of Contents 9

10 Table of Contents Section 7. Internal Clock Generator Module (ICG) 7.1 Contents Introduction Features Functional Description Clock Enable Circuit Internal Clock Generator Digitally Controlled Oscillator Modulo N Divider Frequency Comparator Digital Loop Filter External Clock Generator External Oscillator Amplifier External Clock Input Path Clock Monitor Circuit Clock Monitor Reference Generator Internal Clock Activity Detector External Clock Activity Detector Clock Selection Circuit Clock Selection Switches Clock Switching Circuit Usage Notes Switching Clock Sources Enabling the Clock Monitor Using Clock Monitor Interrupts Quantization Error in DCO Output Digitally Controlled Oscillator Binary Weighted Divider Variable-Delay Ring Oscillator Ring Oscillator Fine-Adjust Circuit Switching Internal Clock Frequencies Nominal Frequency Settling Time Settling to Within 15 Percent Settling to Within 5 Percent Total Settling Time Trimming Frequency on the Internal Clock Generator Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev Table of Contents MOTOROLA

11 Table of Contents 7.6 Low-Power Modes Wait Mode Stop Mode CONFIG or MOR Options External Clock Enable (EXTCLKEN) External Crystal Enable (EXTXTALEN) Slow External Clock (EXTSLOW) Oscillator Enable In Stop (OSCENINSTOP) Input/Output (I/O) Registers ICG Control Register ICG Multiplier Register ICG Trim Register ICG DCO Divider Register ICG DCO Stage Register Section 8. Low-Voltage Inhibit (LVI) 8.1 Contents Introduction Features Functional Description Polled LVI Operation Forced Reset Operation Voltage Hysteresis Protection LVI Trip Selection LVI Status Register LVI Interrupts Low-Power Modes Wait Mode Stop Mode MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA Table of Contents 11

12 Table of Contents Section 9. Configuration Register (CONFIG) 9.1 Contents Introduction Functional Description Section 10. Input/Output (I/O) Ports 10.1 Contents Introduction Port A Port A Data Register Data Direction Register A Port A Input Pullup Enable Register Port B Port B Data Register Data Direction Register B Section 11. Computer Operating Properly Module (COP) 11.1 Contents Introduction Block Diagram Functional Description I/O Signals CGMXCLK STOP Instruction COPCTL Write Power-On Reset Internal Reset Reset Vector Fetch COPD (COP Disable) COPRS (COP Rate Select) COP Control Register Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev Table of Contents MOTOROLA

13 Table of Contents 11.7 Interrupts Monitor Mode Low-Power Modes Wait Mode Stop Mode Section 12. External Interrupt (IRQ) 12.1 Contents Introduction Features Functional Description IRQ1 Pin IRQ Status and Control Register Section 13. Keyboard Interrupt Module (KBI) 13.1 Contents Introduction Features Functional Description Keyboard Initialization Low-Power Modes Wait Mode Stop Mode I/O Registers Keyboard Status and Control Register Keyboard Interrupt Enable Register Section 1. Serial Communications Interface Module (SCI) 1.1 Contents Introduction MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA Table of Contents 13

14 Table of Contents 1.3 Features Pin Name Conventions Functional Description Data Format Transmitter Character Length Character Transmission Break Characters Idle Characters Inversion of Transmitted Output Transmitter Interrupts Receiver Character Length Character Reception Data Sampling Framing Errors Baud Rate Tolerance Receiver Wakeup Receiver Interrupts Error Interrupts Low-Power Modes Wait Mode Stop Mode I/O Signals TxD (Transmit Data) RxD (Receive Data) I/O Registers SCI Control Register SCI Control Register SCI Control Register SCI Status Register SCI Status Register SCI Data Register SCI Baud Rate Register Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev Table of Contents MOTOROLA

15 Table of Contents Section 15. Timebase Module (TBM) 15.1 Contents Introduction Features Functional Description Interrupts TBM Interrupt Rate Low-Power Modes Wait Mode Stop Mode Timebase Control Register Section 16. Timer Interface Module (TIM) 16.1 Contents Introduction Features Functional Description TIM Counter Prescaler Input Capture Output Compare Unbuffered Output Compare Buffered Output Compare Pulse-Width Modulation (PWM) Unbuffered PWM Signal Generation Buffered PWM Signal Generation PWM Initialization Interrupts Low-Power Modes Wait Mode Stop Mode I/O Signals I/O Registers MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA Table of Contents 15

16 Table of Contents TIM Status and Control Register TIM Counter Registers TIM Counter Modulo Registers TIM Channel Status and Control Registers TIM Channel Registers Section 17. Analog-to-Digital Converter (ADC) 17.1 Contents Introduction Features Functional Description ADC Port I/O Pins Voltage Conversion Conversion Time Continuous Conversion Accuracy and Precision Interrupts Low-Power Modes Wait Mode Stop Mode I/O Signals ADC Analog Power and ADC Voltage Reference Pins ADC Voltage In (ADCVIN) I/O Registers ADC Status and Control Register ADC Data Register ADC Input Clock Register Section 18. Monitor ROM (MON) 18.1 Contents Introduction Features Functional Description Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev Table of Contents MOTOROLA

17 Table of Contents 18.5 Monitor Mode Entry Normal Monitor Mode Forced Monitor Mode Monitor Mode Vectors Data Format Break Signal Baud Rate Force Monitor Mode Normal Monitor Mode Commands Security Section 19. Break (BRK) Module 19.1 Contents Introduction Features Functional Description Flag Protection During Break Interrupts CPU During Break Interrupts TIM1 and TIM2 During Break Interrupts COP During Break Interrupts Low-Power Modes Wait Mode Stop Mode Break Module Registers Break Status and Control Register Break Address Registers Break Status Register Break Flag Control Register Break Auxiliary Register MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA Table of Contents 17

18 Table of Contents Section 20. Electrical Specifications 20.1 Contents Introduction Absolute Maximum Ratings Functional Operating Range Thermal Characteristics Vdc DC Electrical Characteristics Vdc DC Electrical Characteristics Internal Oscillator Characteristics External Oscillator Characteristics Trimmed Accuracy of the Internal Clock Generator Volt to 3.3-Volt Trimmed Internal Clock Generator Characteristics Volt to 5.5-Volt Trimmed Internal Clock Generator Characteristics Analog-to-Digital Converter (ADC) Characteristics Memory Characteristics Section 21. Mechanical Specifications 21.1 Contents Introduction Pin Plastic Dual In-Line Package (PDIP) Pin Small Outline Package (SOIC) Section 22. Ordering Information 22.1 Contents Introduction MC Order Numbers Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev Table of Contents MOTOROLA

19 Table of Contents Appendix A. MC68HC908KX2 Overview A.1 Contents A.2 Introduction A.3 Functional Description Appendix B. MC68HC08KX8 Overview B.1 Contents B.2 Introduction B.3 FLASH x ROM Module Changes B.3.1 FLASH for ROM Substitution B.3.2 Partial Use of FLASH-Related Module B. Configuration Register Programming B.5 Electrical Specifiations B.5.1 Absolute Maximum Ratings B.5.2 Functional Operating Range B.5.3 Thermal Characteristics B Vdc DC Electrical Characteristics B Vdc DC Electrical Characteristics B.5.6 Internal Oscillator Characteristics B.5.7 External Oscillator Characteristics B.5.8 Trimmed Accuracy of the Internal Clock Generator B Volt to 3.3-Volt Trimmed Internal Clock Generator Characteristics B Volt to 5.5-Volt Trimmed Internal Clock Generator Characteristics B.5.9 Analog-to-Digital Converter (ADC) Characteristics B.5.10 Memory Characteristics MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA Table of Contents 19

20 Table of Contents Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev Table of Contents MOTOROLA

21 Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 List of Figures Figure Title Page 1-1 MC68HC908KX8 MCU Block Diagram PDIP and SOIC Pin Assignments Power Supply Bypassing Memory Map Control, Status, and Data Registers FLASH Control Register (FLCR) FLASH Programming Flowchart FLASH Block Protect Register (FLBPR) FLASH Block Protect Start Address CPU Registers Accumulator (A) Index Register (H:X) Stack Pointer (SP) Program Counter (PC) Condition Code Register (CCR) SIM Block Diagram SIM I/O Register Summary System Clock Signals Sources of Internal Reset Internal Reset Timing POR Recovery Interrupt Entry Interrupt Recovery Interrupt Processing Interrupt Recognition Example MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA List of Figures 21

22 List of Figures Figure Title Page 6-11 Wait Mode Entry Timing Wait Recovery from Interrupt Wait Recovery from Internal Reset Stop Mode Entry Timing Stop Mode Recovery from Interrupt SIM Reset Status Register (SRSR) Interrupt Status Register 1 (INT1) Interrupt Status Register 2 (INT2) Interrupt Status Register 3 (INT3) ICG Module Block Diagram Internal Clock Generator Block Diagram External Clock Generator Block Diagram Clock Monitor Block Diagram Internal Clock Activity Detector External Clock Activity Detector Clock Selection Circuit Block Diagram Code Example for Switching Clock Sources Code Example for Enabling the Clock Monitor ICG Module I/O Register Summary ICG Control Register (ICGCR) ICG Multiplier Register (ICGMR) ICG Trim Register (ICGTR) ICG DCO Divider Control Register (ICGDVR) ICG DCO Stage Control Register (ICGDSR) LVI Module Block Diagram LVI Status Register (LVISR) Configuration Register 2 (CONFIG2) Configuration Register 1 (CONFIG1) I/O Port Register Summary Port A Data Register (PTA) Data Direction Register A (DDRA) Port A I/O Circuit Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev List of Figures MOTOROLA

23 List of Figures Figure Title Page 10-5 Port A Input Pullup Enable Register (PTAPUE) Port B Data Register (PTB) Data Direction Register B (DDRB) Port B I/O Circuit COP Block Diagram COP Control Register (COPCTL) IRQ Block Diagram IRQ Status and Control Register (ISCR) Keyboard Module Block Diagram I/O Register Summary Keyboard Status and Control Register (KBSCR) Keyboard Interrupt Enable Register (KBIER) SCI Module Block Diagram SCI I/O Register Summary SCI Data Formats SCI Transmitter Break Characters SCI Receiver Block Diagram Receiver Data Sampling Slow Data Fast Data SCI Control Register 1 (SCC1) SCI Control Register 2 (SCC2) SCI Control Register 3 (SCC3) SCI Status Register 1 (SCS1) Flag Clearing Sequence SCI Status Register 2 (SCS2) SCI Data Register (SCDR) SCI Baud Rate Register (SCBR) Timebase Block Diagram Timebase Control Register (TBCR) MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA List of Figures 23

24 List of Figures Figure Title Page 16-1 TIM Block Diagram TIM I/O Register Summary PWM Period and Pulse Width TIM Status and Control Register (TSC) TIM Counter Registers (TCNTH and TCNTL) TIM Counter Modulo Registers (TMODH and TMODL) TIM Channel Status and Control Registers (TSC0 and TSC1) CHxMAX Latency TIM Channel Registers (TCH0H/L and TCH1H/L) ADC Block Diagram ADC Status and Control Register (ADSCR) ADC Data Register (ADR) ADC Input Clock Register (ADICLK) Normal Monitor Mode Circuit Monitor Data Format Break Transaction Read Transaction Write Transaction Stack Pointer at Monitor Mode Entry Monitor Mode Entry Timing Break Module Block Diagram I/O Register Summary Break Status and Control Register (BRKSCR) Break Address Register High (BRKH) Break Address Register Low (BRKL) SIM Break Status Register (SBSR) SIM Break Flag Control Register (SBFCR) Break Auxiliary Register (BRKAR) Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev List of Figures MOTOROLA

25 List of Figures Figure Title Page 20-1 Example of Frequency Variation Across Temperature, Trimmed at Nominal 3 Volts, 25 C, and N = Example of Frequency Variation Across Temperature, Trimmed at Nominal 3 Volts, 25 C, and N = Example of Frequency Variation Across Temperature, Trimmed at Nominal 5 Volts, 25 C, and N = Example of Frequency Variation Across Temperature, Trimmed at Nominal 5 Volts, 25 C, and N = A-1 MC68HC908KX2 Memory Map B-1 M68HC08KX8 MCU Block Diagram B-2 Mask Option Register 2 (MOR2) B-3 Mask Option Register 1 (MOR1) MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA List of Figures 25

26 List of Figures Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev List of Figures MOTOROLA

27 Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 List of Tables Table Title Page 2-1 Vector Locations Protect Start Address Examples Instruction Set Summary Opcode Map Signal Name Conventions Interrupt Sources Correction Sizes from DLF to DCO Quantization Error in ICLK Typical Settling Time Examples ICG Module Register Bit Interaction Summary LVIOUT Bit Indication External Clock Option Settings Port A Pin Functions Port B Pin Functions Pin Name Conventions Start Bit Verification Data Bit Recovery Stop Bit Recovery Character Format Selection SCI Baud Rate Prescaling MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA List of Tables 27

28 List of Tables Table Title Page 1-7 SCI Baud Rate Selection SCI Baud Rate Selection Examples Timebase Divider Selection Prescaler Selection Mode, Edge, and Level Selection Mux Channel Select ADC Clock Divide Ratio Monitor Mode Entry Monitor Mode Vector Relocation Normal Monitor Mode Baud Rate Selection READ (Read Memory) Command WRITE (Write Memory) Command IREAD (Indexed Read) Command IWRITE (Indexed Write) Command READSP (Read Stack Pointer) Command RUN (Run User Program) Command MC Order Numbers Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev List of Tables MOTOROLA

29 Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 1.1 Contents 1.2 Introduction Section 1. General Description 1.2 Introduction Features MCU Block Diagram Pin Assignments Supply Pins (V DD and V SS ) Oscillator Pins (OSC1 and OSC2) External Interrupt Pin (IRQ1) Port A Input/Output (I/O) Pins (PTA/KBD PTA0/KBD0) Analog Reference Pin (V REFH ) Port B Input/Output (I/O) Pins (PTB7/(OSC2)/RST PTB0/AD0) The MC68HC908KX8 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCU). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. The information contained is this document pertains to the MC68HC908KX2 and the MC68HC08KX8 with the exceptions found in: Appendix A. MC68HC908KX2 Overview Appendix B. MC68HC08KX8 Overview MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA General Description 29

30 General Description 1.3 Features Features of the MC68HC908KX8 MCU include: High-performance M68HC08 architecture Fully upward-compatible object code with M6805, M16805, and M68HC05 Families Maximum internal bus frequencies of: 8 MHz at 5.0 V MHz at 3.0 V Internal oscillator requiring no external components: Software selectable bus frequencies 25 percent accuracy with trim capability to 2 percent Clock monitor Option to allow use of external clock source or external crystal/ceramic resonator Eight Kbytes of on-chip, in-circuit programmable FLASH memory FLASH program memory security (1) On-chip programming firmware for use with host personal computer which does not require high voltage for entry 192 bytes of on-chip random-access memory (RAM) 16-bit, 2-channel timer interface (TIM) module -channel, 8-bit, analog-to-digital converter (ADC) with highvoltage reference (V REFH ) double bonded to V DD pin Serial communications interface (SCI) module 5-bit keyboard interrupt (KBI) with wakeup feature 13 general-purpose input/output (I/O) ports: Five shared with KBI and TIM, with 15-mA source/15-ma sink capabilities and with programmable pullups on generalpurpose input ports Four shared with ADC Two shared with SCI 1. No security feature is absolutely secure. However, Motorola s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev General Description MOTOROLA

31 General Description MCU Block Diagram 1. MCU Block Diagram Low-voltage inhibit (LVI) module with software selectable trip points, 2.6-V or.3-v trip point Timebase module (TBM) with Clock prescalar for eight user-selectable, periodic real-time interrupts Active clock source in stop mode for periodic wakeup from stop using external crystal or internal oscillator External asynchronous interrupt pin with internal pullup (IRQ1) System protection features: Computer operating properly (COP) reset Low-voltage detection with reset Illegal opcode detection with reset Illegal address detection with reset 16-pin plastic dual in-line (PDIP) or small outline (SOIC) package Low-power design fully static with stop and wait modes Internal power-up reset circuit requiring no external pins 0 C to +125 C operation Features of the CPU08 include: Enhanced HC05 programming model Extensive loop control functions 16 addressing modes, eight more than the M68HC05 16-bit index register and stack pointer Memory-to-memory data transfers Fast 8 8 multiply instruction Fast 16/8 divide instruction Binary-coded decimal (BCD) instructions Optimization for controller applications Third party C language support Figure 1-1 shows the structure of the MC68HC908KX8 MCU. MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA General Description 31

32 32 General Description MOTOROLA Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0,5 V DD V SS CPU REGISTERS M68HC08 CPU ARITHMETIC/LOGIC UNIT CONTROL AND STATUS REGISTERS 78 BYTES USER FLASH 7680 BYTES USER RAM 192 BYTES MONITOR ROM 295 BYTES USER FLASH VECTOR SPACE 36 BYTES FLASH BURN-IN ROM 102 BYTES INTERNAL CLOCK GENERATOR MODULE 62)7:$5(Ã6(/(&7$%/( POWER SYSTEM INTEGRATION MODULE IRQ MODULE INTERNAL BUS POWER-ON RESET MODULE SECURITY MODULE COMPUTER OPERATING PROPERLY MODULE LOW-VOLTAGE INHIBIT MODULE 2-CHANNEL TIMER INTERFACE MODULE KEYBOARD INTERRUPT MODULE ANALOG-TO-DIGITAL CONVERTER MODULE SERIAL COMMUNICATION INTERFACE MODULE PROGRAMMABLE TIME BASE MODULE BREAK MODULE Notes: 1. Pin contains integrated pullup resistor 2. High-current source/sink pin 3. Pin contains software selectable pullup resistor if general function I/O pin is configured as input.. Pins are used for external clock source or crystal/ceramic resonator option. Figure 1-1. MC68HC908KX8 MCU Block Diagram DDRB DDRA PTB PTA PTB0/AD0 PTB1/AD1 PTB2/AD2 PTB3/AD3 PTB/RxD PTB5/TxD PTB6/(OSC1) () PTB7/(OSC2)/RST () PTA0/KBD0 (2), (3) (2), (3) PTA1/KBD1 PTA2/KBD2/TCH0 (2), (3) (2), (3) PTA3/KBD3/TCH1 PTA/KBD (2), (3) General Description

33 General Description Pin Assignments 1.5 Pin Assignments Supply Pins (V DD and V SS ) Oscillator Pins (OSC1 and OSC2) Figure 1-2 shows the pin assignments for MC68HC908KX8. V SS PTA1/KBD1 PTA0/KBD0 IRQ1 PTB0/AD0 PTB1/AD1 PTB2/AD2 PTB3/AD PTA/KBD PTA3/KBD3/TCH1 PTA2/KBD2/TCH0 PTB/RxD PTB5/TxD PTB6/(OSC1) PTB7/(OSC2)/RST Figure 1-2. PDIP and SOIC Pin Assignments V DD and V SS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as shown in Figure 1-3. Place the bypass capacitors as close to the MCU power pins as possible. Use high-frequency response ceramic capacitors for C Bypass. C Bulk are optional bulk current bypass capacitors for use in applications that require the port pins to source high-current levels. The OSC1 and OSC2 pins are available through programming options in the configuration register. These pins then become the connections to an external clock source or crystal/ceramic resonator. PTB7 and PTB6 are not available for the crystal/ceramic resonator option and PTB6 is unavailable for the external clock source option V DD MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA General Description 33

34 General Description External Interrupt Pin (IRQ1) Figure 1-3. Power Supply Bypassing IRQ1 is an asynchronous external interrupt pin with an internal pullup resistor. See Section 12. External Interrupt (IRQ) Port A Input/Output (I/O) Pins (PTA/KBD PTA0/KBD0) 9 '' PTA/KBD PTA0/KBD0 is a 5-bit special-function port that shares its pins with the keyboard interrupt (KBI) module and the 2-channel timer module (TIM). Any or all of the port A pins can be programmed to serve as keyboard interrupt pins. The respective pin utilizes an internal pullup resistor when enabled. See Section 13. Keyboard Interrupt Module (KBI). Each port A pin contains a software selectable internal pullup resistor when the general-function I/O port is configured as an input. See Section 10. Input/Output (I/O) Ports. The pullup resistor is automatically disabled once a TIM special function is enabled for that pin. All port A pins are high-current source/sink pins. Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 V DD MCU C Bypass 0.1 µf + C Bulk Note: Component values shown represent typical applications. V SS 3 General Description MOTOROLA

35 General Description Pin Assignments NOTE: Analog Reference Pin (V REFH ) Any unused inputs and I/O ports should be tied to an appropriate logic level (either V DD or V SS ). Although the I/O ports of the MC68HC908KX8 do not require termination, termination is recommended to reduce the possibility of static damage. The V REFH pin is the analog reference voltage for the analog-to-digital converter (ADC) module. The voltage is supplied through a double-bond to the V DD pin. See Section 20. Electrical Specifications for ADC parameters Port B Input/Output (I/O) Pins (PTB7/(OSC2)/RST PTB0/AD0) PTB7/(OSC2)/RST PTB0/AD0 are general-purpose bidirectional I/O port pins, all sharing special functions. PTB7 and PTB6 share with the on-chip oscillator circuit through configuration options. See 7..3 External Clock Generator. PTB5 and PTB share with the SCI module. See Section 1. Serial Communications Interface Module (SCI). PTB3 PTB0 share with the ADC module. See Section 17. Analog-to-Digital Converter (ADC). MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA General Description 35

36 General Description Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev General Description MOTOROLA

37 Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 2.1 Contents 2.2 Introduction Section 2. Memory Map 2.2 Introduction I/O Registers Monitor ROM The central processor unit (CPU08) can address 6 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: 7680 bytes of FLASH memory 192 bytes of random-access memory (RAM) 36 bytes of user-defined vectors 295 bytes of monitor read-only memory (ROM) MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA Memory Map 37

38 Memory Map $0000 $003F $000 $00FF $0100 $0FFF $1000 $13FF $100 $DFFF $E000 $FDFF I/O REGISTERS (6 BYTES) RAM (192 BYTES) UNIMPLEMENTED (3839 BYTES) FLASH BURN-IN ROM (102 BYTES) UNIMPLEMENTED (52,22 BYTES) USER FLASH MEMORY (7680 BYTES) Technical Data MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 $FE00 $FE01 $FE02 $FE03 $FE0 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE1F $FE20 $FF6 $FF7 $FF7D $FF7E $FF7F $FFDB $FFDC $FFFF Figure 2-1. Memory Map RESERVED SIM RESET STATUS REGISTER (SRSR) RESERVED RESERVED INTERRUPT STATUS REGISTER 1 (INT1) INTERRUPT STATUS REGISTER 2 (INT2) INTERRUPT STATUS REGISTER 3 (INT3) RESERVED FLASH CONTROL REGISTER (FLCR) BREAK ADDRESS REGISTER HIGH (BRKH) BREAK ADDRESS REGISTER LOW (BRKL) BREAK STATUS AND CONTROL REGISTER (BRKSCR) LVI STATUS REGISTER (LVISR) UNIMPLEMENTED (18 BYTES) MONITOR ROM (295 BYTES) UNIMPLEMENTED (57 BYTES) FLASH BLOCK PROTECT REGISTER (FLBPR) UNIMPLEMENTED (90 BYTES) FLASH VECTORS (36 BYTES) 38 Memory Map MOTOROLA

39 Memory Map I/O Registers 2.3 I/O Registers Most of the control, status, and data registers are in the zero-page area of $0000 $003F. Additional input/output (I/O) registers have the following addresses: $FE01 SIM reset status register, SRSR $FE0 Interrupt status register 1, INT1 $FE05 Interrupt status register 2, INT2 $FE06 Interrupt status register 3, INT3 $FE08 FLASH control register, FLCR $FE09 Break address register high, BRKH $FE0A Break address register low, BRKL $FE0B Break status and control register, BRKSCR $FE0C LVI status register, LVISR $FF7E FLASH block protect register, FLBPR in non-volatile FLASH memory $FFFF COP control register, COPCTL A summary of the registers available on the MC68HC908KX8 is provided in Figure 2-2. Table 2-1 is a list of vector locations. Addr. Register Name Bit Bit 0 $0000 $0001 Port A Data Register (PTA) See page 151. Port B Data Register (PTB) See page 155. $0002 Unimplemented Read: Write: Reset: Read: Write: Reset: PTA PTA3 PTA2 PTA1 PTA0 Unaffected by reset PTB7 PTB6 PTB5 PTB PTB3 PTB2 PTB1 PTB0 Unaffected by reset = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 7) MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Rev. 1.0 Technical Data MOTOROLA Memory Map 39

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