CS61C : Machine Structures

Transcription

1 inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 34 Single Cycle CPU Control I Lecturer PSOE Dan Garcia Quake?! NBC movie on May 3 rd. Truth stranger than fiction? The San Andreas fault may be on the cusp of producing a flurry of quakes that could rattle SoCal w/a strong temblor every few decades or less cnn.com/24/tech/science/4/14/san.andreas.awakens.ap CS 61C L34 Single Cycle CPU Control I (1)

2 Anatomy Review: 5 components of any Computer Personal Computer Today Yesterday (& finish up) Computer Processor Control ( brain ) path ( brawn ) (where programs, data live when running) Devices Input Output Keyboard, Mouse Disk (where programs, data live when not running) Display, Printer CS 61C L34 Single Cycle CPU Control I (2)

3 Review: How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) => datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic CS 61C L34 Single Cycle CPU Control I (3)

4 Register-Register Timing: One complete cycle PC Rs, Rt, Rd, Op, Func ALUctr Old Value New Value Old Value Old Value Instruction Access Time New Value Delay through Control Logic New Value RegWr Old Value New Value Register File Access busa, B Old Value Time New Value ALU Delay busw Old Value New Value busw Rd Rs Rt RegWr5 5 5 Rw Ra Rb -bit Registers busa busb ALUctr ALU Result Register Write Occurs Here CS 61C L34 Single Cycle CPU Control I (4)

5 3c: Logical Operations with Immediate R[rt] = R[rs] op ZeroExt[] ] RegDst busw RegWr Rd Rs Rt? Rw Ra Rb -bit Registers 16 Rt 31 busb ZeroExt busa op rs rt immediate 31 6 bits 5 bits 5 bits rd? 16 bits 16 bits ALUSrc ALUct r ALU Result immediate 16 bits What about Rt register read?? Already defined -bit MUX; Zero Ext? CS 61C L34 Single Cycle CPU Control I (5)

6 3d: Load Operations R[rt] = Mem[R[rs] + SignExt[]] Example: lw rt, rs, busw Rd Rt RegDst Rs Rt? RegWr op rs rt immediate 6 bits 5 bits 5 bits 16 bits Rw Ra Rb -bit Registers 16 busb Extender busa ALUctr ALU In?? ALUSrc MemWr WrEn Adr W_Src ExtOp CS 61C L34 Single Cycle CPU Control I (6)

7 3e: Store Operations Mem[ R[rs] + SignExt[] ] = R[rt] Ex.: sw rt, rs, op rs rt immediate 6 bits 5 bits 5 bits 16 bits Rd Rt ALUctr MemWr RegDst Rs Rt RegWr5 5 5 busa busw Rw Ra Rb -bit Registers 16 busb Extender ALU In WrEnAdr W_Src Mu x CS 61C L34 Single Cycle CPU Control I (7) ExtOp ALUSrc

8 3f: The Branch Instruction beq rs, rt, mem[pc] Fetch the instruction from memory Equal = R[rs] == R[rt] Calculate the branch condition if (Equal) Calculate the next instruction s address - PC = PC ( SignExt() x 4 ) else - PC = PC op rs rt immediate 6 bits 5 bits 5 bits 16 bits CS 61C L34 Single Cycle CPU Control I (8)

9 path for Branch Operations beq rs, rt, path generates condition (equal) 4 PC Ext 31 Adder op rs rt immediate 6 bits 5 bits 5 bits 16 bits Adder npc_sel PC CS 61C L34 Single Cycle CPU Control I (9) Inst Address RegWr busw Rs Rt busa Rw Ra Rb -bit Registers busb Cond Already MUX, adder, sign extend, zero Equal?

10 Putting it All Together:A Single Cycle path 4 PC Ext Adder Adder npc_sel Inst Adr PC <21:25> Rs <16:2> Rt Rd <11:15> RegDst Rd Rt Equal 1 Rs Rt RegWr5 5 5 busa busw Rw Ra Rb -bit Registers busb 1 16 Extender <:15> Imm16 Instruction<31:> ALUctr = ALU MemWr In WrEn Adr MemtoReg 1 CS 61C L34 Single Cycle CPU Control I (1) ExtOp ALUSrc

11 An Abstract View of the Implementation Instruction Address Next Address Ideal Instruction PC Rd 5 Instruction Rs 5 Rt 5 Rw Ra Rb -bit Registers A B Control Control Signals Conditions ALU Address In Ideal Out path CS 61C L34 Single Cycle CPU Control I (11)

12 An Abstract View of the Critical Path This affects how much you can overclock your PC! Instruction Address Next Address Ideal Instruction PC Rd 5 Instruction Rs 5 Rw Ra Rb -bit Registers Critical Path (Load Operation) = Delay clock through PC (FFs) + Instruction s Access Time + Register File s Access Time + ALU to Perform a -bit Add + Access Time + Stable Time for Register File Write Rt 5 Imm 16 A B ALU Address In Ideal CS 61C L34 Single Cycle CPU Control I (12)

13 An Abstract View of the Implementation Instruction Address Next Address Ideal Instruction PC Rd 5 Instruction Rs 5 Rt 5 Rw Ra Rb -bit Registers A B Control Control Signals Conditions ALU Address In Ideal Out path CS 61C L34 Single Cycle CPU Control I (13)

14 Recap: A Single Cycle path Rs, Rt, Rd, Imed16 connected to datapath We have everything except control signals npc_sel Rd Rt RegDst 1 Rs Rt RegWr busw Rw Ra Rb -bit Registers 16 busa busb Extender 1 ALUctr ALUSrc Instruction Fetch Unit ALU In Instruction<31:> Rt Zero <21:25> <16:2> Rs Rd MemWr <11:15> WrEn Adr <:15> Imm16 1 MemtoReg ExtOp CS 61C L34 Single Cycle CPU Control I (14)

15 Recap: Meaning of the Control Signals npc_mux_sel: PC < PC + 4 n =next 1 PC < PC {SignExt(Im16), } Later in lecture: higher-level connection between mux and branch cond npc_mux_sel Adder Adder CS 61C L34 Single Cycle CPU Control I (15) 4 PC Ext PC Adr Inst

16 Recap: Meaning of the Control Signals ExtOp: zero, sign MemWr: 1 write memory ALUsrc: regb; MemtoReg: ALU; 1 Mem 1 immed RegDst: rt ; 1 rd ALUctr: add, sub, or RegWr: 1 write register RegDst Rd Rt Equal 1 Rs Rt RegWr busa busw Rw Ra Rb -bit Registers busb 1 16 Extender ALUctr = ALU MemWr In WrEn Adr MemtoReg 1 CS 61C L34 Single Cycle CPU Control I (16) ExtOp ALUSrc

17 Administrivia Final Exam will be here! (25 VLSB) Sat, , 12:3 3:3pm Take EECS Survey this week! (results will be presented to Faculty; you CAN make a difference in your education & undergraduate experience) CS 61C L34 Single Cycle CPU Control I (17)

18 RTL: The Add Instruction op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add rd, rs, rt MEM[PC] Fetch the instruction from memory R[rd] = R[rs] + R[rt] The actual operation PC = PC + 4 Calculate the next instruction s address CS 61C L34 Single Cycle CPU Control I (18)

19 Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory: Instruction = MEM[PC] same for all instructions npc_mux_sel Inst Adr Instruction<31:> PC Ext Adder Adder CS 61C L34 Single Cycle CPU Control I (19) 4 PC

20 RegDst = 1 The Single Cycle path during Add RegWr = 1 busw 31 R[rd] = R[rs] + R[rt] 1 Rd Rt Rs 5 Rw Ra Rb -bit Registers 16 Rt ExtOp = x busb Extender 21 busa ALUctr = Add 1 16 op rs rt rd shamt funct npc_sel= +4 In ALUSrc = 11 Instruction Fetch Unit ALU Zero Instruction<31:> Rt <21:25> 6 WrEn Rs <16:2> MemtoReg = MemWr = Adr Rd <11:15> <:15> Imm16 1 CS 61C L34 Single Cycle CPU Control I (2)

21 Instruction Fetch Unit at the End of Add PC = PC + 4 This is the same for all instructions except: Branch and Jump npc_mux_sel Inst Adr Instruction<31:> 4 Adder Adder 1 PC CS 61C L34 Single Cycle CPU Control I (21)

22 Summary: Single cycle datapath 5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Control is the hard part MIPS makes that easier Instructions same size Processor Control path Source registers always in same place Immediates same size, location Operations always on registers/immediates Input Output CS 61C L34 Single Cycle CPU Control I (23)