EZ-USB FX Technical Reference Manual

Transcription

1 EZ-USB FX Technical Reference Manual Cypress Semiconductor Interface Products Division Avenue of Science Suite 200 San Diego, CA 92128

2 Cypress Disclaimer Agreement The information in this document is subject to change without notice and should not be construed as a commitment by Cypress Semiconductor Corporation Incorporated. While reasonable precautions have been taken, Cypress Semiconductor Corporation assumes no responsibility for any errors that may appear in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Cypress Semiconductor Corporation. Cypress Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Cypress Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Cypress Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Cypress Semiconductor and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Cypress Semiconductor was negligent regarding the design or manufacture of the part. The acceptance of this document will be construed as an acceptance of the foregoing conditions. Chapter 16, 17, and 18 of this databook contain copyrighted material that is the property of Synopsys, Inc., 1998, ALL RIGHTS RESERVED. The EZ-USB FX Technical Reference Manual, Version 1.2. Copyright 2000, Cypress Semiconductor Corporation. All rights reserved.

3 Table of Contents Chapter 1. Introducing EZ-USB FX Introduction EZ-USB FX Block Diagrams The USB Specification Tokens and PIDs Host is Master Receiving Data from the Host Sending Data to the Host USB Direction Frame EZ-USB FX Transfer Types Bulk Transfers Interrupt Transfers Isochronous Transfers Control Transfers Enumeration The USB Core EZ-USB FX Microprocessor ReNumeration EZ-USB FX Endpoints EZ-USB FX Bulk Endpoints EZ-USB FX Control Endpoint Zero EZ-USB FX Interrupt Endpoints EZ-USB FX Isochronous Endpoints Interrupts Reset and Power Management Slave FIFOs GPIF (General Programmable Interface) EZ-USB FX Product Family i

4 (Table of Contents) Chapter 2. EZ-USB FX CPU Introduction Enhancements EZ-USB FX Enhancements EZ-USB FX Register Interface EZ-USB FX Internal RAM I/O Ports Interrupts Power Control SFRs Internal Bus Reset Chapter 3. EZ-USB FX Memory Introduction Memory About 8051 Memory Spaces Expanding EZ-USB FX Memory CS# and OE# Signals Chapter 4. EZ-USB FX Input/Output Introduction I/O Ports Input/Output Port Registers Port Configuration Tables I 2 C-Compatible Controller I 2 C-Compatible Controller Control Bits START STOP LASTRD Status Bits DONE ACK BERR ID1, ID ii Table of Contents

5 (Table of Contents) 4.9 Sending I 2 C-Compatible Data Receiving I 2 C-Compatible Data I 2 C-Compatible Boot Loader SFR Addressing SFR Control of PORTs A-E Chapter 5. EZ-USB FX Enumeration & ReNumeration Introduction The Default USB Device USB Core Response to EP0 Device Requests Port Configuration Bits Firmware Load Enumeration Modes No Serial EEPROM Serial EEPROM Present, First Byte is 0xB Serial EEPROM Present, First Byte is 0xB Configuration Byte ReNumeration Multiple ReNumeration Default Descriptor Chapter 6. EZ-USB FX Bulk Transfers Introduction Bulk IN Transfers Interrupt Transfers EZ-USB FX Bulk IN Example Bulk OUT Transfers Endpoint Pairing Paired IN Endpoint Status Paired OUT Endpoint Status Reusing Bulk Buffer Memory Data Toggle Control Polled Bulk Transfer Example Enumeration Note Bulk Endpoint Interrupts Interrupt Bulk Transfer Example Table of Contents iii

6 (Table of Contents) 6.15 Enumeration Note The Autopointer Chapter 7. EZ-USB FX Slave FIFOs Introduction FIFO Access External Logic FIFO Access ASEL, BSEL in 8-Bit Mode ASEL, BSEL in Double-Byte Mode FIFO Registers FIFO Flags and Interrupts Slave FIFO Register Descriptions FIFO A Read Data A-IN FIFO Byte Count A-IN FIFO Programmable Flag Filling FIFO Emptying FIFO A-IN FIFO Pin Programmable Flag B-IN FIFO Read Data B-IN FIFO Byte Count B-IN FIFO Programmable Flag Filling FIFO Emptying FIFO B-IN FIFO Pin Programmable Flag Input FIFOs A/B Toggle CTL and Flags Input FIFOs A/B Interrupt Enables Input FIFOs A/B Interrupt Requests FIFO A Write Data A-OUT FIFO Byte Count A-OUT FIFO Programmable Flag Filling FIFO Emptying FIFO A-OUT FIFO Pin Programmable Flag B-OUT FIFO Write Data B-OUT FIFO Byte Count B-OUT FIFO Programmable Flag Filling FIFO Emptying FIFO iv Table of Contents

7 (Table of Contents) B-OUT FIFO Pin Programmable Flag Output FIFOs A/B Toggle CTL and Flags Output FIFOs A/B Interrupt Enables Output FIFOs A/B Interrupt Requests FIFO A/B Setup FIFO A/B Control Signal Polarities FIFO Flag Reset FIFO Timing Chapter 8. General Programmable Interface (GPIF) What is GPIF? Applicable Documents and Tools Typical GPIF Interface External GPIF Connections The External GPIF Interface Connecting GPIF Signal Pins to Hardware Example GPIF Hardware Interconnect Internal GPIF Operation The Internal GPIF Engine Global GPIF Configuration Data Bus Width Control Output Modes Synchronous/Asynchronous Mode Programming GPIF Waveforms The GPIF IDLE State Defining Intervals Interval Waveform Descriptor Physical Structure of the Waveform Memories Starting GPIF Waveform Transactions Performing a Single Read Transaction Performing a Single Write Transaction GPIF FIFO Transactions The GPIF_PF Flag Performing a FIFO Read Transaction Performing a FIFO Write Transaction Burst FIFO Transactions Waveform Selector Data/Trigger Registers Table of Contents v

8 (Table of Contents) FIFO Operation Trigger Registers Transaction Count Registers READY Register CTLOUTCFG Register IDLE State Registers Address Register GPIFADRL GPIF_ABORT Register Chapter 9. EZ-USB FX Endpoint Zero Introduction Control Endpoint EP USB Requests Get Status Set Feature Clear Feature Get Descriptor Get Descriptor-Device Get Descriptor-Configuration Get Descriptor-String Set Descriptor Set Configuration Get Configuration Set Interface Get Interface Set Address Sync Frame Firmware Load Chapter 10. EZ-USB FX Isochronous Transfers Introduction Isochronous IN Transfers Initialization IN Data Transfers Isochronous OUT Transfers Initialization OUT Data Transfer Setting Isochronous FIFO Sizes vi Table of Contents

9 (Table of Contents) 10.5 Isochronous Transfer Speed Other Isochronous Registers Disable ISO Zero Byte Count Bits ISO IN Response with No Data Restrictions Near SOF Chapter 11. EZ-USB FX DMA System Introduction DMA Register Descriptions Source, Destination, Transfer Length Address Registers DMA Start and Status Register DMA Synchronous Burst Enables Register Dummy Register External DMA Transfers - Strobes Selection of RD/FRD and WR/FWR DMA Strobes Interaction of DMA Strobe Waveforms and Stretch Bits DMA External Writes DMA External Reads Modes 0 and Modes 2 and Chapter 12. EZ-USB FX Interrupts Introduction USB Core Interrupts Resume Interrupt USB Signaling Interrupts SUTOK, SUDAV Interrupts SOF Interrupt Suspend Interrupt USB RESET Interrupt Bulk Endpoint Interrupts USB Autovectors Autovector Coding I 2 C-Compatible Interrupt In Bulk NAK Interrupt Table of Contents vii

10 (Table of Contents) I 2 C-Compatible STOP Complete Interrupt Slave FIFO Interrupt (INT4) Chapter 13. EZ-USB FX Resets Introduction EZ-USB FX Power-On Reset (POR) Releasing the 8051 Reset RAM Download EEPROM Load External ROM Reset Effects USB Bus Reset EZ-USB FX Disconnect Reset Summary Chapter 14. EZ-USB FX Power Management Introduction Suspend Resume Remote Wakeup Chapter 15. EZ-USB FX Registers Introduction Example Register Formats Other Conventions Slave FIFO Registers FIFO A Read Data A-IN FIFO Byte Count A-IN FIFO Programmable Flag A-IN FIFO Pin Programmable Flag B-IN FIFO Read Data B-IN FIFO Byte Count B-IN FIFO Programmable Flag B-IN FIFO Pin Programmable Flag Input FIFOs A/B Toggle CTL and Flags Input FIFOs A/B Interrupt Enables Input FIFOs A/B Interrupt Requests viii Table of Contents

11 (Table of Contents) FIFO A Write Data A-OUT FIFO Byte Count A-OUT FIFO Programmable Flag A-OUT FIFO Pin Programmable Flag B-OUT FIFO Write Data B-OUT FIFO Byte Count B-OUT FIFO Programmable Flag B-OUT FIFO Pin Programmable Flag Output FIFOs A/B Toggle CTL and Flags Output FIFOs A/B Interrupt Enables Output FIFOs A/B Interrupt Requests FIFO A/B Setup FIFO A/B Control Signal Polarities FIFO Flag Reset Waveform Selector GPIF Done, GPIF IDLE Drive Mode Inactive Bus, CTL States GPIF Address LSB FIFO A IN Transaction Count FIFO A OUT Transaction Count FIFO A Transaction Trigger FIFO B IN Transaction Count FIFO B OUT Transaction Count FIFO B Transaction Trigger GPIF Data H (16-bit mode only) Read or Write GPIF Data L and Trigger Read Transaction Read GPIF Data L, No Read Transaction Trigger Internal READY, Sync/Async, READY Pin States Abort GPIF Cycles General Purpose I/F Interrupt Enable Generic Interrupt Request Input/Output Port Registers D and E Port D Outputs Input Port D Pins Port D Output Enable Port E Outputs Table of Contents ix

12 (Table of Contents) Input Port E Pins Port E Output Enable PORTSETUP Interface Configuration PORTA and PORTC Alternate Configurations Port A Alternate Configuration # Port C Alternate Configuration # DMA Registers Source, Destination, Transfer Length Address Registers DMA Start and Status Register DMA Synchronous Burst Enables Register Select 8051 A/D busses as External FIFO Slave FIFO Interrupt (INT4) Interrupt 4 Autovector Interrupt 4 Autovector Waveform Descriptors Bulk Data Buffers Isochronous Data FIFOs Isochronous Byte Counts CPU Registers Port Configuration Input/Output Port Registers A - C Outputs Pins Output Enables Isochronous Control/Status Registers I 2 C-Compatible Registers Interrupts Endpoint 0 Control and Status Registers Endpoint 1-7 Control and Status Registers Global USB Registers Fast Transfers AUTOPTRH/L AUTODATA SETUP Data x Table of Contents

13 (Table of Contents) Isochronous FIFO Sizes Chapter Introduction Introduction Features Performance Overview Software Compatibility x/805x Feature Comparison Core/DS80C320 Differences Serial Ports Timer Timed Access Protection Watchdog Timer Chapter Architectural Overview Introduction Memory Organization Registers Program Memory Data Memory EZ-USB FX Program/Data Memory Accessing Data Memory Instruction Set Instruction Timing CPU Timing Stretch Memory Cycles (Wait States) Dual Data Pointers Special Function Registers Chapter Hardware Description Introduction Timers/Counters x/805x Compatibility Timers 0 and Mode Mode Mode Mode Table of Contents xi

14 (Table of Contents) Timer Rate Control Timer Timer 2 Mode Control Bit Timer/Counter Mode Bit Timer/Counter Mode with Capture Bit Timer/Counter Mode with Auto-Reload Baud Rate Generator Mode Serial Interface x/805x Compatibility Mode Mode Mode 1 Baud Rate Mode 1 Transmit Mode 1 Receive Mode Mode 2 Transmit Mode 2 Receive Mode Multiprocessor Communications Interrupt SFRs Interrupt Processing Interrupt Masking Interrupt Priorities Interrupt Sampling Interrupt Latency Single-Step Operation Reset Power Saving Modes Idle Mode EZ-USB FX Register Summary... RegSum - 1 xii Table of Contents

15 List of Figures Figure 1-1. CY7C646x3-80NC (80 pin) Simplified Block Diagram Figure 1-2. CY7C646x3-128NC (128 pin) Simplified Block Diagram Figure 1-3. USB Packets Figure 1-4. Two Bulk Transfers, IN and OUT Figure 1-5. An Interrupt Transfer Figure 1-6. An Isochronous Transfer Figure 1-7. A Control Transfer Figure 1-8. What the SIE Does Figure Registers Figure 3-1. EZ-USB FX 8-KB Memory Map - Addresses are in Hexadecimal Figure 3-2. EZ-USB FX 4-KB Memory Map - Addresses are in Hexadecimal Figure 3-3. Unused Bulk Endpoint Buffers (Shaded) Used as Data Memory Figure 3-4. EZ-USB FX Memory Map with EA= Figure 3-5. EZ-USB FX Memory Map with EA= Figure 4-1. EZ-USB FX Input/Output Pin Figure 4-2. Alternate Function is an OUTPUT Figure 4-3. Alternate Function is an INPUT Figure 4-4. Output Port Configuration Registers Figure 4-5. PINSn Registers Figure 4-6. Output Enable Registers Figure 4-7. General I2C-Compatible Transfer Figure 4-8. Addressing an I2C-compatible Peripheral Figure 4-9. I2C-compatible Registers Figure EZ-USB FX Method, sample code Figure SFR Method, sample code Figure EZ-USB FX I/O Structure Figure Use MOVX to Set PA0, sample code Figure Test the State of PORTC, sample code Figure 5-1. Configuration Figure 5-2. USB Control and Status Register Figure 5-3. Disconnect Pin Logic xiii

16 (List of Figures) Figure 5-4. Typical Disconnect Circuit Figure 6-1. Two BULK Transfers, IN and OUT Figure 6-2. Registers Associated with Bulk Endpoints Figure 6-3. Anatomy of a Bulk IN Transfer Figure 6-4. Anatomy of a Bulk OUT Transfer Figure 6-5. Bulk Endpoint Toggle Control Figure 6-6. Example Code for a Simple (Polled) BULK Transfer Figure 6-7. Interrupt Jump Table Figure 6-8. INT2 Interrupt Vector Figure 6-9. Interrupt Service Routine (ISR) for Endpoint 6-OUT Figure Background Program Transfers Endpoint 6-OUT Data to Endpoint 6-IN Figure Initialization Routine Figure Autopointer Registers Figure Use of the Autopointer Figure 7-1. The Four 64-Byte Slave FIFOs Configured for 16-Bit Mode Figure 7-2. Slave FIFOs in 8-Bit Mode Figure 7-3. Double-Byte Mode with A-FIFO Selected Figure 7-4. AINDATA s Role in the FIFO A Register Figure 7-5. FIFO A Read Data Figure 7-6. AINBC s Role in the FIFO A Register Figure 7-7. A-IN FIFO Byte Count Figure 7-8. AINPF s Role in the FIFO A Register Figure 7-9. A-IN FIFO Programmable Flag Figure AINPFPIN s Role in the FIFO A Register Figure A-IN FIFO Pin Programmable Flag Figure BINDATA s Role in the FIFO B Register Figure B-IN FIFO Read Data Figure BINBC s Role in the FIFO B Register Figure B-IN FIFO Byte Count Figure BINPF s Role in the FIFO B Register Figure B-IN FIFO Programmable Flag Figure BINPFPIN s Role in the FIFO B Register Figure B-IN FIFO Pin Programmable Flag Figure FIFO Toggle Mode vs. Normal Mode Diagram Figure Input FIFOs A/B Toggle CTL and Flags xiv List of Figures

17 (List of Figures) Figure Input FIFOs A/B Interrupt Enables Figure Input FIFOs A/B Interrupt Requests Figure AOUTDATA s Role in the FIFO A Register Figure FIFO A Write Data Figure AOUTBC s Role in the FIFO A Register Figure Input FIFOs A/B Interrupt Requests Figure AOUTPF s Role in the FIFO A Register Figure Input FIFOs A/B Interrupt Requests Figure AOUTPFPIN s Role in the FIFO A Register Figure A-OUT FIFO Pin Programmable Flag Figure BOUTDATA s Role in the FIFO B Register Figure B-OUT FIFO Write Data Figure BOUTBC s Role in the FIFO B Register Figure B-OUT FIFO Byte Count Figure BOUTPF s Role in the FIFO B Register Figure B-OUT FIFO Programmable Flag Figure BOUTPFPIN s Role in the FIFO B Register Figure B-OUT FIFO Pin Programmable Flag Figure FIFO Toggle Mode vs. Normal Mode Diagram Figure Output FIFOs A/B Toggle CTL and Flags Figure Output FIFOs A/B Interrupt Enables Figure Output FIFOs A/B Interrupt Requests Figure FIFO A/B Setup Figure A-IN FIFO Double-Byte Mode Figure A-OUT FIFO Delay Synchronous Reads Figure B-OUT FIFO Double-Byte Mode Figure FIFO A/B Control Signal Polarities Figure FIFO Flag Reset Figure Synchronous Write/Read Timing Figure Synchronous Double-byte Write/Read Figure 8-1. GPIF s Place in the FX System Figure 8-2. EZ-USB FX Interfacing to a Peripheral Figure 8-3. Non-Decision Point (NDP) Intervals Figure 8-4. One Decision Point: Wait States Inserted Until RDY0 Goes Low List of Figures xv

18 (List of Figures) Figure 8-5. One Decision Point: No Wait States Inserted: RDY0 is Already Low at Decision Point I Figure 8-6. Ready Register Figure 8-7. IDLE_CTLOUT 0x7826 Register Figure 8-8. GPIF Abort Register Figure 9-1. A USB Control Transfer (With Data Stage) Figure 9-2. Two Interrupts Associated with EP0 CONTROL Transfers Figure 9-3. Registers Associated with EP0 Control Transfers Figure 9-4. Data Flow for a Get_Status Request Figure 9-5. Using Setup Data Pointer (SUDPTR) for Get_Descriptor Requests Figure EZ-USB FX Isochronous Endpoints Figure Isochronous IN Endpoint Registers Figure Isochronous OUT Registers Figure FIFO Start Address Format Figure Using Assembler to Translate the FIFO Sizes to Addresses Figure Data Transfer to Isochronous FIFO (IN8DATA) w/dma Figure ISOCTL Register Figure ZBCOUT Register Figure ISOIN Register Figure Upper Byte of the DMA Source Address Figure Lower Byte of the DMA Source Address Figure Upper Byte of the DMA Destination Address Figure Lower Byte of the DMA Destination Address Figure DMA Transfer Length (0=256 Bytes, 1=1 Byte, =255 Bytes) Figure DMA Start and Status Register Figure Fast Transfer Control Register Figure Synchronous Burst Enables Figure Effect of the RB Bit on DMA Mode 0 Reads Figure Effect of the RB Bit on DMA Mode 1 Reads Figure Effect of the WB Bit on DMA Mode 0 Writes Figure DMAEXTFIFO Register. Data is Don t Care Figure DMA Write Strobe Timing: 4 Modes Selected by FASTXFR[4..3] Figure DMA Read Strobe Timing: 4 Modes Selected by FASTXFR[4..3] Figure USB Interrupts Figure The Order of Clearing Interrupt Requests is Important xvi List of Figures

19 (List of Figures) Figure EZ-USB FX Interrupt Registers Figure SUTOK and SUDAV Interrupts Figure A Start Of Frame (SOF) Packet Figure The Autovector Mechanism in Action Figure I 2 C-Compatible Interrupt Enable Bits and Registers Figure IN Bulk NAK Interrupt Request Register Figure IN Bulk NAK Interrupt Enable Register Figure I 2 C-Compatible Mode Register Figure I 2 C-Compatible Control and Status Register Figure I 2 C-Compatible Data Figure Interrupt 4 Autovector Figure Interrupt 4 Setup Figure EZ-USB FX Resets Figure Suspend-Resume Control Figure EZ-USB FX Suspend Sequence Figure EZ-USB FX Resume Sequence Figure EZ-USB FX RESUME Interrupt Figure USB Control and Status Register Figure Register Description Format Figure FIFO A Read Data Figure A-IN FIFO Byte Count Figure A-IN FIFO Programmable Flag Figure A-IN FIFO Pin Programmable Flag Figure B-IN FIFO Read Data Figure B-IN FIFO Byte Count Figure B-IN FIFO Programmable Flag Figure B-IN FIFO Pin Programmable Flag Figure Input FIFOs A/B Toggle CTL and Flags Figure Input FIFOs A/B Interrupt Enables Figure Input FIFOs A/B Interrupt Requests Figure FIFO A Write Data Figure Input FIFOs A/B Interrupt Requests Figure Input FIFOs A/B Interrupt Requests Figure A-OUT FIFO Pin Programmable Flag Figure B-OUT FIFO Write Data List of Figures xvii

20 (List of Figures) Figure B-OUT FIFO Byte Count Figure B-OUT FIFO Programmable Flag Figure B-OUTFIFO Pin Programmable Flag Figure Output FIFOs A/B Toggle CTL and Flags Figure Output FIFOs A/B Interrupt Enables Figure Output FIFOs A/B Interrupt Requests Figure FIFO A/B Setup Figure FIFO A/B Control Signal Polarities Figure FIFO Flag Reset Figure Waveform Selector Figure GPIF Done, GPIF IDLE Drive Mode Figure Inactive Bus, CTL States Figure CTLOUT Pin Drive Figure GPIF Address Low Figure FIFO A IN Transaction Count Figure FIFO A OUT Transaction Count Figure FIFO A Transaction Trigger Figure FIFO B IN Transaction Count Figure FIFO B OUT Transaction Count Figure FIFO B Transaction Figure GPIF Data H (16-bit mode only) Figure Read or Write GPIF Data L and Trigger Read Transaction Figure Read GPIF Data L, No Read Transaction Trigger Figure Internal READY, Sync/Async, READY Pin States Figure Abort GPIF Cycles Figure Generic Interrupt Enable Figure Generic Interrupt Request Figure Port D Outputs Figure Input Port D Pins Figure Port D Output Enable Register Figure Port E Outputs Figure Input Port E Pins Figure Port E Output Enable Register Figure PORTSETUP Figure Interface Configuration xviii List of Figures

21 (List of Figures) Figure Port A Alternate Configuration # Figure Port C Alternate Configuration # Figure Upper Byte of the DMA Source Address Figure Lower Byte of the DMA Source Address Figure Upper Byte of the DMA Destination Address Figure Lower Byte of the DMA Destination Address Figure DMA Transfer Length (0=256 Bytes, 1=1 Byte, =255 Bytes) Figure DMA Start and Status Register Figure Synchronous Burst Enables Figure Dummy Register Figure Interrupt 4 Autovector Figure Interrupt 4 Setup Figure Waveform Descriptors Figure Bulk Data Buffers Figure Isochronous Data FIFOs Figure Isochronous Byte Counts Figure CPU Control and Status Register Figure I/O Port Configuration Registers Figure Port A Outputs Figure Port B Outputs Figure Port C Outputs Figure Port A Pins Figure Port B Pins Figure Port C Pins Figure Port A Output Enable Figure Port B Output Enable Figure Port C Output Enable Figure Isochronous OUT Endpoint Error Register Figure Isochronous Control Register Figure Zero Byte Count Register Figure I 2 C-Compatible Transfer Registers Figure I 2 C-Compatible Mode Register Figure Interrupt Vector Register Figure IN/OUT Interrupt Request (IRQ) Registers Figure USB Interrupt Request (IRQ) Registers List of Figures xix

22 (List of Figures) Figure IN/OUT Interrupt Enable Registers Figure USB Interrupt Enable Register Figure Breakpoint and Autovector Register Figure IN Bulk NAK Interrupt Request Register Figure IN Bulk NAK Interrupt Enable Register Figure IN/OUT Interrupt Enable Registers Figure Port Configuration Registers Figure IN Control and Status Registers Figure IN Byte Count Registers Figure OUT Control and Status Registers Figure OUT Byte Count Registers Figure Setup Data Pointer High/Low Registers Figure USB Control and Status Registers Figure Data Toggle Control Register Figure USB Frame Count High/Low Registers Figure Function Address Register Figure USB Endpoint Pairing Register Figure IN/OUT Valid Bits Register Figure Isochronous IN/OUT Endpoint Valid Bits Register Figure Fast Transfer Control Register Figure Auto Pointer Registers Figure SETUP Data Buffer Figure SETUP Data Buffer Figure Features Figure /Standard 8051 Timing Comparison Figure Internal RAM Organization Figure CPU Timing for Single-Cycle Instruction Figure Timer 0/1 - Modes 0 and Figure Timer 0/1 - Mode Figure Timer 0 - Mode Figure Timer 2 - Timer/Counter with Capture Figure Timer 2 - Timer/Counter with Auto Reload Figure Timer 2 - Baud Rate Generator Mode Figure Serial Port Mode 0 Receive Timing - Low Speed Operation Figure Serial Port Mode 0 Receive Timing - High Speed Operation xx List of Figures

23 (List of Figures) Figure Serial Port Mode 0 Transmit Timing - Low Speed Operation Figure Serial Port Mode 0 Transmit Timing - High Speed Operation Figure Serial Port 0 Mode 1 Transmit Timing Figure Serial Port 0 Mode 1 Receive Timing Figure Serial Port 0 Mode 2 Transmit Timing Figure Serial Port 0 Mode 2 Receive Timing Figure Serial Port 0 Mode 3 Transmit Timing Figure Serial Port 0 Mode 3 Receive Timing List of Figures xxi

24 xxii List of Figures

25 List of Tables Table 1-1. USB PIDs Table 1-2. EZ-USB FX Family Table 2-1. EZ-USB FX Interrupts Table 2-2. Added Registers and Bits Table 4-1. Port A Configuration Table 4-2. Port B Configuration Table 4-3. Port C Configuration Table 4-4. Port D Bits Table 4-5. Port E Bits Table 4-6. Strap Boot EEPROM Address Lines to These Values Table 4-7. Results of Power-On I2C-Compatible Test Table 4-8. EZ-USB FX Special Function Registers* Table 5-1. EZ-USB FX Default Endpoints Table 5-2. How the USB Core Handles EP0 Requests When RENUM= Table 5-3. Firmware Download Table 5-4. Firmware Upload Table 5-5. USB Core Action at Power-Up Table 5-6. EZ-USB FX Device Characteristics, No Serial EEPROM Table 5-7. EEPROM Data Format for B4 Load Table 5-8. EEPROM Data Format for B6 Load Table 5-9. USB Default Device Descriptor Table USB Default Configuration Descriptor Table USB Default Interface 0, Alternate Setting 0 Descriptor Table USB Default Interface 0, Alternate Setting 1 Descriptor Table Default Interface 0, Alternate Setting 1, INT Endpoint Descriptor Table Default Interface 0, Alternate Setting 1, Bulk Endpoint Descriptors Table Default Interface 0, Alternate Setting 1, ISO Endpoint Descriptors Table USB Default Interface 0, Alternate Setting 2 Descriptor Table Default Interface 0, Alternate Setting 1, INT Endpoint Descriptor Table Default Interface 0, Alternate Setting 2, Bulk Endpoint Descriptors Table Default Interface 0, Alternate Setting 2, ISO Endpoint Descriptors xxiii

26 (List of Tables) Table 6-1. EZ-USB FX Bulk, Control, and Interrupt Endpoints Table 6-2. Endpoint Pairing Bits (in the USB PAIR Register) Table 6-3. EZ-USB FX Endpoint 0-7 Buffer Addresses Table INT2 Interrupt Vector Table 6-5. Byte Inserted by USB Core at Location 0x45 if AVEN= Table 7-1. Autovector for INT4* Table 7-2. INT4 Autovectors Table 7-3. Filling FIFO Table 7-4. Emptying FIFO Table 7-5. Filling FIFO Table 7-6. Emptying FIFO Table 7-7. Filling FIFO Table 7-8. Emptying FIFO Table 7-9. Filling FIFO Table Emptying FIFO Table 8-1. GPIF Pin Descriptions Table 8-2. Example GPIF Hardware Interconnect Table 8-3. CTL Output Modes Table 8-4. Control Outputs (CTLn) During the IDLE State Table 8-5. Waveform Memory Types Table 8-6. Waveform Memory Descriptors Table 8-7. Selecting the GPIF_PF Flag Table 8-8. Addresses of Transaction Count Registers Table 9-1. The Eight Bytes in a USB SETUP Packet Table 9-2. How the 8051 Handles USB Device Requests (RENUM=1) Table 9-3. Get Status-Device (Remote Wakeup and Self-Powered Bits) Table 9-4. Get Status-Endpoint (Stall Bits) Table 9-5. Get Status-Interface Table 9-6. Set Feature-Device (Set Remote Wakeup Bit) Table 9-7. Set Feature-Endpoint (Stall) Table 9-8. Clear Feature-Device (Clear Remote Wakeup Bit) Table 9-9. Clear Feature-Endpoint (Clear Stall) Table Get Descriptor-Device Table Get Descriptor-Configuration Table Get Descriptor-String xxiv List of Tables

27 (List of Tables) Table Set Descriptor-Device Table Set Descriptor-Configuration Table Set Descriptor-String Table Set Configuration Table Get Configuration Table Set Interface (Actually, Set Alternate Setting AS for Interface IF) Table Get Interface (Actually, Get Alternate Setting AS for interface IF) Table Sync Frame Table Firmware Download Table Firmware Upload Table Isochronous Endpoint FIFO Starting Address Registers Table Addresses for RD# and WR# vs. ISODISAB Bit Table DMA Sources and Destinations Table Legends Used in Table Table DMA External RAM Control Table Effect of Stretch Values on a Write Strobe Table Effect of Stretch Values on a Write Strobe Table EZ-USB FX Interrupts Table JUMP Instruction Table A Typical USB Jump Table Table Autovector for INT4* Table INT4 Autovectors Table EZ-USB FX States After Power-On Reset (POR) Table EZ-USB FX States After a USB Bus Reset Table Effects of an EZ-USB FX Disconnect and Re-connect Table Effects of Various EZ-USB FX Resets ( U Means Unaffected ) Table Port A Alternate Functions When GSTATE= Table Pin Configurations Based on IFCONFIG[1..0] Table Port A Bit Table Port A Bit Table Port C Bit Table Port C Bit Table Port C Bit Table Port C Bit Table Port C Bit List of Tables xxv

28 (List of Tables) Table Port C Bit Table Port C Bit Table Bulk Endpoint Buffer Memory Addresses Table Isochronous Endpoint FIFO Register Addresses Table Isochronous Endpoint Byte Count Register Addresses Table I/O Pin Alternate Functions Table Control and Status Register Addresses for Endpoints Table Isochronous FIFO Start Address Registers Table /Standard 8051 Speed Comparison Table Features of 8051 Core & Common 803x/805x Configurations Table Legend for Instruction Set Table Table Instruction Set Table Data Memory Stretch Values Table Special Function Registers Table Special Function Register Reset Values Table PSW Register - SFR D0h Table Timer/Counter Implementation Comparison Table TMOD Register SFR 89h Table TCON Register SRF 88h Table CKCON Register SRF 8Eh Table Timer 2 Mode Control Summary Table T2CON Register SFR C8h Table Serial Port Modes Table SCON0 Register SFR 98h Table SCON1 Register SFR C0h Table Timer 1 Reload Values for Common Serial Port Mode 1 Baud Rates Table Timer 2 Reload Values for Common Serial Port Mode 1 Baud Rates Table IE Register SFR A8h Table IP Register SFR B8h Table EXIF Register SFR 91h Table EICON Register SFR D8h Table EIE Register SFR E8h Table EIP Register SFR F8h Table Interrupt Natural Vectors and Priorities Table Interrupt Flags, Enables, and Priority Control Table PCON Register SFR 87h xxvi List of Tables

29 Chapter 1. Introducing EZ-USB FX 1.1 Introduction Like a well designed automobile or appliance, a USB peripheral s outward simplicity hides internal complexity. There s a lot going on under the hood of a USB device, which gives the user a new level of convenience. For example: A USB device can be plugged in anytime, even when the PC is turned on. When the PC detects that a USB device has been plugged in, it automatically interrogates the device to learn its capabilities and requirements. From this information, the PC automatically loads the device s driver into the operating system. When the device is unplugged, the operating system automatically logs it off and unloads its driver. USB devices do not use DIP switches, jumpers, or configuration programs. There is never an IRQ, DMA, MEMORY, or I/O conflict with a USB device. USB expansion hubs make the bus available to dozens of devices. USB is fast enough for printers, CD-quality audio, and scanners. USB is defined in the Universal Serial Bus Specification Version 1.1, a 268-page document describing in elaborate detail all aspects of a USB device. The USB Specification is available at The EZ-USB FX Technical Reference Manual describes the EZ-USB FX chip along with USB topics that provide help in understanding the USB Specification. The Cypress Semiconductor EZ-USB FX is a compact, integrated circuit that provides a highly integrated solution for a USB peripheral device. Three key EZ-USB FX features are: The EZ-USB FX family provides a soft (RAM-based) solution that allows unlimited configuration and upgrades. The EZ-USB FX family delivers full USB throughput. Designs that use EZ-USB FX are not limited by number of endpoints, buffer sizes, or transfer speeds. The EZ-USB FX family does much of the USB housekeeping in the USB core, simplifying code and accelerating the USB learning curve. Chapter 1. Introducing EZ-USB FX Page 1-1

30 EZ-USB FX Technical Reference Manual This chapter introduces key USB concepts and terms to make reading this Technical Reference Manual easier. 1.2 EZ-USB FX Block Diagrams +5V D+ D- GND USB Connector USB Transceiver Serial Interface Engine (SIE) bytes bytes USB Interface Program & Data RAM General Purpose Microprocessor EZ-USB GPIF Slave FIFOs IO Ports 16 Figure 1-1. CY7C646x3-80NC (80 pin) Simplified Block Diagram The Cypress Semiconductor EZ-USB FX chip packs the intelligence required by a USB peripheral interface into a compact, integrated circuit. As Figure 1-1 illustrates, an integrated USB transceiver connects to the USB bus pins D+ and D-. A Serial Interface Engine (SIE) decodes and encodes the serial data and performs error correction, bit stuffing, and other signaling-level details required by USB. Ultimately, the SIE transfers data bytes to and from the USB interface. The internal microprocessor is an enhanced 8051 with fast execution time and added features. It uses internal RAM for program and data storage, making the EZ-USB FX family a soft solution. The USB host downloads 8051 program code and device personality into RAM over the USB bus, and then EZ-USB FX re-connects as the custom device, as defined by the loaded code. The EZ-USB FX family uses an enhanced SIE/USB interface (USB Core), which has the intelligence to function as a full USB device, even before the 8051 runs. The enhanced core simplifies 8051 code by implementing much of the USB protocol, itself. EZ-USB FX chips operate at 3.3V. This simplifies the design of bus-powered USB devices, since the 5V power available in the USB connector (USB Specification allows power to be as low as 4.4V) can drive a 3.3V regulator to deliver clean, isolated power to the EZ-USB FX chip. Page 1-2 EZ-USB FX Technical Reference Manual v1.2

31 +5V D+ D- GND USB Connector USB Transceiver Serial Interface Engine (SIE) bytes bytes USB Interface Program & Data RAM General Purpose Microprocessor EZ-USB GPIF Slave FIFOs IO Ports Address Bus Data Bus External Memory 16 Figure 1-2. CY7C646x3-128NC (128 pin) Simplified Block Diagram Figure 1-2 illustrates the CY7C646x3-128NC, a 128-pin version of the EZ-USB FX family. In addition to the 40 I/O pins, it contains a 16-bit address bus and an 8-bit data bus for external memory expansion. Slave interface FIFOs and a General Programmable Interface (GPIF) controller provide a flexible, high-bandwidth interface to external logic. Also included, the DMAEXTFIFO register provides legacy support for invoking the fast transfer mode available on the EZ-USB Series This allows data to move directly between external logic and internal USB FIFOs. This, along with abundant endpoint resources, allows the EZ-USB FX family to support transfer bandwidths to external logic that exceed the USB delivery/consumption rate. 1.3 The USB Specification The Universal Serial Bus Specification Version 1.1 is available on the Internet at Published in January 1998, the USB Specification is the work of a founding committee of seven industry heavyweights: Compaq, DEC, IBM, Intel, Microsoft, NEC, and Northern Telecom. This impressive list of developers secures USB as the low-to-medium speed PC connection method of the future. A glance at the USB Specification makes it immediately apparent that USB is not nearly as simple as the customary serial or parallel port. The USB Specification uses new terms like endpoint, isochronous, and enumeration, and finds new uses for old terms like configuration, interface, and interrupt. Woven into the USB fabric is a software abstraction model that deals with things such as pipes. The USB Specification also contains detail about the connector types and wire colors. Chapter 1. Introducing EZ-USB FX Page 1-3