Computer and Hardware Architecture I. Benny Thörnberg Associate Professor in Electronics

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1 Computer and Hardware Architecture I Benny Thörnberg Associate Professor in Electronics

2 Hardware architecture Computer architecture The functionality of a modern computer is so complex that no human can grasp it without first organize it into smaller units We define computer architecture as a set of rules and methods that describes a programming model, organization and implementation of a computer system We define hardware architecture as the description of a set of physical or logical components and their interrelationships There exist lots of hardware components that perform complex computations without being programmable, e.g. communication interfaces for Ethernet or usb.

3 Computer architecture Description of computer architecture can be further divided into two layers Programming model Organization and Implementation The programming model is the processor s window to the programmer, describing a toolbox that can be used to perform computations. Typically, this part of the computer architecture has a long lifetime. The organization and implementation is describing how computations are being done in hardware. This description can be optimized and changed while still being able to execute the same machine code and using the same set of registers

4 Computer architecture Programming model Instruction Set Architecture Instruction set Instruction representation Set of registers Operating modes Organization and Implementation Hardware architecture Memory system Instruction pipeline Internal and external communication busses

5 The von Neumann architecture System bus CPU Memory Bus interface ALU ar ir pc Execution unit Control unit I/O System IO-channels I/O System IO-channels ar = accumulator register ir = instruction register pc = program counter

6 Execution in the von Neumann computer Execute: Y=a+b (ADD Y, a, b) Address bus set to pc, ir is loaded with value from data bus Decode instruction Load ar with a Add ar with b Save ar in Y This sequence is called microprogram System bus CPU Memory Bus interface ALU ar ir pc Execution unit Control unit I/O System IO-channels I/O System IO-channels

7 The von Neumann architecture The von Neumann architecture has only one memory area (one single system bus) code is executed sequentially An instruction in the von Neumann architecture is executed in the following sequence Read instruction code, decode, read operand, perform op., write result Simple architecture for computer engineers, programmers and compiler designers Inefficient, only 20% of the execution time is used for computation (ALU operations) The most common processor architecture (but modified) What can be done to make this architecture more efficient? Pre-fetch, cache, pipelining, branch prediction, DMA CPU Memory I/O System bus

8 Harvard architecture Two busses One for instructions One for data Which means that instructions and data can be loaded at the same time. Increased speed Programmemory Program system bus CPU Data memory I/O Data system bus

9 Modified Harvard architecture Commonly used for modern microcontrollers and processors Mix of Harvard internally and von Neumann externally Memory for program and data Program cache memory CPU Program system bus Data system bus Data cache memory I/O

10 Different parts of a computer system What can be found in a computer system? Processor (CPU, Central Processing Unit) Memory Peripheral I/O System bus, used for communication with external units When we have a single chip that contains all those parts, this device is then referred to as microcontroller CPU I/O-enhet Minne RAM ROM Omvärden/ Användare

11 Mainly two types of processors CISC (Complex Instruction Set Computer) Lots of instructions for various computations Makes life easier for the designers of compilers and assembler programs A few instructions are used for most programs which makes the processor slow and power hungry Lots of information is needed to describe the functionality of an instruction E.g. Motorola MC68040 having 200 instructions and 18 addressing modes RISC (Reduced Instruction Set Computer) Fewer and simpler instructions All instructions execute in one single clock cycle Faster execution of programs Only one single code word needed to describe one instruction E.g. Alpha, ARM, and MIPS

12 Execution pipelining for RISC processors This is an example of a five stage pipeline Fetch next instruction Decode and fetch operands Perform arithmetic operation Memory read or write Store results Throughput is one instruction per clock cycle Latency is five clock cycles for instructions to conclude This pipeline exploits parallelism in instruction execution such that speed is increased

13 Execution pipelining for RISC processors Situations referred to as hazards can prevent an instruction from being executed at scheduled clock cycles: Structural hazards arises from resource conflicts when overlapping instructions need access to the same hardware e.g co-processor, Data hazards data dependencies can prevent overlapping instructions to execute, Control hazards data dependent branches or subroutine calls makes it difficult to know which instruction should be fetched.

14 Pipelining and instruction stalls An instruction might need to be stalled while waiting for result from another previous instruction Instructions issued later than the stalled instruction must also be stalled and no more instructions are issued Instructions issued earlier than the stalled instruction must proceed in order to resolve the data dependency This means that the control logic of the instruction pipeline must be able to analyze data dependencies on the fly

15 Pipelining and instruction stalls Data hazards Clk Mnemonic Fetch instruction Decode and fetch operands ALU operation Memory read or write Write result 1 ADD R2,R3 -> R1 Inst K Inst K-1 Inst K-2 Inst K-3 Inst K-4 2 SUB R4,R1 -> R5 Inst K+1 Inst K Inst K-1 Inst K-2 Inst K-4 3 XOR R2,R3 -> R1 Inst K+2 Stall Inst K Inst K-1 Inst K-2 4 No instruction fetch Stall Stall Stall Inst K Inst K-1 5 No instruction fetch Stall Stall Stall Stall Inst K 6 No instruction fetch Stall Inst K+1 Stall Stall Stall 7 INV R1 -> R1 Inst K+3 Inst K+2 Inst K+1 Stall Stall 8 INV R1 -> R1 Inst K+4 Inst K+3 Inst K+2 Inst K+1 Stall 9 INV R1 -> R1 Inst K+5 Inst K+4 Inst K+3 Inst K+2 Inst K+1 10 INV R1 -> R1 Inst K+6 Inst K+5 Inst K+4 Inst K+3 Inst K+2

16 Pipelining and instruction stalls Mitigate data hazards Fetch next instruction Decode and fetch operands Perform arithmetic operation Memory read or write Store results Blue arrow shows an example of a forwarding path that can resolve data dependencies without stalling an instruction

17 Memory mapped I/O I/O units are decoded exactly the same way as memory and I/O is thus belonging to the same address space as memory Data from I/O units are accessed using the same instructions as for memory access Address bus Data bus Control signals Memory CPU I/O units

18 Port mapped I/O Separate address space for I/O units Special instructions for access of I/O units Address bus Data bus Control signals Memory CPU I/O units Data bus and a subset of the address bus I/O control signals

19 Synchronization of I/O Polling Polling The I/O port is read at a predefined interval Also called programmed I/O Polling happens synchronous with the rest of the program control flow

20 Synchronization of I/O Polling System bus MPU I/O 1 I/O 2 I/O N Does I/O 1 need service? No Yes Service I/O 1 Polling of several I/O units All I/O units are checked at a predefined interval for need of service If needed, the service program associated with a specific I/O will be executed The rest of the processor time is assigned to execution of main program Simple implementation Lots of the processor capacity is needed for synchronization which in turn leads to high power consumption Does I/O 2 need service? No Does I/O N need service? No Main program Yes Yes Service I/O 2 Service I/O N

21 Synchronization of I/O Timed Timed Interval between events is known Accessing I/O units a certain time after an event happened Very little processor capacity is used for synchronization Requires a real time OS T period

22 Synchronization of I/O Interrupt Interrupt An event occurring at an I/O unit forces the normal program flow to be interrupted by activating any of the processor's interrupt request input signals. A dedicated service routine is then executed for that event. The service routine is executed asynchronously with respect to the main program Very little processor capacity is used for synchronization Enables the processor to enter a power down mode for later wakeup at an external event. This leads to low power consumption. Additional hardware dedicated for interrupt handling is required Start execution of interrupt service routine Start execution of interrupt service routine

23 Synchronization of I/O Interrupt Address bus The I/O unit signals to the processor that it needs service by activating control signal Interrupt Request. CPU IACK V Data bus Control signals Memory The processor interrupts its current computations and signals to the I/O unit that it excepts the interrupt request by activating control signal Interrupt Acknowledge. The I/O unit identifies itself by sending a Vector on the data bus IRQ I/O units The processor runs the service routine dedicated for the I/O unit who activated the request The processor returns to previous computations If interrupt vectors are not used, then the processor needs to poll every I/O unit to find out which one requested the interrupt

24 Synchronization of I/O DMA DMA Direct Memory Access The processor is disconnected The I/O unit gets an address space assigned to it It is faster to transfer a block of data as a single intensive burst Or data transfer can run in background, interleaved with the processor bus cycles Address bus Data bus Control signals Memory CPU I/O units

25 Synchronization of I/O DMA Address buss Data buss Control buss bus_switch_1 bus_switch_2 bus_switch_3 CPU ROM RAM IRQ BR BG DMAC Address register Transfer count Control Status Peripherial ACK Ready DMA Grant DMA Request IRQ Opening switch 1, closing switch 2 and 3 allows the DMA controller to handle data transfers between the peripheral I/O and memory. Busy Done

26 Software drivers A software driver is one or more functions used to access a peripheral hardware component The software driver hides technical details of this hardware component An application software is communicating with the hardware component through an Application Program Interface (API), which is typically a set of C functions

27 Drivrutiner

28 Why cache memories The memory wall Performance CPU 10 1 Memory Year Speed has increased much faster for CPUs than for memories over time

29 What is a cache Data path Registers Higher speed Level 1 cache Larger More energy/access Level 2 cache Memory External storage e.g server, disk A hierarchy of memories of different sizes and speeds Accesses to smaller memories are both faster and less power consuming Memory accesses with temporal and spatial locality are preferably done from a smaller memory such that accesses become faster and less power hungry 29

30 Spatial and temporal locality int main() { int i; int a[2048]; signed b[1024]; for( i=1; i<1024; i=i+1) { b(i) = ( a(i) + a(i+1) + a(i+2) + a(i+3) + a(i+4) ) / 4; } return(0); } a(1) a(2) a(3) a(4) a(5) a(6) a(7) a(8) a(9) a(10) a(11) a(12) a(13) a(14) a(15) b(1) a(2) to a(4) is reused input data from previous computation b(2) b(3) a(4) to a(6) is reused input data from previous computation b(4)

31 Cache memories in computers CPU Data Address Main Memory Cache controller Hit Cache memory Miss The cache controller uses a cache tag memory to keep track of the parts of main memory storage that has a local copy in the cache Content of cache is concurrently updated according to spatial and temporal locality of memory accesses 31

32 Direct mapped cache memory Cache tag memory 32

33 Direct mapped cache memory 33

34 Associative cache memory Cache tag memory is of type associative 34

35 Associative memories N bit input CAM A Content Addressable Memory (CAM) or associative memory can associate an N bit input word with an M bit output word All memory cells are searched in parallel for possible matching with input word M bit output hit miss These memories are expensive to manufacture and are not feasible for large number of associations 35

36 Set associative cache memory 36

37 Pixel Steam Input 1 1 p11 p10 p1-1 p01 p00 p0-1 p-11 p-10 p-1-1 Application specific memory hierarchy for FPGA Frame delay This is an example of an application specific memory hierarchy s11 s10 s1-1 s01 s00 s0-1 s-11 s-10 s-1-1 designed for three levels and suitable for FPGA N C (N R -2) Control flow is known at compile time as in this case for spatio- N C -2 temporal video processing Frame delay r11 r10 r1-1 r01 r00 r0-1 r-11 r-10 r-1-1 Pixel Stream Input Frame delay N C N R N C N C p11 p10 p1-1 p01 p00 p0-1 p-11 p-10 p-1-1 L2 L1 N C = Number of columns N R = Number of rows N C N C L2 Frame delay N C N R s11 s10 s1-1 s01 s00 s0-1 s-11 s-10 s-1-1 L1 L3 N C N C L L1 r11 r10 r1-1 r01 r00 r0-1 r-11 r-10 r

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