Midrange 8b PIC Microcontrollers. ECE Senior Design 14 February 2017

Transcription

1 Midrange 8b PIC Microcontrollers ECE Senior Design 14 February 2017

2 Harvard vs. Von Neumann Harvard Architecture Program Memory 14-bit Bus CPU 8-bit Bus Data Memory Harvard architecture Separate busses for program memory and data memory Improved operating bandwidth Allows for different bus widths Used in many microcontrollers Von Neumann Architecture CPU 8-bit Bus Program & Data Memory Von Neumann architecture Program and data stored in same memory Used in many microprocessors

3 RISC vs. CISC generalizations RISC Reduced Instruction Set Computer Emphasis on Software Most instructions execute in a single clock cycle Larger code sizes CISC Complex Instruction Set Computer Emphasis on Hardware Instructions require multiple clock cycles Smaller code size

4 What the does PIC stand for anyway? PIC Peripheral Interface Controller The original PIC was designed to be a Peripheral Interface Controller for 6502 microcontroller from Rockwell late 70's.

5 Why did we choose Microchip PIC Family of Microcontrollers? Free development software MPLAB IDE (Includes a Simulator) Low cost development hardware (Boards starting at $10) Devices are easy to obtain through distributors and can be sampled A wide range of devices are available with varying feature sets Microchip is in continuous development of new PIC devices Has a large online support community Wide acceptance in industry over 15 Billion units shipped (1B/yr)

6 Datasheet Feature Page 16F18324 Datasheet PIC16F18324 Processor Structure of the PIC16F18324 Device Pins for the PIC16F18324

7 Microcontroller Block Diagram

8 GPIO PIC16F18324 Port A (RA0, RA1, RA2, RA3, RA4, RA5) Port C (RC0, RC1, RC2, RC3, RC4, RC5)

9 Generic Port Structure

10 PORTA Register

11 TRISIA Register

12 LATA Register

13 ANSELA Register

14 Lighting an LED

15 Program Memory Map and Stack Reset Vector h Interrupt Vector h Program Memory Stack Depth - 16

16 Data Memory (32 Banks total)

17 The W Register (working register) reg1, w ; Move a file registers contents into the W register addwf reg2, w ; Place result in W register Program Memory Program Address 13 Program Counter 14 Instruction Instruction Register Direct Addr. 7 File Registers Data Bus 8 Instruction Decode and Control ALU 8 W Register

18 The Status Register Program Memory Program Address 13 Program Counter 14 Instruction Instruction Register Direct Addr. 7 File Registers Data Bus 8 Instruction Decode and Control Status Register result 3 ALU 8 W Register

19 The Status bits Arithmetic Status of the ALU Reset Status WDT and PD

20 Pipelining of Instructions Most instructions Execute in a single Processor Cycle A Processor Cycle is 4 Clock Cycles Using a 4MHz oscillator each processor cycle is 1MHz This results in a 1us execution time

21 Non-Sequential Address Read Exception to the one processor cycle per instruction is for Branching operations The Pipeline will be broken on a non-sequential address read Branching instructions require two processor cycles to execute

22 Instruction Pipelining Pre-ed Instruction Executing Instruction movlw 0x05 - Instruction Cycles Example Program MAIN movlw 0x05 movwf REG1 call SUB1 addwf REG2 T SUB1 SUB2 PORTB,w PORTC,w

23 Instruction Pipelining Pre-ed Instruction Executing Instruction movwf REG1 movlw 0x05 Instruction Cycles Example Program MAIN movlw 0x05 movwf REG1 call SUB1 addwf REG2 T0 T1 Execute SUB1 SUB2 PORTB,w PORTC,w

24 Instruction Pipelining Pre-ed Instruction Executing Instruction call SUB1 movwf REG1 Instruction Cycles Example Program MAIN movlw 0x05 movwf REG1 call SUB1 addwf REG2 T0 T1 T2 Execute Execute Time to execute normal instruction SUB1 SUB2 PORTB,w PORTC,w

25 Instruction Pipelining Pre-ed Instruction Executing Instruction addwf REG2 call SUB1 Instruction Cycles Example Program MAIN movlw 0x05 movwf REG1 call SUB1 addwf REG2 T0 T1 T2 T3 Execute Execute Execute SUB1 SUB2 PORTB,w PORTC,w

26 Instruction Pipelining Pre-ed Instruction Executing Instruction PORTB,w call SUB1 Instruction Cycles Example Program MAIN movlw 0x05 movwf REG1 call SUB1 addwf REG2 T0 T1 T2 T3 T4 Execute Execute Execute Flush Time to execute call instruction includes pipeline flush SUB1 SUB2 PORTB,w PORTC,w

27 Instruction Pipelining Pre-ed Instruction Executing Instruction PORTB,w Instruction Cycles Example Program MAIN movlw 0x05 movwf REG1 call SUB1 addwf REG2 T0 T1 T2 T3 T4 T5 Execute Execute Execute Flush SUB1 SUB2 PORTB,w PORTC,w Execute

28 Instruction Pipelining Pre-ed Instruction Executing Instruction PORTC,w Instruction Cycles Example Program MAIN movlw 0x05 movwf REG1 call SUB1 addwf REG2 T0 T1 T2 T3 T4 T5 Execute Execute Execute Flush T SUB1 SUB2 PORTB,w PORTC,w Execute Execute

29 Instruction Pipelining Pre-ed Instruction Executing Instruction addwf REG2 Instruction Cycles Example Program MAIN movlw 0x05 movwf REG1 call SUB1 addwf REG2 T0 T1 T2 T3 T4 T5 Execute Execute Execute Flush T6 T SUB1 SUB2 PORTB,w PORTC,w Execute Execute Flush

30 Blinking an LED time wasting loop bad Initialize Main Call Count_Time Call Toggle_LED Goto Main Count_Time ToggleLED Kill some time Looping in here Change state of LED