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1 SRM UNIVERSITY FACULTY OF ENGINEERING AND TECHNOLOGY SCHOOL OF COMPUTING DEPARTMENT OF SOFTWARE ENGINEERING COURSE PLAN Course Code : SE1002 Course Title : COMPUTER ORGANIZATION AND ARCHITECTURE Semester : III Course Time : July-Dec 2014 Day Hour Timing pm pm am am Location: :UNIVERSITY BUILDING Faculty Details: Section Name Office Office hour Mail id A P.Deivanai UB,12 th floor Mon Fri deivanai.divya@gmail.com Required Text Books 1. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, 5th Edition Computer Organization, McGraw-Hill, Ghosh T.K, Computer Organization and Architecture, Tata McGraw-Hill, Reference Books 1. William Stallings, Computer Organization and Architecture Designing for Performance, 7th Edition, Pearson Education, Behrooz parahami, Computer Architecture Oxford University Press-Eighth Impression, David A. Patterson and John Hennessy L, Computer Architecture-A Quantitative Approach, Fifth edition, Elsevier, a division of reed India Private Limited, Prerequisite Nil OBJECTIVES 1. To have an understanding of the basic structure and operation of a digital computer. 2. Discuss in detail the operation of the arithmetic unit including the algorithms & implementation of fixed-point and floating-point addition, subtraction, multiplication & division. 3. To study in detail the different types of control and the concept of pipelining. 4. To study the hierarchical memory system including cache memories and virtual memory 5. To study the different ways of communicating with I/O devices and its interfaces.

2 Assessment Details Cycle Test I : 10marks Cycle Test II : 10 Marks Model Exam : 20 Marks Surprise Test II : 5 Marks Attendance : 5 Marks S.NO DATE TEST TOPICS DURATION 1 CYCLE TEST 1 UNIT I & II 2 PERIODS 2 CYCLE TEST 2 UNIT III & IV 2 PERIODS 3 MODEL EXAM ALL 5 UNITS 3 HOURS Outcomes Students who have successfully completed this course will have full understanding of the following concepts Course Outcome To Learn : Basic concepts of computer structure and Functional units Input /Output Organisation, Memory system in computers Program Outcome An ability to understand the basic structure Of computers An ability to understand the operation of Arithmetic and processing units An ability to understand the concepts and types of memory system DETAILED SESSION PLAN UNIT I BASIC STRUCTURE OF COMPUTERS Functional units basic operational concepts Bus Structures Software performance memory location and addresses memory operations Instruction and instruction sequencing Addressing modes Assembly Language Basic I/O operations Sessio n No. 1 Topics to be covered Functional units basic operational concepts Time (min) Ref Teaching Method 2 Bus Structures 3 Software performance 4 Memory location and addresses 5 Memory operations Testing Method 6 Instruction and instruction sequencing 7 Addressing modes, Assignment 8 Assembly Language 9 Basic I/O operations

3 UNIT 2 ARITHMETIC UNIT Addition and subtraction of signed numbers design of fact adders Multiplication of positive numbers Signed operand multiplication and fast multiplication Integer Division Floating point numbers and its operations. 10 Addition of signed numbers 11 Subtraction of signed numbers 12 design of fact adders 13 Multiplication of positive numbers 14 Signed operand multiplication 15 fast multiplication 16 Integer Division, Assignment 17 Floating point numbers and its operations. 18 Floating point numbers operations. UNIT III BASIC PROCESSING UNIT Fundamental concepts Execution of a complete instruction Multiple bus organisation Hardwired control Micro programmed control Pipelining Basic concept Data Hazards Instruction Hazards Influence on Instruction sets Data path and control consideration. 19 Fundamental concepts 20 Execution of a complete instruction 21 Multiple bus organisation, Hardwired control 22 Micro programmed control 23 Pipelining 24 Data Hazards 25 Instruction Hazards 26 Influence on Instruction sets, Assignment

4 27 Data path and control consideration. UNIT IV MEMORY SYSTEM Basic concepts Semiconductor RAMs ROMs Speed Size and cost Cache memories Performance consideration Virtual memory Memory management Secondary storage devices 28 Semiconductor RAMs 29 ROMs 30 MEMORY SYSTEM - Speed 31 MEMORY SYSTEM - Size and cost 32 Cache memories 33 Performance consideration 50 1,2 BB 34 Virtual memory 50 1,2 BB, Assignment 35 Memory management 50 1,2 BB 36 Secondary storage devices 50 1,2 BB UNIT V I/O ORGANISATION Accessing I/O devices Interrupts Direct Memory Access Buses Interface Circuits standard I/O Interfaces (PCI, SCSI, USB) 37 Accessing I/O devices 50 2 BB 38 Interrupts 50 2 BB 39 Direct Memory Access 50 2 BB 40 Buses 50 2 BB 41 Interface Circuits 50 2 BB 42 standard I/O Interfaces 50 2 BB 43 standard I/O Interfaces - PCI 50 2 BB, Assignment 44 standard I/O Interfaces - SCSI 50 2 BB

5 45 standard I/O Interfaces - USB 50 2 BB Prepared by : P. Deivanai Signature : Date : Signature of the HOD