Zynq-7000 All Programmable SoC Product Overview
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1 Zynq-7000 All Programmable SoC Product Overview The SW, HW and IO Programmable Platform August 2012 Copyright Xilinx
2 Introducing the Zynq All Programmable SoC Breakthrough Processing Platform Higher system performance, lower total power Flexible and scalable solution Industry Standard Design Environments Well defined SW programming model Familiar SW & HW design flows Flexible Accelerators and IP World class 28nm unified Programmable Logic Standard AMBA 4 AXI interfaces Broad Ecosystem Support Tools, OS s & IPs Middleware, codecs System integrators and training partners. Familiar Processing System + Scalable Programmable Logic Page 2
3 Value of the Zynq-7000 All Programmable SoC Next level of Programmable System Integration All programmable (Hardware and Software) processing platform ARM Cortex -A9 MPCore Processing System with hardened peripherals, ADC and 28nm scalable optimized programmable logic Increased System Performance 1 GHz, dual core processors with NEON and vector floating point units 7 series programmable logic (PL) with built-in DSP High bandwidth, low latency connects enable acceleration of key functions BOM Cost Advantage in an cost optimized 28nm platform Integration for component reduction, PCB simplification and area reduction Platform approach enables aggregation of volumes over several projects Low Total Power solution Industry-leading ARM processors maximize MHz/W and low power states 28nm HPL process and Integration provides ultra-lower power data transfers Software and Hardware programmable power control and operating modes Accelerated Design Productivity for TTM and TIM advantage Industry standard HW and SW development tools for fast Time-To-Market Flexible and scalable platform enables extended Time-In-Market Extensive ecosystem of tools and solutions partners Page 3
4 Zynq-7000 Family Highlights Complete ARM -based Processing System Dual ARM Cortex -A9 MPCore, processor centric Integrated memory controllers & peripherals Fully autonomous to the Programmable Logic Processing System Memory Interfaces 7 Series Programmable Logic Tightly Integrated Programmable Logic Used to extend Processing System Common Peripherals ARM Dual Cortex-A9 MPCore System Common Peripherals Custom Peripherals High performance ARM AXI interfaces Scalable density and performance Common Accelerators Custom Accelerators Flexible Array of I/O Wide range of external multi-standard I/O High performance integrated serial transceivers Analog-to-Digital Converter inputs Software & Hardware & IO Programmable Page 4
5 Complete ARM-based Processing System Processor Core Complex Dual ARM Cortex-A9 MPCore with NEON extensions Single / Double Precision Floating Point support Up to 1 GHz operation High BW Memory Internal L1 Cache 32KB/32KB (per Core) L2 Cache 512KB Unified On-Chip Memory of 256KB Integrated Memory Controllers (DDR3, DDR2, LPDDR2, 2xQSPI, NOR, NAND Flash) Integrated Memory Mapped Peripherals 2x USB 2.0 (OTG) w/dma 2x Tri-mode Gigabit Ethernet w/dma 2x SD/SDIO w/dma 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 32b GPIO AMBA Open Standard Interconnect High bandwidth interconnect between Processing System and Programmable Logic ACP port for enhanced hardware acceleration and cache coherency for additional soft processors Processing System Ready to Program Page 5
6 Powerful Application Processor at Heart The Application Processor Unit (APU) Dual ARM Cortex-A9 MPCore with NEON extensions Up to 1 GHz operation (7030 & 7045) 2.5 DMIPS/MHz per core Multi-issue (up to 4), Out-of-order, Speculative Separate 32KB Instruction and Data Caches with Parity Snoop Control Unit L1 Cache Snoop Control Snoop filtering monitors cache traffic Accelerator Coherency Port Level 2 Cache and Controller Shared 512 KB Cache with parity Lockable NEON / FPU Engine MI Cortex -A9 MPCore O 32/32 KB I/D Caches 512KB L2 Cache Snoop Control Unit On-Chip Memory (OCM) Dual-ported 256KB Low-latency CPU access NEON / FPU Engine Cortex -A9 MPCore 32/32 KB I/D Caches 256 KB OCM Interrupt Controller, Timers, DMA, Debug, etc. Accessible by DMAs, Programmable Logic, etc. Page 6
7 Processing System External Memories Built-in Controllers and dedicated DDR Pins DDR controller DDR3, DDR2, and LPDDR2 16 bit or 32 bit wide; ECC on 16 bit up to DDR1333 up to DDR800 up to DDR dedicated DDR pins NAND Controller ECC 8 bit or 16 bit data widths NOR/SRAM Controller 8 bit data width Quad SPI (QSPI) Controller To MIO Up to 2 QSPI parallel memories for highspeed boot and configuration NAND CTRL From Central Interconnect 2 Chip Selects NOR /SRAM CTRL APU QSPI CTRL DDR Controller From L2 Cache Controller 32 bit 16 bit 4 x 8 bit 2 x 8 bit 2 x 16 bit 1 x 16 bit 1x 32bit NA 2 Dedicated to Programmable Logic Legend Arrow direction shows control, Data flows both directions AXI3 64 bit / APB 32 bit Page 7
8 Comprehensive set of Built-in Peripherals Enabling a wide set of IO functions Two USB 2.0 OTG/Device/Host Two Tri- Mode GigE (10/100/1000) Two SD/SDIO interfaces Two CAN 2.0B, SPI, I2C, UART Four GPIO 32bit Blocks Multiplexed Input/Output (MIO) Multiplexed output of peripheral and static memories Two I/O Banks: each selectable - 1.8V, 2.5V or 3.3V Configured using new feature in XPS Extended MIO Enables use of Select IO with PS peripherals 54 I/O MUX 2x SPI 2x I2C 2x CAN 2x UART GPIO 2x SD/SDIO with DMA 2x USB with DMA 2x GigE with DMA Static Memory Controllers Extended MIO Page 8
9 Peripherals Programmable Logic to Memory Primary System Interconnects Maximizing Data Transfers Programmable Logic to Memory 2 Ports to DDR Controller 1 Port to OCM SRAM Central Interconnect Crossbar switches for high bandwidth communications Processing System Master Ports 2x 32b AXI Ports from Processing System to Programmable Logic Connects CPU Block to Common Peripherals, through the Central Interconnect Processing System Slave Ports 2x 32b AXI Ports from Programmable Logic to Processing System ACP (Accelerator Coherence Port) Low-latency cache-coherent port for programmable logic Enables application-specific customizations with a standard programming model Page 9 NAND, NOR/SRAM, QSPI Controllers... Legend Configurable AXI3 32 bit/64 bit AXI3 64 bit / AXI3 32 bit / AHB 32 bit / APB 32 bit DMA L2 Cache APU OCM Central Interconnect DDR Controller OCM Master/Slave AXI Interfaces to Programmable Logic ACP Arrow direction shows control, Data flows both directions
10 Tightly Integrated Programmable Logic Built with State-of-the-art 7 Series Programmable Logic Artix-7 & Kintex-7 FPGA Fabric 28K-350K logic cells 430K-5.2M equivalent ASIC gates Over 3000 Internal Interconnects Up to ~100Gb of BW Memory-mapped interfaces Note: ASIC equivalent gates based on analysis over broad range of designs Integrated Analog Capability Dual multi channel 12-bit A/D converter Up to 1Msps Enables Massive Parallel Processing Up to 900 DSP blocks delivering over 1334 GMACs Scalable Density and Performance Page 10
11 Flexible External I/O 54 Dedicated Peripheral I/Os Supports integrated peripherals Static memory (NAND, NOR, QSPI) More I/Os available though the Programmable Logic 73 Dedicated Memory I/Os DDR3 / DDR2 / LPDDR2 Memory Interfaces Configurable as 16bit or 32bit Over 350 Multi-Standard and High Performance I/O Up to V capable multi-standard I/O Up to 150 high performance I/O Up to differential 17 ADC inputs High Performance Integrated Serial Tranceivers (Two largest devices only) Up to 16 transceivers Operates up to 12.5Gbs Supports popular protocols Integrated PCIe Gen2 block Flexibility Beyond Any Standard Processing Offering Page 11
12 I/O Programmable Logic Processing System Zynq-7000 Device Portfolio Summary Scalable platform offers easy migration between devices Zynq-7000 AP SoC Devices Z-7010 Z-7020 Z-7030 Z-7045 Processor Core Dual ARM Cortex -A9 MPCore Processor Extensions NEON & Single / Double Precision Floating Point Max Frequency 800 MHz 1 GHz Memory External Memory Support Peripherals L1 Cache 32KB I / D, L2 Cache 512KB, on-chip Memory 256KB DDR3, DDR2, LPDDR2, 2x QSPI, NAND, NOR 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO Approximate ASIC Gates ~430K (30k LC) ~1.3M (85k LC) ~1.9M (125k LC) ~5.2M (350k LC) Block RAM 240KB 560KB 1,060KB 2,180KB Peak DSP Performance (Symmetric FIR) 100 GMACS 276 GMACS 593 GMACS 1334 GMACS PCI Express (Root Complex or Endpoint) - Gen2 x4 Gen2 x8 Agile Mixed Signal (XADC) 2x 12bit 1Msps A/D Converter Processor System IO 130 Multi Standards 3.3V IO Multi Standards High Performance 1.8V IO Multi Gigabit Transceivers Page 12
13 BOM Cost BOM Cost Reduction Reduced Devices per Board Processors, PLDs, DSPs A/D converters Power supplies, fans, etc Reduced PCB Complexity Fewer traces/interconnect/layers Fewer power supplies Smaller overall PCB In-System Reconfiguration Combines Multiple Device Functions Reconfigureable programmable logic to provide specific functionality at a given time PS Aggregates Numerous IP Royalties for Net Cost Benefit FPGA PCB / Other Components ASIC or full FPGA solutions would require purchase of these IPs from 3 rd parties. DSP Processor Multi-chip Up to 40% BOM Cost Reduction vs. Multi- Chip Solutions AP SoC Zynq-7000 Platform approach enables higher volumes and lower prices
14 Total Power Reduction Flexible/Tunable Power Envelope Adjustable processor speed Adjustable ARM AMBA - AXI & memory speeds ARM low power states Programmable logic can be turned off Programmable logic clock gating Partial reconfiguration to reduce Programmable logic requirement Integration Power Reduction Reduced interconnections between devices Fewer system devices Lower programmable logic power (28nm HPL process) FPGA DSP Processor Multi-chip Up to 50% Lower Power Vs. Multi-Chip Solutions AP SoC Zynq-7000 Significant Power Reduction at the System Level
15 Accelerated Design Productivity Reduced Time To Market Fixed processor system with large set of built in peripherals Xilinx standardizing on AMBA-4 AXI enhances portability of IPs Scalable optimized architecture for IP re-use; AXI interfaces for plug & play IP Accelerate development with targeted design platforms Increased Time In Market ASIC / ASSP / 2 Chip Dev. Design #1 Dev. Design #2 Software and hardware re-programmability Dev. Design #3 Field upgradable Address Processor/ASSPs short shelf life AP SoC Dev. Platform #1 Dev. Dev. Extended Product life Platform Approach Enables Horizontal and Vertical Scalability
16 Zynq-7000 AP SoC Applications Mapping Page 16
17 Device Table Copyright Xilinx
18 Zynq-7000 Device Table Processing System Processing System Part Number Processor Core Processor Extensions Maximum Frequency L1 Cache L2 Cache On-Chip Memory External Memory Support (5) External Static Memory Support (5) DMA Channels Peripherals Peripherals w / built-in DMA (5) Security (1) Processing System to Programmable Logic Interface Ports (Primary Interfaces & Interrupts Only) Zynq All Programmable SoC Device Name Z-7010 Z-7020 Z-7030 Z-7045 XC7Z010 XC7Z020 XC7Z030 XC7Z045 Dual ARM Cortex -A9 MPCore w ith CoreSight NEON & Single / Double Precision Floating Point for each processor 800 MHz 1 GHz 32 KB Instruction, 32 KB Data per processor 512 KB 256 KB DDR3, DDR2, LPDDR2 2x Quad-SPI, NAND, NOR 8 (4 dedicated to Programmable Logic) 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO AES and SHA 256b Decryption and Authentication for Secure Boot 2x AXI 32b Master, 2x AXI 32b Slave, 4x AXI 64b/32b Memory See next slide for Programmable Logic and package details Page 18
19 Zynq-7000 Device Table Programmable Logic and Packages Programmable Logic Speed Grades Device Name Part Number Xilinx 7 Series Programmable Logic Equivalent Programmable Logic Cells (Approximate ASIC Gates (3) ) Look-Up Tables (LUTs) Flip-Flops Extensible Block RAM (# 36 Kb Blocks) Programmable DSP Slices (18x25 MACCs) Peak DSP Performance (Symmetric FIR) PCI Express (Root Complex or Endpoint) Agile Mixed Signal (AMS) / XADC (5) Security (1) Commercial (0C to 85C) Extended (0C to 100C) Industrial (-40C to 100C) Zynq All Programmable SoC Z-7010 Z-7020 Z-7030 Z-7045 XC7Z010 XC7Z020 XC7Z030 XC7Z045 Artix -7 FPGA Artix -7 FPGA Kintex -7 FPGA Kintex -7 FPGA 28K Logic Cells (~430K) 85K Logic Cells (~1.3M) 125K Logic Cells (~1.9M) 350K Logic Cells (~5.2M) 17,600 53,200 78, GMACS 276 GMACS 593 GMACS 1334 GMACS Gen2 x4 Gen2 x8 2x 12 bit, MSPS ADCs w ith up to 17 Differential Inputs AES and SHA 256b Decryption and Authentication for Secure Programmable Logic Configuration Package Type (4) CLG225 (5) CLG400 CLG400 CLG484 FBG484 FBG676 FFG676 FBG676 FFG676 FFG900 Size (mm) 13x13 17x17 17x17 19x19 23x23 27x27 27x27 27x27 27x27 31x31 Pitch (mm) Processing System User I/Os (Excludes DDR dedicated I/Os) (2) Packages Multi-Standards and Multi-Voltage SelectIO TM Interfaces (1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V) Multi-Standards and Multi-Voltage High Performance SelectIO Interfaces (1.2V, 1.35V, 1.5V, 1.8V) Serial Transceivers Maximum Transceiver Speed (Speedgrade Dependant) N/A N/A N/A N/A 6.6 Gb/s 6.6 Gb/s 12.5 Gb/s 6.6 Gb/s 12.5 Gb/s 12.5 Gb/s -1-2, -3-1, ,600 35, , , , KB (60) 560 KB (140) 1,060 KB (265) 2,180 KB (545) Notes: 1. Security block is shared by the Processing System and the Programmable Logic. 2. Static memory interface combined w ith the usage of many peripherals could require more than 54 I/Os. In that case the designer can use the Programmable Logic SelectIO interface. 3. Eqivalent ASIC gate count is dependent of the function implemented. The assumption is 1 Logic Cell = ~15 ASIC Gates. 4. Devices in the same package are pin to pin compatible, FBG676 and FFG676 are also pin to pin compatible 5. Z-7010 in CLG225 has restrictions on PS peripherals, Memory interfaces and I/Os. Please refer to the datasheet for more details 6. Preliminary product information. Subject to change. Please contact your Xilinx representative for the latest information Page 19
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