Optimizing RX Performance

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1 Optimizing RX Performance Renesas Electronics America Inc.

2 Renesas Technology & Solution Portfolio 2

3 Microcontroller and Microprocessor Line-up bit 1200 DMIPS, Superscalar Automotive & Industrial, 65nm 600µA/MHz, 1.5µA standby 500 DMIPS, Low Power Automotive & Industrial, 90nm 600µA/MHz, 1.5µA standby 32-Bit High Performance DSP, FPU with High Integration 1200 DMIPS, Performance Automotive, 40nm 500µA/MHz, 35µA deep standby 165 DMIPS, FPU, DSC Industrial, 90nm 500µA/MHz, 1.6µA deep standby 165 DMIPS, FPU, DSC Industrial, 40nm 200µA/MHz, 0.3µA deep standby 8/16-bit 25 DMIPS, Low Power Industrial & Automotive, 150nm 190µA/MHz, 0.3µA standby 10 DMIPS, Capacitive Touch Wide Industrial Format & Automotive, LCDs 130nm 350µA/MHz, 1µA standby 44 DMIPS, True Low Power Industrial & Automotive, 130nm 144µA/MHz, 0.2µA standby 3

4 Enabling The Smart Society Solution: This lab will help you understand ways to squeeze more performance out of the RX microcontroller. 4

5 Agenda Presentation: RX High-Performance Architecture Core Instruction set Peripherals Lab: Measure & Maximize RX Performance Basic benchmarking Improve a real application Q & A 5

6 RX Architecture: Enabling High-Performance 6

7 RX Architecture CPU Core and Pipeline RX600 CISC CPU 100MHz CPU Core 9 x 32 bit Control Registers 16 x 32 bit General Purpose Registers 32 bit Floating Point Unit 32 x 32 MAC to 48 bit or 80 bit Result 32 x 32 DIV or MULT 32 bit or 64 bit Result Interrupt Control Memory Protection Unit On-Chip Debug 64bit Instructions 32bit Operands (Data) TICK 5-STAGE PIPELINE TICK F D E M W F TICK E D F TICK E ENHANCED HARVARD ARCHITECTURE D F TICK M E D F TICK F W M E D TICK D F W M E TICK E D F W M TICK M E D F W Achieves One Clock-Per-Instruction (CPI) PRE-FETCH QUEUE (PFQ) 64bits 64bits 64bits 64bits Holds 4 to 32 Instructions for Slower Memory WRITE BUFFER Buffer Only for Writes For Slower Memory Inst Data Typically Flash Memory 64 Memory Interface 32 Typically SRAM 5 STAGES OF PIPELINE F = FETCH INSTRUCTION D = DECODE INSTRUCTION E = EXECUTE INSTRUCTION M = READ OR WRITE MEMORY W = WRITE BACK TO REGISTER 7

8 RX Architecture Memory Interface External Bus Pins for CPU RX600 CPU 100MHz 32 bits PIPELINE External Bus Controller (BSC) PFQ BUFFER Bus Master of Internal Main Bus 1 32 bits 64b INST 32b DATA BUS MATRIX Allows CPU to concurrently fetch Instructions or access Data from any of 3 sources: Flash Memory SRAM Internal Main Bus 1 64 bits 64 bits 32 bits Internal Main Bus 1 SRAM, 100MHz Access RX600 MCU Flash Memory, 100MHz Access Bus Bridge Peripherals 100 MHz Flash and SRAM means zero wait-state code and data access PFQ minimizes stalls from slower memory, such as external memory CPU is bus master of Internal Bus 1 Internal Bus 2 connects to peripherals 8

9 RX Architecture System Interface One External Device Another External Device External Bus Pins for CPU RX600 CPU 100MHz PIPELINE Communication (USB, CAN, SCI, SPI, I2C) PFQ BUFFER Bus Master of Internal Main Bus 1 32 bits External Bus Controller (BSC) EXDMA (external bus master) 32 bits 32 bits 64b INST 32b DATA Bus Bridge Bus Bridge Multiple Peripheral Busses to Spread Bandwidth Loading Timers (MTU, TPU, TMR, CMT) BUS MATRIX Allows CPU to concurrently fetch Instructions or access Data from any of 3 sources: Flash Memory SRAM Internal Main Bus 1 Internal Main Bus 2 DTC (bus master) CNTL Analog (DAC, ADC, PGA) 64 bits 64 bits 32 bits Internal Main Bus 1 GPIO SRAM, 100MHz Access DMAC (bus master) CNTL System Control (DMA, E2P, ICU, LVD, RTC, WDG, CLKS) Ethernet DMAC (bus master) CNTL RX600 MCU Flash Memory, 100MHz Access Ethernet MAC 9

10 RX Floating Point Unit 10

11 Question: Who Said It? Microprocessor manufacturers unfortunately seem to feel that floating-point math is not very important in embedded systems. This has not been my experience. Jean Labrosse, President Micrium Author, μc/os operating system 11

12 RX Floating Point Unit IEEE 754 single precision 32 bits data format Subtract, Multiply, Divide and Integer Conversion directly from CPU registers Example: FMUL # H,R4 IEEE 754 Exceptions Floating Point Instructions: FADD - Floating-point ADD FCMP - Floating-point COMPare FDIV - Floating-point DIVide FMUL - Floating-point MULtiply FSUB - Floating-point SUBtract FTOI - Float TO Integer ITOF - Integer TO Floating-point ROUND - ROUND floating-point to integer R0 (SP ) R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Memory map tap FIR: us Floating Point Unit 12

13 Under the Hood: FPU Code Generation Sample floating point operation: temperature conversion Variables: single precision floats float Degrees_C, Degrees_F ; Degrees_C = 22.1 ; Degrees_F = (Degrees_C * 9.0/5.0) ; Floating point constants Floating point operations 13

14 Under the Hood: FPU Code Generation Code emitted by compiler float Degrees_C, Degrees_F ; Degrees_C = 22.1 ; Degrees_F = (Degrees_C * 9.0/5.0) ; Degrees_C = 22.1 ; MOV.L #41B0CCCDH,R3 Degrees_F = (Degrees_C * 9.0/5.0) ; MOV.L R3,R4 FMUL # H,R4 FDIV #40A00000H,R4 FADD # H,R4 Constants stored in IEEE 754 format RX floating point instructions operate directly on registers & memory 14

15 Under the Hood: FPU Code Generation Comparison: 1 FPU instruction = 100+ SW instructions SHLR _COM_DIVf BEQ.S #1,R1 MOV.L make_result denormalize_loop SHLR MOV.L R1,R15 ADD #1,R2 #0H,R5 XOR R2,R1 R2,R15 make_result BNC.B MOV.L MOV.L next_loop #0H,R4 SHLL R5,R2 BSET MOV.L #1,R1 SHLL #0,R2 #1AH,R14 MOV.L #1,R2 Degrees_C = 22.1 ; next_loop CMP BRA.S R1,R3 XOR #0H,R3 SHLR #01H,R4 MOV.L #41B0CCCDH,R3 div_loop_entry BGE.B #24,R3 OR round_denormal SHLL R4,R2 div_loop ADD SHLL #8,R1 SHLL #1H,R3 #1,R5 Degrees_F = (Degrees_C * 9.0/5.0) ; SHLL #6,R2 BRA.B BTST #1,R2 CMP #0,R4 MOV.L R3,R4 MOV.L #0H,R1 denormalize_loop BNE.S R2,R4 BEQ.S FMUL # H,R4 round_denormal div_loop_entry SHLR #24,R4 end_calc_sticky BTST #7,R2 FDIV #40A00000H,R4 BEQ.B BSET SHLL #0,R5 #8,R2 OR end_round_d FADD # H,R4 div_loop_entry SHLL CMP #20H,R2 #1,R1 #0FFH,R3 end_calc_sticky MOV.L MOV.L R2,R4 ROLC BEQ.W R2,R4 AND exception1 BTST #017FH,R4 BTST CMP #31,R4 round_carry BEQ.S RORC #1,R4 #0FFH,R4 BNE.S end_round_d R2 BNE.S BEQ.W div_1 exception2 end_normalize ADD ADD #0100H,R2,R2 #1H,R3 end_round BPZ.B SUB SHLL CMP R2,R1 #0H,R3 SHLL end_round_d #1,R2 BC.B BEQ.W #1,R2 ADD SHLR div_2 exception3 exception_return3 SUB #1H,R3 #8,R2 XOR CMP #1H,R3 end_round_d #01H,R4 #0H,R4 end_normalize BRA.B SHLL CMP end_round #24,R3 BRA.S BEQ.B #0FFH,R3 end_denormal BTST OR div_2 exception4 div_1 exception_return4 BLT.B #7,R2 R2,R3 ADD SUB 0FFFF885EH BEQ.B MOV.L R2,R1 R4,R3 BRA.W end_round R3,R1 BNC.B ADD return_inf MOV.L SHLL div_2 #7FH,R3,R3 CMP R2,R4 #1,R15 XOR OR #-17H,R3 AND RORC #01H,R4 #1H,R1 BGE.B #017FH,R4R1 div_2 SUB ROTR 0FFFF8866H BEQ.B RTS #1H,R14 #1,R1 BRA.W end_round BNE.B RORC return_zero ADD div_loop R2 CMP #0100H,R2,R2 #0H,R3 div_loop_exit BNC.B AND #1H,R4 BGT.B end_round end_denormal 15

16 RX Instruction Set 16

17 Question: What programming language do you use? If it doesn t run Python, I won t use it C/C++ Real men program in assembler No, real men use a hex editor & opcodes I once programmed a database using only 1 s & 0 s You had 0 s!?!? 17

18 Another Question How big is your code? <10K 10K - 64K 64K 128K Under one megabyte Under 4 Megabytes I write code for Microsoft and own stock in Seagate! 18

19 Instruction Set Target: Improve code density, support for High Level Langs Analyze code from real-world customer applications Adopt variable byte-length instruction Assign most used instructions to short instruction codes Add addressing modes Benchmark, refine, benchmark, refine Result: 30% Code Size Reduction Code size (relative) Motor control 28% less Data communication 19% less Data conversion 17% less Real-time control 25% less System control 25% less 1.0 = RX600 = Cortex-M3 based MCU Note: Internal benchmark test, your results may vary 19

20 RX Smart Peripherals 20

21 Why Smart Peripherals? I don t care what it is, when it has an LCD screen, it makes it better. Kevin Rose, Diggnation 21

22 Peripherals Targets: Offload the CPU, ease migration, reduce power Cherry pick from extensive portfolio Add intelligent DMAC, Data Transfer Controller, new Timers, Ethernet, USB, CAN Result: Only 5% CPU loading for 60 Hz refresh of static image 22

23 DMAC vs Data Transfer Control (DTC) Similarities Registers (SAR, DAR, Xfer & Block Count) Byte, words, long words Auto Increment/Decrement SAR/DAR Normal/Repeat/Block modes Interrupt generation Differences DMA faster, 1 transfer/cycle DMA dedicated registers for each channel DMA channels limited DTC many virtual channels DTC channels can be chained DTC much more flexible 23

24 Lab Technique: Measuring Performance 24

25 Measuring System Performance Performance Counters Hardware supported high-resolution timer Counts execution cycles & number of passes for two sections of user code No affect on your code Two 32-bit timers or one 64-bit timer Triggered by complex events Selectively record all executions cycles, interrupts, exceptions 25

26 Performance Analysis Setup 26

27 RX Performance Labs: Goals RX Core Benchmarking Dhrystone Optimize a real application Benchmark application polled mode Use timers & interrupts Use DMAC to read & buffer ADC readings 90% CPU loading doubles the schedule, 95% triples it. Alan M. Davis 201 Principles of Software Development 27

28 Start your lab! 28

29 Start the Lab Please refer to the Lab Handout and let s get started! 29

30 RX Performance Labs: Review RX Core Benchmarking Dhrystone: 1.65 DMIPS/MHz Performance scales linearly to 100 MHz 30

31 Start the Lab Please refer to the Lab Handout and let s get started! 31

32 RX Performance Labs: Sample Application Collect samples from ADC Scale reading to J thermocouple range, convert C Version 1: Polled No optimization, do everything as fast as possible Version 2: Interrupts Post-process while ADC is sampling One interrupt/sample Version 3: DMAC DMAC buffers 5,000 readings One interrupt/buffer 32

33 RX Performance Labs: Review Reduce CPU overhead w/ smart peripherals Benchmark: 100% of 330 khz Timer & interrupts: 90% of 500 khz Plus DMAC: 69% of 500 khz Take advantage of smart peripherals! 33

34 Questions? 34

35 Enabling The Smart Society Solution: This lab will help you understand ways to squeeze more performance out of the RX microcontroller. 35

36 Renesas Electronics America Inc.

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