Real-Time Embedded Systems. CpE-450 Spring 06

Transcription

1 Real-Time Embedded Systems CpE-450 Spring 06 Class 5 Bruce McNair bmcnair@stevens.edu 5-1/42

2 Interfacing to Embedded Systems Distance 100 m 10 m 1 m 100 cm 10 cm "Transmission line" capacitance ( C) Distance ( D) dv dt Power Data Rate ( R) dv C DiR dt constant power Speed 1 kb/s 10 kb/s 100 kb/s 1 Mb/s 10 Mb/s 5-2/42

3 Interfacing to Embedded Systems Distance 100 m 10 m 1 m 100 cm RS232 I 2 C SPI 10 cm Speed 1 kb/s 10 kb/s 100 kb/s 1 Mb/s 10 Mb/s 5-3/42

4 Embedded System Interfacing RS-232 Serial Communications μc Data TX status RX Status UART TxD TX status/control/clock RxD RX status/control/clock Master Clock Master Clock = ~10 MHz Data rate = 75*2 N 5-4/42

5 Embedded System Interfacing RS-232 Serial Communications μc Data TX status RX Status UART TxD TX status/control/clock RxD RX status/control/clock Master Clock Master Clock = ~10 MHz Data rate = 75*2 N asynchronous communications Start Data Stop 5-5/42

6 Embedded System Interfacing RS-232 Serial Communications μc Data TX status RX Status UART TxD TX status/control/clock RxD RX status/control/clock Master Clock Master Clock = ~10 MHz Data rate = 75*2 N asynchronous communications Start Data Stop 5-6/42

7 Embedded System Interfacing RS-232 Serial Communications μc Data TX status RX Status UART TxD TX status/control/clock RxD RX status/control/clock Master Clock Master Clock = ~10 MHz Data rate = 75*2 N asynchronous communications Start Data Stop Framing 5-7/42

8 Embedded System Interfacing RS-232 Serial Communications μc Data TX status RX Status UART TxD TX status/control/clock RxD RX status/control/clock Master Clock Master Clock = ~10 MHz Data rate = 75*2 N -V +V 5 V 12 Start Data Framing Stop 5-8/42

9 Embedded System Interfacing RS-232 Serial Communications μc Data TX status RX Status UART TxD TX status/control/clock RxD RX status/control/clock Master Clock Master Clock = ~10 MHz Data rate = 75*2 N -V +V 5 V 12 Start Data Framing Stop Asynchronous Start/Stop Protocol efficiency < 80% 5-9/42

10 Embedded System Interfacing RS-232 Serial Communications TxD RxD Sig GND Computer/ Terminal Modem/ Network DTE DCE 5-10/42

11 Embedded System Interfacing RS-232 Serial Communications TxD RxD Sig GND Frame GND Computer/ Terminal RTS CTS Modem/ Network Request To Send Clear To Send DTR Data Terminal Ready DSR Data Set Ready DCD Data Carrier Detect RI Ring Indication DTE DCE 5-11/42

12 Embedded System Interfacing RS-232 Serial Communications TxD Distance < 50 m Data rate < 50 kb/s RxD Sig GND Frame GND Computer/ Terminal RTS CTS Modem/ Network Request To Send Clear To Send DTR Data Terminal Ready DSR Data Set Ready DCD Data Carrier Detect RI Ring Indication DTE DCE 5-12/42

13 Embedded System Interfacing RS-232 Serial Communications - variations TxD TTL levels Minimizing functions RxD Sig GND Frame GND Computer/ Terminal RTS CTS Modem/ Network Request To Send Clear To Send DTR Data Terminal Ready DSR Data Set Ready DCD Data Carrier Detect RI Ring Indication DTE DCE 5-13/42

14 Embedded Systems Interfacing SPI Serial Peripheral Interface MOSI SI MISO SO Processor SCLK CLK Peripheral I/O CS GND GND 5-14/42

15 Embedded Systems Interfacing SPI Serial Peripheral Interface synchronous communications SR SR Processor Master MOSI MISO SCLK I/O SI SO CLK CS SR SR Peripheral Slave GND GND 5-15/42

16 Embedded Systems Interfacing SPI Serial Peripheral Interface SR MOSI SR MISO Processor SCLK Master I/O Master Out Slave In Slave In SI SR SO SR CLK Peripheral CS Slave GND GND 5-16/42

17 Embedded Systems Interfacing SPI Serial Peripheral Interface MOSI SI S SCLK CLK S R R Processor MISO SO Peripheral 5-17/42

18 Embedded Systems Interfacing SPI Serial Peripheral Interface MOSI SI SO SI SO SI SO Processor MISO SCLK CLK Peripheral 1 Peripheral 2 Peripheral 3 I/O CS GND GND GND GND Extension to multiple peripherals: Real Time Clocks (time of day) Sensors (e.g. potentiometers) FLASH memory Interface speed limited by device technology Mb/s, compared to kb/s for RS /42

19 Embedded Systems Interfacing SPI timing (Clock low, Clock phase 0) SPI cycle SCLK MOSI MSB LSB MISO MSB LSB x CS 5-19/42

20 Embedded Systems Interfacing I 2 C Inter Integrated Circuit V CC SCL SDA Serial Clock Serial Data Master Slave Master Slave Slave 5-20/42

21 Embedded Systems Interfacing I 2 C Inter Integrated Circuit V CC SCL SDA Serial Clock Serial Data Master Slave Master Slave Slave SDA SCL Start message 5-21/42

22 Embedded Systems Interfacing I 2 C Inter Integrated Circuit V CC SCL SDA Serial Clock Serial Data Master Slave Master Slave Slave SDA SCL Data sampled Data sampled Data can change 5-22/42

23 Embedded Systems Interfacing I 2 C Inter Integrated Circuit Multi-master bus V CC SCL SDA Serial Clock Serial Data Master Slave Master Slave Slave SDA1 SCL1 SDA2 SCL2 Writing 0 Writing 1 Writing 0 Writing /42

24 Embedded Systems Interfacing I 2 C Inter Integrated Circuit Multi-master bus V CC SCL SDA Serial Clock Serial Data Master Slave Master Slave Slave SDA1 SCL1 SDA2 SCL2 Writing 0 Writing 1 Writing 0 Writing 1 Device writing 1 passively allows pullup resistors to pull bus to 1 Device writing 0 actively sets bus to /42

25 Embedded Systems Interfacing I 2 C Inter Integrated Circuit Multi-master bus V CC SCL SDA Serial Clock Serial Data Master Slave Master Slave Slave SDA1 SCL1 SDA2 SCL2 Writing 0 Writing 1 Writing 0 Writing 1 Device writing 1 passively allows pullup resistors to pull bus to 1 Device writing 0 actively sets bus to 0 Device that writes 1 but hears 0 aborts transmission and tries later 5-25/42

26 Inter-process Communications Processor 1 Peripheral 1 Peripheral M 5-26/42

27 Inter-process Communications Processor 1 Peripheral 1 RS-232 SPI I 2 C Peripheral M 5-27/42

28 Inter-process Communications Processor 1 Peripheral 1 RS-232 SPI I 2 C Processor N Peripheral M 5-28/42

29 Inter-process Communications Processor 1 Peripheral 1 I 2 C Processor N Peripheral M 5-29/42

30 Higher Speed Inter-process Communications Processor 1 Parallel Registers FIFO Shared RAM Interconnect busses Processor N 5-30/42

31 Parallel Register for IPC Processor 1 Processor 2 Parallel Latch 5-31/42

32 Parallel Register for IPC Processor 1 Processor 2 Parallel Latch at t 0, write data, ready flag at t 1 > t 0, find ready flag, read data 5-32/42

33 Parallel Register for IPC Parallel Processor 1 Processor 2 Latch at t 0, write data, ready flag at t 1 > t 0, find ready flag, read data Issues: One word per transfer One latch per processor pair/direction 5-33/42

34 Parallel Register for IPC Parallel Processor 1 Processor 2 Latch at t 0, write data, ready flag at t 1 > t 0, find ready flag, read data Issues: One word per transfer No potential for batch transfers One latch per processor pair/direction N 2 latches are required 5-34/42

35 Parallel Registers for IPC Parallel Processor 1 Processor 2 Latches at t 0, write K words of data, ready flag at t 1 > t 0, find ready flag, read K words of data Issues: One word per transfer No potential for batch transfers Restrictive interface (always K words to transfer) One latch per processor pair/direction N 2 latches are required 5-35/42

36 FIFOs for IPC Full Not empty First-In, First-Out Processor 1 Processor 2 Registers at t 0, write K words of data at t 1 > t 0, find not-empty flag, read J<K words of data Issues: One FIFO per processor pair/direction N 2 FIFOs are required 5-36/42

37 FIFOs as Elastic Storage Buffer Full Not empty Processor 1 FIFO Processor 2 activity activity t t Batch processing can proceed without tight synchronization 5-37/42

38 Dual-Port RAM for IPC Address Address Dual-port Processor 1 Processor 2 RAM Data Data 5-38/42

39 Dual-Port RAM for IPC Address Address Dual-port Processor 1 Processor 2 RAM Data Data RAM appears normally in the address space of P1 and P2 Data and semaphores can be shared 5-39/42

40 Dual-Port RAM for IPC Address Address Dual-port Processor 1 Processor 2 RAM Data Data RAM appears normally in the address space of P1 and P2 Data and semaphores can be shared but, N 2 /2 dual-port RAMs are needed for N processors. 5-40/42

41 Configurations of Multiprocessing in Embedded Systems Tree Structure O(N) connections Fully interconnected, O(N 2 ) connections 5-41/42

42 Configurations of Multiprocessing in Embedded Systems Tree Structure O(N) connections Fully interconnected, O(N 2 ) connections More likely configuration (by careful design?!) 5-42/42