Reader's Guide Outline of the Book A Roadmap For Readers and Instructors Why Study Computer Organization and Architecture Internet and Web Resources

Transcription

1 Reader's Guide Outline of the Book A Roadmap For Readers and Instructors Why Study Computer Organization and Architecture Internet and Web Resources Overview Introduction Organization and Architecture Structure and Function Key Terms and Review Questions Computer Evolution and Performance A Brief History of Computers Designing for Performance The Evolution of the Intel x86 Architecture Embedded Systems and the ARM Performance Assessment The Computer System A Top-Level View of Computer Function and Interconnection Computer Components Computer Function Interconnection Structures Bus Interconnection PCI A Timing Diagrams Cache Memory Computer Memory System Overview Cache Memory Principles Elements of Cache Design Pentium 4 Cache Organization ARM Cache Organization A Performance Characteristics of Two-Level Memorie Internal Memory Technology Semiconductor Main Memory Error Correction Advanced DRAM Organization

2 External Memory Magnetic Disk RAID Optical Memory Magnetic Tape Input/Output External Devices I/O Modules Programmed I/O Interrupt-Driven I/O Direct Memory Access I/O Channels and Processors The External Interface: FireWire and Infiniband Operating System Support Operating System Overview Scheduling Memory Management Pentium Memory Management ARM Memory Management Computer Arithmetic The Arithmetic and Logic Unit (ALU) Integer Representation Integer Arithmetic Floating-Point Representation Floating-Point Arithmetic Instruction Sets: Characteristics and Functions Machine Instruction Characteristics Types of Operands Intel x86 and ARM Data Types Types of Operations Intel x86 and ARM Operation Types

3 Instruction Sets: Addressing Modes and Formats Addressing x86 and ARM Addressing Modes Instruction Formats x86 and ARM Instruction Formats Assembly Language Processor Structure and Function Processor Organization Register Organization The Instruction Cycle Instruction Pipelining The x86 Processor Family The ARM Processor Reduced Instruction Set Computers (RISCs) Instruction Execution Characteristics The Use of a Large Register File Compiler-Based Register Optimization Reduced Instruction Set Architecture RISC Pipelining MIPS R4000 SPARC The RISC versus CISC Controversy Instruction-Level Parallelism and Superscalar Processors Overview Design Issues Pentium 4 ARM Cortex-A8 The Control Unit Control Unit Operation Micro-operations Control of the Processor

4 Hardwired Implementation Microprogrammed Control Basic Concepts Microinstruction Sequencing Microinstruction Execution TI 8800 Parallel Organization Parallel Processing1 The Use of Multiple Processors Symmetric Multiprocessors Cache Coherence and the MESI Protocol Multithreading and Chip Multiprocessors Clusters Nonuniform Memory Access Computers Vector Computation Multicore Computers HardwarePerformance Issues Software Performance Issues Multicore Organization Intel x86 Multicore Organization ARM11 MPCore Projects for Teaching Computer Organization and Architecture Interactive Simulations Research Projects Simulation Projects Reading/Report Assignments Writing Assignments Test BankAppendix Assembly Language, Assemblers, and Compilers Assembly Language Assemblers Loading and Linking and Web Site

5 Online Chapters WilliamStallings.com/COA/COA8e.htm Number Systems The Decimal System The Binary System Converting between Binary and Decimal Hexadecimal Notation Digital Logic Boolean Algebra Gates Combinational Circuits Sequential Circuits Programmable Logic Devices and Web Site Key Terms and Problems The IA-64 Architecture Motivation General Organization Predication and Speculation IA-64 Instruction Set Architecture Itanium Organization Online Appendices WilliamStallings.com/COA/COA8e.html Hash Tables Victim Cache Interleaved Memory International Reference Alphabet Virtual Memory Page Replacement Algorithms Recursive Procedures Additional Instruction Pipeline TopicsH.1 Pipeline Reservation Tables Reorder Buffers Scoreboarding Tomasulo's AlgorithmReferences Glossary Index Acronyms Table of Contents provided by Blackwell's Book Services and R.R. Bowker. Used with permission.