RS232 SERIAL INTERFACE

Transcription

1 High-Tech Made in Switzerland INTERFACE QUAD RS232 SERIAL INTERFACE The is a low cost quad serial interface built around the HD6350 from HITACHI. The board contains four identical serial channels with the possibility of selecting individual baud rates for each channel. All the serial I/O lines are compatible with the RS232-C standard and are available on four identical connectors on the front of the PCB. Because of its on board DC/ DC converter there is no need to provide an external ±12V supply for the serial driver. Normal access to the board is made via the synchronous VPA space. It is fully compatible with the G-64/96 bus. The supports vectored interrupts in synchronous and asynchronous cycles as well as auto vectored interrupts. In the vectored mode there is the possibility to supply one vector which is identical for all channels or four vectors, one for each channel. Through the careful implementation of full CMOS technology the consumes only 40mA at +5V. TECHNICAL FEATURES Full G-64/96 bus interface Four identical serial channels Six standard baud rates from 300 to baud individually selectable for each channel Synchronous or asynchronous vectored interrupt Synchronous access mode in the I/O space Automatic vector generation One vector for each channel or one for all channels DTE or DCE configuration Low power consumption Access LED requires 16 byte of VPA space Temperature range 0 to 70 C ( +32 to 132 F) References : -1: CMOS Quad serial controller 1993 by MPL AG 1 MEH Rev. C

2 TABLE OF CONTENTS 1. GENERAL INFORMATION DESCRIPTION TECHNICAL CHARACTERISTICS PREPARATION FOR USE PARTS LOCATION JUMPER AND CONNECTOR ASSIGNMENT JUMPER CONFIGURATION VPA ADDRESS SETTING (J2) VECTORED INTERRUPT LEVEL (J3) BUS INTERRUPT SELECTOR (J4) INTERRUPT MODE CONFIGURATION (J5) BAUD RATE SELECTOR (J6-J9) OUTPUT CONFIGURATION (J10-J13) IRQ AFTER RESET SUPPRESSION (J14) IACK CYCLE MODE (J15) SINGLE/MULTI LEVEL INTERRUPT (J16) CONNECTOR PIN ASSIGNMENT RS232 CONNECTOR (P1-P4) G-64/96 BUS CONNECTOR (J1) ACCESS INDICATOR LED THEORY OF OPERATION MEMORY MAP IRQ AFTER RESET SUPPRESSION VECTOR REGISTER

3 P1 P2 P3 P4 RS232 converter RS232 converter RS232 converter RS232 converter ACIA 1 ACIA 2 ACIA 3 ACIA 4 Addressbus A0.. A9 Databus D0.. D7 Control logic Baudrate generator Addressbus Buffer Databus Buffer Controlbus Buffer A0.. A9 D0.. D7 G-64 / G-96 Bus Block diagram 3

4 1. GENERAL INFORMATION 1.1. DESCRIPTION The is a four channel serial controller which is fully compatible with the G-64/96 bus built in full CMOS technology for low power consumption. The board contains four ACIA (Asynchronous Communications Interface Adapter) HD6350. The ACIA provides the data formatting and control to interface serial asynchronous data communications information to the G-64/96 bus and its attached CPU. The functional configuration of the ACIA is programmed via the data bus during system initialisation. The HD6350 is fully hard- and software compatible with the MC6850. The ACIA supports 7 or 8 bit transmission with 1 or 2 stop bits as well as even, odd or no parity. All serial ACIA signals except DCD (Data Carrier Detect) which is not available on the connector are converted to RS232 level and available on four identical 10 pin connectors on the front edge of the card. Every channel also has its own baud rate selector field with which six different baud rates can be selected. The output configuration can be changed on a jumper field which is available for each channel separately. In the vectored interrupt mode there is the possibility to supply one vector for all four ACIAs or one vector for every ACIA depending on a jumper setting. In the four vector mode all vectors are built up from one and only one base vector. The vectored interrupt mode can be used in synchronous or asynchronous interrupt acknowledge cycles ( IACK ). All six interrupt levels which are available on the G-64/96 bus are supported on the. The board occupies 16 bytes in the synchronous address space and can be located anywhere within this address space through the setting of a few jumpers. The has an on-board DC/DC converter which avoids the need for an external ±12V supply. Due to the careful implementation of its fully CMOS technology the current consumptioin of the is extremely low. 2. PREPARATION FOR USE 2.1. PARTS LOCATION 1.2. TECHNICAL CHARACTERISTICS Bus Interface: G-64/96 Data access mode: synchronous Interrupt access mode: synchronous/asynchronous vectored/autovectored Interrupts: 6 Baud rates : 6, Baud Connectors: 4 identical 10 pin headers Technology: 100%CMOS Mech. Dimensions: 100x160mm Weight : 140g Temperature range: 0 to 70C (+32 to 132F) Relative humidity: 20 to 90% non condensing Power requirements: +5V only / 40mA Power range: 4.75V to 5.25V Table 1.2: Technical characteristics Fig. 2.1: Parts location 2.2. JUMPER AND CONNECTOR ASSIGNMENT J1 G-64/96 connector J2 VPA address selector J3 Interrupt vector selector J4 Bus interrupt selector J5 Mode configuration J6-J9 Baud rate selector J10-J13 Output configuration jumper J14 IRQ after reset suppressor jumper J15 IACK cycle mode J16 Single/multi level interrupt P1-P4 RS232 connector channel 1-4 Table 2.2: Jumper and connector assignment 4

5 2.3. JUMPER CONFIGURATION VPA ADDRESS SETTING (J2) The occupies 16 bytes in the VPA range. The base address of the card can be set with J2. The device offset related to the base address can be found in paragraph 3.1. MEMORY MAP. The address at which the card operates is defined by two factors: The predecoded base address defined by the CPUcard (VPA) An offset defined by the setting of J2 Assuming the VPA is true from $EC00-$EFFF and the MPL 4212 should be at $EF80, the following jumpers have to be installed: A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A X X X X X X X X X X VECTORED INTERRUPT LEVEL (J3) If vectored interrupt mode is selected there is the necessity to define a level on which the interrupt logic should act on a interrupt acknowledge cycle. This level can be set by J3. The level set on J3 must be the same as set on J Level 1 Level 2 Level 3 (IRQ 1) (IRQ 2) (IRQ 3) Level 4 Level 5 Level 7 (IRQ 4) (IRQ 5) (IRQ 7) Fig : Vectored interrupt level X X X X VPA X X X X E F 8 0 Offset (J2 A9-A4) Table : J2 VPA select Resulting address The base address of the card ($EF80) is defined by installing the jumpers A9,A8 and A7. A3 to A0 have to remain undefined since these bits define the card-internal offset. The card occupies 16 Bytes, so the next card could be addressed at $EF90! The offset can directly be set in the jumperfield J2. A A4 6 1 J2 Fig : VPA range select Note: Each jumper that is set denotes a logical zero. Address lines A0-A3 are used on the card for internal addressing purpose BUS INTERRUPT SELECTOR (J4) The collected interrupt from the four serial controllers can be assigned to all interrupts available on the G-64/96 bus connector. The level can be selected with J IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ IRQ 7 J4 Fig : Interrupt level select INTERRUPT MODE CONFIGURATION (J5) Jumper J5 is used to select different interrupt modes. The following table shows the configuration for the four different modes. 2 3 auto vectored 1 4 one vector for each channel 2 3 vectored 1 4 one vector for all channels Fig : Interrupt mode configuration 5

6 BAUD RATE SELECTOR (J6-J9) The four jumper fields J6 to J9 are used to select different baud rates. Each channel has its own baud rate selector. The following list shows the four baud rate jumper fields arranged for the four channels. Jumper J6 J7 J8 J9 Channel No. channel1 channel2 channel3 channel4 Table 2.3.5: Baud rate selector jumpers The following figure shows one of the four baud rate selectors baud baud baud baud baud baud Fig : Baudrate selector Note: On jumper field J6 to J9 only one jumper must be inserted at any time, otherwise serious damage to the board can occur OUTPUT CONFIGURATION (J10-J13) The signals from the RS232 converter are connected to P1 - P4 through the interconnections of J10 to J13. The figure below shows how each signal is connected. MAX 238 Channel 1-4 TxD RxD RTS CTS V 1K TxD RxD RTS CTS DCD DSR DTR Fig 2.3.6: Output configuration IRQ AFTER RESET SUPPRESSION (J14) If jumper J14 is inserted no interrupt will be generated until the correct vector is written into the vector register. If it is open there is the possibility for an interrupt after reset. For more information about this MC6850 specific problem see also 3.2 IRQ AFTER RESET SUPPRESSION. IRQ suppression disabled IRQ suppression enabled IACK CYCLE MODE (J15) J15 is used to select synchronous or asynchronous mode in an IACK cycle for the. Synchronous IACK mode Asynchronous IACK mode SINGLE/MULTI LEVEL INTERRUPT (J16) This mode is present for compatibility with older cards only. Normally this jumper will be inserted, and will therefore work in a multilevel interrupt system. Single level interrupt Multi level interrupt 2.4 CONNECTOR PIN ASSIGNMENT RS232 CONNECTOR (P1-P4) Connector P1-P4 are the inputs/outputs to/from the RS232 driver routed through J10-J13. The following table shows the interconnection between the 10pin header and a standard DB25 cable. 1 Gnd 2 TxD 3 RxD 4 RTS CTS 6 DSR DTR 20 7 Gnd 8 DCD 9 10 Fig : RS232 connector Note: Signal GND is directly connected to pin 1 which is normally reserved for chassis. When necessary connect pin 1 from P1-P4 to pin 7 (normally GND) of the RS232 connector. 6

7 2.4.2 G-64/96 BUS CONNECTOR (J1) The following table gives an overview of the bus signals used and their type. PIN ROWB us- T ROWA us- T No. G-64 ed G-64 ed 1 GND GND 2 A8 TS A0 TS 3 A9 TS A1 TS 4 A10 TS A2 TS 5 A11 TS A3 TS 6 A12 TS A4 TS 7 A13 TS A5 TS 8 A14 TS A6 TS 9 A15 TS A7 TS 10 BRQ* OC BGRT TS 11 RRQ* OC RGRT TS 12 BGACK* OC HALT* OC 13 E TS MCLK TS 14 RES* OC VPA* TS 15 NMI* OC RDY OC 16 IRQ* OC VMA* TS 17 FIRQ* OC R/W* TS 18 IACK TS HALT ACK T 19 D12* TS D8* TS 20 D13* TS D9* TS 21 D14* TS D10* TS 22 D15* TS D11* TS 23 D4* TS D0* TS 24 D5* TS D1* TS 25 D6* TS D2* TS 26 D7* TS D3* TS 27 BERR* OC PAGE* TS 28 CHAIN IN T CHAIN OUT T 29 +5V BATT -5V 30-12V +12V 31 +5V +5V 32 GND GND Table 2.4.1: G-64/96 Bus connector Note: The column T designates the type of line. T = TTL OC = Open collector TS = Tristate * = Inverted signal 2.5. ACCESS INDICATOR LED The green LED at the upper card edge will be lit at each access to a valid card address. 3. THEORY OF OPERATION 3.1. MEMORY MAP The following table shows the memory map of the. Address Device VPABase+$0 MC6850 channel 1 VPABase+$2 MC6850 channel 2 VPABase+$4 MC6850 channel 3 VPABase+$6 MC6850 channel 4 VPABase+$8 $F Vector register Table 3.1: Memory map 3.2. IRQ AFTER RESET SUPPRESSION Normally it's not desirable to receive an interrupt from a peripheral card before the software is up and running and allows the hardware to send interrupts. But this situation will occur with the MC6850 or the HD6350 following a reset. This serial controller chip has only an internal power on reset and no reset pin. This means that after a normal bus reset via the CPU board the MC6850 probably has an interrupt pending from the task outstanding before the CPU reset the system. In that case it's not always sure that the CPU can start working again. Because of that reason the has jumper J14 which resolves this situation. If the jumper is inserted all interrupts from the board will be suppressed until a write to the vector register is done. From this point of time the card will work correctly VECTOR REGISTER The vector register holds, as its name says, the vector in vectored mode. Before using the vectored mode this register must be initialised with an appropriate vector. The first two bits cannot be written by the user. They will be changed by the interrupt logic in accordance to the mode selected. The following table shows how each channel corresponds to the vector. The following table shows the vectors when the four vector mode is set. channel 1 channel 2 channel 3 channel 4 VectorBase+1 VectorBase+2 VectorBase+3 This table shows the vectors when one vector mode is enabled. channel 1 channel 2 channel 3 channel 4 7

8 COPYRIGHT AND REVISION HISTORY Copyright 1993 by MPL AG Elektronikunternehmen. All Rights Reserved. Reproduction of this document in part or whole, by any means is prohibited, without written permission from MPL AG Elektronikunternehmen. This manual reflects the Revision A of the Publication Date : January 1994 DISCLAIMER The information contained herein is believed to be accurate as of the date of this publication, however, MPL AG will not be liable for any damages, including indirect or consequential, arising out of the application or use of any product, circuit or software described herein. MPL AG reserves the right to make changes to any product herein to improve reliability, function or design. TRADEMARKS G-64/96 is a trademark of GESPAC SA AUTHOR'S NOTE Dear user of this product. It is my expressed wish that this product is not to be used to apply any kind of violence to anyone. Because there is no absolute criterium for violence, I trust your subjective interpretation if it s honest for you, it s ok for me. Disregarding my wish will not break the license agreement or any other contracts. However, ignoring it would mean not respecting the thoughts I had when putting my efforts into this product. A. Stöckli, MPL AG Our local distributor: Printed in Switzerland