IMEC CORE CMOS P. MARCHAL

Transcription

1 APPLICATIONS & 3D TECHNOLOGY IMEC CORE CMOS P. MARCHAL

2 OUTLINE What is important to spec 3D technology How to set specs for the different applications - Mobile consumer - Memory - High performance Conclusions 2

3 WHAT S IMPORTANT TO SPEC 3D TECHNOLOGY IMEC CORE CMOS

4 MECHANICAL STRESS OF THE INTEGRATION SCHEME You don t want this to happen when stacking a thin die on top of a thick bottom die How to avoid?! How to design for this!

5 COOLING SOLUTIONS High Performance high power densities, big heat sources, big thermal issues Thermal gradients on thinned top die a 2D stack (3D130C) Mobile consumer small heat sources, low power densities, minor thermal issues Strategies for spreading and removing heat from stack 5

6 MANAGING YIELD OF 3D INTERCONNECTS Yield TSV pitch=15um pitch 15um yield of TSV at edges is poor, center is excellent Yield TSV pitch=20um pitch 20um yield of TSV at edges is limited, center is excellent Higher density = more work for good yield

7 TSV INDUCED STRESS AND IMPACT ON DEVICE PERFORMANCE Decreased Ion i Single TSV at 1.7um TSV 5 4 5x5 S1 S2 S3 5 Rows TSVS4 4 3 S5 2 Columns 1 Increased Ion i 4.5% Ion variation near TSV Delta Ion vs ref [%] 7

8 TSV CAPACITANCE C dep 90 ff Majority carriers 1E-13 8E-14 Accumulation TSV Top Die TSV CTSV [F] 6E-14 Top Die 4E-14 Depletion C ox 35 ff Bottom Die C ox 2E-14 Bottom Die Vbias [V] 8

9 HOW TO SET SPECS FOR DIFFERENT APPLICATIONS IMEC CORE CMOS

10 DESIGN SPECS FOR 3D Stack organization Electric al Specs TSV Tech. Backside Tech.

11 DESIGN SPECS FOR 3D # TIERS, PACKAGE THICKNESS Stack organization Electric al Specs TSV Tech. Backside Tech. T2 T1 INTER-TIER IO (#, speed, power, Imax) 11

12 DESIGN SPECS FOR 3D # TIERS, PACKAGE THICKNESS PACKAGING TECHNOLOGY DIE THICKNESS mbump THICKNESS Stack organization T2 T1 mbump Ø INTER-TIER IO (#, speed, power, Imax) 12

13 DESIGN SPECS FOR 3D # TIERS, PACKAGE THICKNESS PACKAGING TECHNOLOGY DIE THICKNESS mbump THICKNESS RDL Backside Tech. T2 T1 mbump Ø mbump PITCH INTER-TIER IO (#, speed, power, Imax) 13

14 DESIGN SPECS FOR 3D # TIERS, PACKAGE THICKNESS PACKAGING TECHNOLOGY DIE THICKNESS TSV DIAMETER Ø TSV PITCH mbump THICKNESS TSV Tech. RDL L/S T2 T1 mbump Ø mbump PITCH INTER-TIER IO (#, speed, power, Imax) 14

15 # TIERS, PACKAGE THICKNESS PRIMARY DESIGN SPECS DRIVING 3D TECHNOLOGY TRADE-OFFS PACKAGING TECHNOLOGY DIE THICKNESS TSV DIAMETER Ø TSV PITCH mbump THICKNESS Stacking Organization TSV Tech. RDL L/S Electric al specs Backside Tech. T2 T1 RDL EOT TSV EOT mbump Ø mbump PITCH INTER-TIER IO (#, speed, power, Imax) 15

16 3D TECHNOLOGY TRENDS Convergence MOBILE CONSUMER High performance MEMORY Memory HIGH PERFORMANCE 16

17 3D TECHNOLOGY TRENDS Convergence MOBILE CONSUMER High performance MEMORY Memory HIGH PERFORMANCE 17

18 MOBILE CONSUMER ELECTRONICS Modem 2G GSM/GPRS/EDGE 3G CDMA2000/EV-HDO HSPA/WCDMA 4G LTE Power Management RF Multimedia >30MP Camera Video encoding/decoding 2D/3D gaming Audio Low power >1 GHz/1V Quadcore CPU Memory 256gB NVM >8gb DRAM Low cost 18

19 APPLICATION TRENDS MULTIMEDIA PERFORMANCE 8Gb 8-32Gb LPPDDR2 HD fs DRAM Bandwidth (Gb/s) HD1080 HD720 Application Throughput (Gb/s) Energy/bit (pj) source: STE ISSCC

20 APPLICATION TRENDS MULTIMEDIA PERFORMANCE Application throughput to DRAM memory increases with every generation. As memory bandwidth cannot be 100% efficiently used, the memory bandwidth is over-designed typically by 4x Hence, in near future, single LPDDR will not meet the targets set by the application. Possible solutions are: Use of multiple LPDDR memories in parallel Wide-IO DRAM technology As bandwidth increases, we must reduce energy/bit in IOs to limit DRAM power below 0.5W as required by the system Finally, observe that the memory storage requirements may vary between 8-32Gb. Again in excess of single DRAM die capacity 20

21 WIDE IO DRAM - BEYOND LPDDR2 12.8GB/s Mobile wide IO on logic ~1k TSV 1-2 layers DRAM Low power/noise Low design complexity IO frequency (Mhz) 8x Logic die FCBGA substrate IO count Low parallelism High design complexity 21

22 WIDE IO DRAM - BEYOND LPDDR2 Increasing bandwidth involves a trade-off between package design complexity/power and number of IO pins on DRAM die 3D changes this trade-off in favor of more pins. Lot of R&D is ongoing to define wide IO DRAM interface, which have up to 1k 3DIOs * More than one DRAM must be stacked to achieve the desired DRAM density (Max available density can be up to 8Gb per die, but up to 32Gb may be required). * cfr. QCT IEDM09, STE ISSCC10, Samsung ISSCC10 22

23 SPECS FOR MOBILE 2015 Trend Notes yield YIELD $ COST # TIERS PACKAGE THICKNESS 3-4 <0.6mm Package thickness does not scale T1 T2 3D IO SPECIFICATION >1k TSV/tier >400mHz <2.5pJ/bit Cfr. previous slides

24 SPECS FOR MOBILE 2015 Trend Notes yield YIELD $ COST # TIERS PACKAGE THICKNESS 3-4 <0.6mm Package thickness does not scale T1 T2 3D IO SPECIFICATION >1k TSV/tier >400mHz <2.5pJ/bit Cfr. previous slides SILICON DIE THICKNESS >40-30mm Minimum DRAM die thickness mbump PITCH 20-10mm Scaling further does not bring significant added value for 1k TSVs TSV Ø/PITCH 5-3mm/ 20mm-10mm TSV Ø scaling if it reduces the cost or improves reliability of TSV process RDL L/S Preferably no RDL Eliminating RDL decreases cost by 12% (assuming large volumes) TSV Cox <0.2pF No aggressive Cox scaling to achieve energy target for 3D IO 24

25 3D TECHNOLOGY TRENDS Convergence yield $ LP MOBILE CONSUMER YIELD COST LOW POWER N>2 MIXED SIGNAL High performance MEMORY Memory HIGH PERFORMANCE 25

26 3D INTEGRATION TECHNOLOGY TRENDS Convergence yield $ LP MOBILE CONSUMER YIELD COST LOW POWER N>2 MIXED SIGNAL High performance MEMORY Memory HIGH PERFORMANCE 26

27 DELIVERING MEMORY BANDWIDTH TO HIGH PERFORMANCE SYSTEMS Mobile 12.8GB/s Graphics 512GB/s 4x Low power/noise Low design complexity IO frequency (Mhz) Low parallelism High design complexity IO count 27

28 GRAPHICS MEMORY STACK 4Gb DRAM tier Logic IO + Power management IOs Data path Advanced Package substrate Processor/GPU Up to eight tiers of 4Gb for 32Gb Graphics memory source: Samsung ISSCC 2010 High number of TSVs - 4k-8k TSVs & mbumps per tier Thermal impact of GPU directly affects stacked DRAM (GPU W, DRAM thermal budget <85-95 ) 28

29 MEMORY yield YIELD $ COST N>8 WLP PACKAGING 10Y RELIABILITY 2015 Trend Notes TIERS PACKAGE THICKNESS >8 <0.5mm Many more tiers in the same package thickness WLP? T1 T2 3D IO SPECIFICATION >4k TSV/tier >1GHz <2.5pJ/bit Previous slides 29

30 yield KEY SPECS FOR MEMORY YIELD $ COST 2015 Trend Notes N>8 WLP PACKAGING 10Y RELIABILITY TIERS PACKAGE THICKNESS >8 <0.5mm Many more tiers in the same package thickness WLP? T1 T2 3D IO SPECIFICATION >4k TSV/tier >1GHz <2.5pJ/bit Previous slides SILICON DIE THICKNESS >40-30mm Minimum DRAM die thickness mbump PITCH 20-10mm Lower = better TSV Ø/PITCH 5-3mm/ 20-10mm RDL L/S Preferably no RDL TSV Cox <0.1pF Lower Cox with respect to mobile consumer as Ctsv may add up when stacking 30

31 3D TECHNOLOGY TRENDS Convergence yield $ LP MOBILE CONSUMER YIELD COST LOW POWER N>2 MIXED SIGNAL yield High performance $ 10Y WLP MEMORY YIELD COST RELIABILITY N>8 PACKAGING Memory HIGH PERFORMANCE

32 3D TECHNOLOGY TRENDS Convergence MOBILE CONSUMER yield $ YIELD COST yield High performance MEMORY YIELD $ COST LP LOW POWER N>2 WLP 10Y RELIABILITY MIXED SIGNAL N>8 PACKAGING Memory HIGH PERFORMANCE 32

33 SILICON INTERPOSER FOR HIGH PERFORMANCE System Integration Logic die (E.g. processor, GPU, FPGA) 20mmx30mm 5-6k IOs ELK/ULK BEOL & lead-free solder 1Ghz DRAM IO Analog Product customization Better form factor Improve Yield/Reliability Silicon interposer acts as stress buffer between ELK & package substrate Reduce Packaging cost* Less routing layers in the package substrate Easier Circuit Design Silicon interposer 5-10k mbumps/mixed signal 4Ghz Short in package connections Less signal/power integrity challenges Decrease power and footprint for high speed IOs * Source ASE ISSCC10 33

34 PATHFINDING DESIGN/TECHNOLOGY TRADE-OFFS µbump connections Dielectric layers [Dt3] Dt2 Dt1 DC1 Si - TSV Db1 TSV type Conformal/filled? Diameter, Aspect ratio? Flip-chip pillar or solder bump or CSP? Multilayer thin film build-up: #layers, line width & spacing, via density? Metal layers Mtp [Mt2] Optional Mt1 MC2 MC1 Mb1 Mbp Integrated passives? Backside RDL Active? 34

35 3D TECHNOLOGY TRENDS CONCLUSIONS Convergence yield $ LP MOBILE CONSUMER YIELD COST LOW POWER N>2 MIXED SIGNAL yield High performance $ 10Y WLP MEMORY YIELD COST RELIABILITY N>8 PACKAGING Memory yield 10Y HIGH PERFORMANCE YIELD INTERPOSER RELIABILITY COOLING 35