Alex Milenkovich 1. CPE/EE 421 Microcomputers: Motorola The CPU Hardware Model. Outline

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1 Outline CPE/EE 421 Microcomputers: Motorola The CPU Hardware Model Instructor: Dr Aleksandar Milenkovic Lecture Notes interface Timing diagram Minimal configuration using the Extensions Exception Processing CPE/EE 421/521 Microcomputers Interface M68000: 64 pins, arranged in 9 groups: Address Bus: A 01 A 23 Data Bus: D 00 D 15 Asynchronous bus control: AS*, R/W*, UDS*, LDS*, DTACK*, BERR* Synchronous bus control: E, VPA*, VMA* Bus arbitration control: BR*, BG*, BGACK* Function code: FC0, FC1, FC2 System control: CLK, RESET*, HALT* Interrupt control: IPL0*, IPL1*, IPL2* Miscellaneous: Vcc(2), Gnd(2) Legend: Type XX Input XX Output XX Input/Output CPE/EE 421/521 Microcomputers Interface, cont d Classification of pins based on function SYSTEM SUPPORT PINS Essential in every system (power supply, clock, ) MEMORY AND PERIPHERAL INTERFACE PINS Connect the processor to an external memory subsystem SPECIAL-PURPOSE PINS (not needed in a minimal application of the processor) Provide functions beyond basic system functions Terminology Asterisk following a name: indicates the signal is active low Signal is asserted means signal is placed in its active state Signal is negated means signal is placed in its inactive state CPE/EE 421/521 Microcomputers 4 Alex Milenkovich 1

2 System Support Pins Power Supply Single +5V power supply: 2 Vcc pins and 2 ground pins Clock Single-phase, TTL-compatible signal Bus cycle: memory access, consists of a minimum 4 clock cycles Instruction: consists of one or more bus cycles RESET* Forces the into a known state on the initial application of power: supervisor s A7 is loaded from memory location $ Program counter is loaded from address $ During power-up sequence must be asserted together with the HALT* input for at least 100 ms. Acts also as an output, when processor executes the instruction RESET (used to reset peripherals w/out resetting the 68000) CPE/EE 421/521 Microcomputers 5 System Support Pins, cont d HALT* In simple systems can be connected together with RESET* Can be used: by external devices to make the stop execution after current bus cycle (and to negate all control signals) to single-step (bus cycle by bus cycle) through program to rerun a failed bus cycle (if memory fails to respond correctly) in conjunction with the bus error pin, BERR* It can be used as an output, to indicate that the found itself in situation from which it cannot recover (HALT* is asserted) CPE/EE 421/521 Microcomputers 6 Memory and Peripheral Interface Pins Memory and Peripheral Interface Pins, cont d Address Bus 23-bit address bus, permits bit words to be addressed Tri-state output pins (to permit devices other then the CPU to take a control over it) Auxiliary function: supports vectored interrupts Address lines A01, A02, A03 indicate the level of the interrupt being serviced All other address lines are set to a high level Data Bus AS* When asserted, indicates that the content of the address bus is valid. R/W* Determines the type of a memory access cycle CPU is reading from memory: R/W* = 1 CPU is writing to memory: R/W* = 0 If CPU is performing internal operation, R/W* is always 1 When CPU relinquishes control of its busses, R/W* is undefined UDS* and LDS* Bi-directional 16-bit wide data bus Used to determine the size of the data being accessed During a CPU read cycle acts as an input If both UDS* and LDS* are asserted, word is accessed During a CPU write cycle acts as an output R/W* UDS* LDS* Byte operations: only D00-D07 or D08-D15 are active 010: write lower byte (D Interrupting device identifies itself to the CPU by placing an 00 D 07 : data valid, replicated on D 8 -D 15 ) 011: write word (D interrupt vector number on D00-D07 during an interrupt 00 D 15 : data valid) 101: read upper byte (D acknowledge cycle 00 D 07 : invalid, D 8 -D 15 data valid) CPE/EE 421/521 Microcomputers 7 CPE/EE 421/521 Microcomputers 8 Alex Milenkovich 2

Memory and Peripheral Interface Pins, cont d DTACK* (Data Transfer Acknowledge) Handshake signal generated by the device being accessed Indicates that the contents of the data bus is valid If DTACK*

3 Memory and Peripheral Interface Pins, cont d DTACK* (Data Transfer Acknowledge) Handshake signal generated by the device being accessed Indicates that the contents of the data bus is valid If DTACK* is not asserted, CPU generates waitstates until DTACK goes low or until an error state is declared. When DTACK* is asserted, CPU completes the current access and begins the next cycle Memory and Peripheral Interface Pins, cont d Figure 4.3 DTACK* has to be generated a certain time after the beginning of a valid memory access (timer supplied by the system designer). CPE/EE 421/521 Microcomputers 9 CPE/EE 421/521 Microcomputers 10 Special-Function Pins of the BERR* (Bus Error Control) Enables the to recover from errors within the memory system BR*, BG*, BGACK* (Bus Arbitration Control) Used to implement multiprocessor systems based on M68000 FC0-FC2 (Function Code Output) Indicate the type of cycle currently being executed Becomes valid approximately half a clock cycle earlier than the contents of the address bus IPL0*-IPL2* (Interrupt Control Interface) Used by an external device to indicate that it requires service 3-bit code specifies one of eight levels of interrupt request Special-Function Pins of the Function Code Outputs Function Code Output FC2 FC1 FC0 Processor Cycle Type Undefined, reserved User data User program Undefined, reserved Undefined, reserved Supervisor data Supervisor program CPU space (interrupt acknowledge) CPE/EE 421/521 Microcomputers 11 CPE/EE 421/521 Microcomputers 12 Alex Milenkovich 3

4 Special-Function Pins of the Using FC Outputs Special-Function Pins of the Asynchronous Bus Control User data memory User program memory Figure 4.8 Supervisor program and data memory CPE/EE 421/521 Microcomputers 13 The is not fully asynchronous because its actions are synchronized with a clock input Figure 4.11 It can prolong a memory access until an ACK is received, but it has to be in increments of one clock cycle CPE/EE 421/521 Microcomputers 14 Outline interface Timing diagram Minimal configuration using the Extensions Exception Processing Timing Diagram of a Simple Flip-Flop Idealized form of the timing diagram Actual behavior of a D flip-flop Data hold time Data setup time Max time for output to become valid after clock CPE/EE 421/521 Microcomputers 15 CPE/EE 421/521 Microcomputers 16 Alex Milenkovich 4

General form of the timing diagram An alternative form of the timing diagram The Clock A microprocessor requires a clock that provides a stream of timing pulses to control its internal operations A

5 General form of the timing diagram An alternative form of the timing diagram The Clock A microprocessor requires a clock that provides a stream of timing pulses to control its internal operations A memory access takes a minimum of eight clock states numbered from clock state S0 to clock state S7 CPE/EE 421/521 Microcomputers 17 CPE/EE 421/521 Microcomputers 18 A memory access begins in clock state S0 and ends in state S7 The most important parameter of the clock is the duration of a cycle, t CYC. CPE/EE 421/521 Microcomputers 19 CPE/EE 421/521 Microcomputers 20 Alex Milenkovich 5

6 At the start of a memory access the CPU sends the address of the location it wishes to read to the memory Address Timing We are interested in when the generates a new address for use in the current memory access The next slide shows the relationship between the new address and the state of the s clock CPE/EE 421/521 Microcomputers 21 CPE/EE 421/521 Microcomputers 22 Initially, in state S0 the address bus contains the old address In state S1 a new address becomes valid for the remainder of the memory access CPE/EE 421/521 Microcomputers 23 The time at which the contents of the address bus change can be related to the edges of the clock. CPE/EE 421/521 Microcomputers 24 Alex Milenkovich 6

7 Address Timing Let s look at the sequence of events that govern the timing of the address bus The old address is removed in state S0 The address bus is floated for a short time, and the CPU puts out a new address in state S1 The old address is removed in clock state S0 and the address bus floated CPE/EE 421/521 Microcomputers 25 CPE/EE 421/521 Microcomputers 26 t CLAV The designer is interested in the point at which the address first becomes valid. This point is t CLAV seconds after the falling edge of S0. CPE/EE 421/521 Microcomputers 27 The memory needs to know when the address from the CPU is valid. An address strobe, AS*, is asserted to indicate that the address is valid. CPE/EE 421/521 Microcomputers 28 Alex Milenkovich 7

8 Address and Address Strobe We are interested in the relationship between the time at which the address is valid and the time at which the address strobe, AS*, is asserted When AS* is active-low it indicates that the address is valid We now look at the timing of the clock, the address, and the address strobe CPE/EE 421/521 Microcomputers 29 AS* goes active low after AS* goes inactive the address has become valid high before the address changes CPE/EE 421/521 Microcomputers 30 AS* goes low in clock state S2 The Data Strobes The has two data strobes LDS* and UDS*. These select the lower byte or the upper byte of a word during a memory access To keep things simple, we will use a single data strobe, DS* The timing of DS* in a read cycle is the same as the address strobe, AS* CPE/EE 421/521 Microcomputers 31 CPE/EE 421/521 Microcomputers 32 Alex Milenkovich 8

9 The Data Bus During a read cycle the memory provides the CPU with data The next slide shows the data bus and the timing of the data signal Note that valid data does not appear on the data bus until near the end of the read cycle The data strobe, is asserted at the same time as AS* in a read cycle CPE/EE 421/521 Microcomputers 33 CPE/EE 421/521 Microcomputers 34 Data from the memory appears near the end of the read cycle Analyzing the Timing Diagram We are going to redraw the timing diagram to remove clutter We aren t interested in the signal paths themselves, only in the relationship between the signals CPE/EE 421/521 Microcomputers 35 CPE/EE 421/521 Microcomputers 36 Alex Milenkovich 9

10 We are interested in the relationship between the clock, AS*/DS* and the data in a read cycle CPE/EE 421/521 Microcomputers 37 The earliest time at which the memory can begin to access data is measured from the point at which the address is first valid CPE/EE 421/521 Microcomputers 38 Address becomes valid Data becomes valid The time between address valid and data valid is the memory s CPE/EE access 421/521 time, Microcomputers t 39 acc Calculating the Access Time We need to calculate the memory s access time By knowing the access time, we can use the appropriate memory component Equally, if we select a given memory component, we can calculate whether its access time is adequate for a particular system CPE/EE 421/521 Microcomputers 40 Alex Milenkovich 10

11 Data from the memory is latched into the by the falling edge of the clock in state S6. CPE/EE 421/521 Microcomputers 41 Data must be valid t DICL seconds before the falling edge of S6 CPE/EE 421/521 Microcomputers 42 We know that the time between the address valid and data valid is t acc CPE/EE 421/521 Microcomputers 43 The address becomes valid t CLAV seconds after the falling edge of S0 CPE/EE 421/521 Microcomputers 44 Alex Milenkovich 11

12 From the falling edge of S0 to the falling edge of S6: the address becomes valid the data is accessed the data is captured CPE/EE 421/521 Microcomputers 45 The falling edge of S0 to the falling edge of S6 is three clock cycles CPE/EE 421/521 Microcomputers 46 Timing Example clock 8 MHz t CYC = 125 ns CPU t CLAV = 70 ns CPU t DICL = 15 ns What is the minimum t acc? 3 t CYC = t CLAV + t acc + t DICL 375 = 70 + t acc + 15 t acc = 290 ns 3 t cyc = t CLAV + t acc + t DICL CPE/EE 421/521 Microcomputers 47 CPE/EE 421/521 Microcomputers 48 Alex Milenkovich 12

13 A Read Cycle Extended Read Cycle DTACK* did not go low at least 20ns before the falling edge of state S4 Figure 4.15 Figure 4.14 CPE/EE 421/521 Microcomputers 49 Designer has to provide logic to control DTACK* CPE/EE 421/521 Microcomputers 50 Memory Timing Diagram Memory Timing (min 200ns Diagram, address stable) cont d The 6116 static memory component 2K x 8bit memory byte-oriented! Two 6116 s configured in parallel to allow word accesses Eleven address inputs (usually derived from UDS*/LDS*) (max 200ns) Data is floating Figure 4.18 CPE/EE 421/521 Microcomputers 51 Figure 4.17 Assumptions: (max 15ns) R/W* is high for the duration of the read cycle OE* is low (max 50ns) CPE/EE 421/521 Microcomputers 52 Alex Milenkovich 13

14 RAMCS Inputs UDS Outputs CS2 AS* LDS* CS1* Operation 1 X* X* A 01 X 1 1* No operation D 00 X 1 X X 1 1 No operation Word read D A Upper byte read Lower byte read No operation Connecting The 6116 RAM to a CPU A 12 A 23 D 08 D 15 A 01 A 11 A 01 A 11 Figure 4.19 CPE/EE 421/521 Microcomputers 53 Connecting The 6116 RAM to a CPU Timing Diagram Figure ns 10ns 60ns Turnoff time = 140ns CPE/EE 421/521 Microcomputers 54 Timing Example clock 8 MHz t CYC = 125 ns CPU t CLAV = 70 ns CPU t DICL = 15 ns What is the minimum t acc? 3 t CYC >t CLAV +t acc +t DICL 375 > 70 + t acc + 15 t acc < 290 ns (or t AA from the timing diagram, access time) For the 12.5MHz version of t CYC = 80 ns CPU t CLAV = 55 ns CPU t DICL = 10 ns 3 80 > 55 + t acc + 10 t acc < 175 ns Remember, maximum t AA for the 6116 RAM was 200 ns CPE/EE 421/521 Microcomputers Write Cycle transmits a byte or a word to memory or a peripheral Essential differences: The CPU provides data at the beginning of a write cycle One of the bus slaves (see later) reads the data In a read cycle DS* and AS* were asserted concurrently This will be not a case here! Reason for that: asserts DS* only when the contents of data bus have stabilized Therefore, memory can use UDS*/LDS* to latch data from the CPU CPE/EE 421/521 Microcomputers 56 Alex Milenkovich 14

15 Simplified write cycle timing diagram Write Cycle In a write cycle: UDS*/LDS* is asserted one cycle after AS* Follow this sequence of events in a write cycle: Address stable AS* asserted R/W* brought low Data valid DS* asserted Figure 4.22 CPE/EE 421/521 Microcomputers 57 CPE/EE 421/521 Microcomputers 58 Figure 4.23 Write Cycle Timing Diagram of a 6116 RAM Write Cycle Timing Diagram of a 6116 RAM, cont d Write recovery time (min 10ns) Address setup time (min 20ns) Address valid to end of write (min 120ns) Write pulse width (min 90ns) Figure 4.24 CPE/EE 421/521 Microcomputers 59 Write cycle ends with either CS* or WE* being negated (CS* and WE* internally combined) An address must be valid for at least t AS nanoseconds before WE* is asserted Must remain valid for at least t WR nanoseconds after WE* is negated Data from the CPU must be valid for at least t DW nanoseconds before WE* is negated Must remain valid for at least t DH nanoseconds after the end of the cycle CPE/EE 421/521 Microcomputers 60 Alex Milenkovich 15

16 Designing a Memory Subsystem An Example Design a M68000 memory subsystem using Two 32K 8 RAM chips residing at address $ Two 8K 8 RAM chips residing in the consecutive window LS 138 (3 to 8 decoder) and basic logic gates Solution 32K is 4 8K => Let s split the address space into 8K modules In total, we have five (4+1) 8K windows To address each line in 8K window => 13 bits (23*210 = 213 = 8K) To address five modules we need 3 bits Don t forget that there is no A0, we will use LDS/UDS A 23 A 22 A 21 A 20 A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A 09 A 08 A 07 A 06 A 05 A 04 A 03 A 02 A 01 A 00 A17... A23 Designing a Memory Subsystem An Example A14 A15 A16 AS* Vcc module address LS138 A B C E1 E2 E3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 address within 8K module RAM1* RAM2* LDS* UDS LDS R1CSL* R2CSL* R1CSU* R2CSU* CPE/EE 421/521 Microcomputers 61 UDS* CPE/EE 421/521 Microcomputers 62 Designing a Memory Subsystem An Example Interrupt Control Interface (details later) D0..D15 A1..A23 low p ri A1 A0 D0 D0 A1 A0 D0 D8... A15 A14 D1 D2 D1 D2... A15 A14 D1 D2 D9 D10 o ri R/W* R1CSL* WE* CE* OE* RAM 32Kx8 D3 D4 D5 D6 D7 D3 D4 D5 D6 D7 R/W* R1CSLU* WE* CE* OE* RAM 32Kx8 D3 D4 D5 D6 D7 D11 D12 D13 D14 D15 high t y R/W* R2CSL* A1 A0... A13 A12 WE* CE* OE* RAM 8Kx8 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 R/W* R2CSLU* A1 A0... A13 A12 WE* CE* OE* RAM 8Kx8 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Figure 4.9 CPE/EE 421/521 Microcomputers 63 CPE/EE 421/521 Microcomputers 64 Alex Milenkovich 16

Bus Arbitration Control Bus Arbitration Control, cont d When 68000 controls the address and data buses, we call it the bus master The 68000 may allow another 68000 or DMA controller to take control

17 Bus Arbitration Control Bus Arbitration Control, cont d When controls the address and data buses, we call it the bus master The may allow another or DMA controller to take control over buses In the system with only one bus master, would have permanent control of the address and data buses Address bus Data bus Control bus Slave module Memory Arbitration bus Master module Master module CPU Local CPU Local memory memory I/O I/O CPE/EE 421/521 Microcomputers must respond to BR* request (it cannot be masked) Assertion of BG* indicates that the bus will be given up at the end of present bus cycle Requesting device waits until AS*, DTACK*, and BGACK* have been negated, and only then asserts its own BGACK* output Old master negates its BG*, and BR* can be asserted by another potential master CPE/EE 421/521 Microcomputers 66 Data Bus Contention in Microcomputers Data Bus Contention in Microcomputers, cont d Situation where more than one device attempts to drive the bus simultaneously Example: Two memory modules, M1 selected during read cycle 1, M2 selected during read cycle 2 Assumption: M1 has data bus drivers with relatively long turn-off times M2 has data bus drivers with relatively short turn-on times Long turn-off time Short turn-on time Figure 4.27a CPE/EE 421/521 Microcomputers 67 CPE/EE 421/521 Microcomputers 68 Alex Milenkovich 17

18 Bus Contention and Data Bus Transceivers Outline interface Timing diagram Minimal configuration using the Extensions Exception Processing Data bus transceiver consists of a transmitter (driver) and a receiver Driver tristate output, can be driven high, low, or internally disconnected form the rest of the circuit Two control inputs: Enable (active low) and DIR (direction) Dynamic data bus contention CPE/EE 421/521 Microcomputers 69 CPE/EE 421/521 Microcomputers 70 DESIGN CONSTRAINTS Used in stand-alone mode Classroom teaching aid 16 KB EPROM-based monitor Speed is not important At least 4 KB RAM 1 serial and 1 parallel port Memory expandable No interrupts and multiple processors MAJOR COMPONENTS ROM Two 8K 8 components RAM Two 2K 8 components Parallel 6821 Peripheral Interface Adapter (PIA) Serial 6850 Asynchronous Comm. Interface Adapter (ACIA) CPE/EE 421/521 Microcomputers 71 CPE/EE 421/521 Microcomputers 72 Alex Milenkovich 18

DESIGH CHOICES The 68000 s Reset Sequence Chose the location of ROM (16KB) and RAM (8 KB) within the address space (16 MB) Unimportant, as long as the reset vectors are located at $00 0000 Chose the

19 DESIGH CHOICES The s Reset Sequence Chose the location of ROM (16KB) and RAM (8 KB) within the address space (16 MB) Unimportant, as long as the reset vectors are located at $ Chose the location of memory-mapped peripherals Control of DTACK* (is delay applied or not?) RESET SEQUENCE Set SR S bit to 1 Set SR T bit to 0 Set SR mask to 111 Fetch SSP from address 0 Transfer longword to SSP Bus error occurs? Double bus error FATAL ERROR Fetch initial PC from address 4 Bus error occurs? Transfer longword to PC Begin processing in the supervisor state CPE/EE 421/521 Microcomputers 73 CPE/EE 421/521 Microcomputers 74 REMEMBER When the RESET* pin is asserted for the appropriate duration: SR = $2700 SSP is loaded with the $ PC is loaded with the $ CPE/EE 421/521 Microcomputers 75 Block Diagram of a based microcomputer Figure 4.43 CPE/EE 421/521 Microcomputers 76 Alex Milenkovich 19

20 Memory and Peripheral Components We assigned address lines to address pins, and data lines to data pins. Before designing logic that will generate chip select signals, we have to decide about RAM/ROM location. To assure that the reset vector location is at $ , let s situate 16 KB of ROM at $ CPE/EE 421/521 Microcomputers 77 Memory and Peripheral Components Figure 4.44 CPE/EE 421/521 Microcomputers 78 Control Section We will divide the memory space $ $01 FFFF into eight blocks of 16 KB (IC1a,b, IC2a, IC3) 16 KBytes of ROM are at $ to $00 3FFF Where is the RAM situated? Peripherals? Note: there is no delay applied to DTACK*. What will happen if we access nondecoded memory? Control Section Figure 4.45 CPE/EE 421/521 Microcomputers 79 CPE/EE 421/521 Microcomputers 80 Alex Milenkovich 20

21 Different approaches to memory arrangement Largest memory window (16 KB) [MEMORY GAPS] Different approaches to memory arrangement, cont d Smallest memory window (4 KB) [NO MEMORY GAPS] A 23 A 15 A 14 A 13 A 12 A 11 A 1 A 23 A 17 A 16 A 15 A 14 A 13 A 1 SELECT DECODER DECODER SELECT DECODER DECODER A15... A23 A12 A13 A14 AS* Vcc A B C E1 E2 E3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 ROM (16 KB) 4 Windows (Blocks) RAM Q7 CPE/EE 421/521 Microcomputers 81 CPE/EE 421/521 Microcomputers 82 Outline interface Timing diagram Minimal configuration using the Extensions Exception Processing How can we make it better? ROM is EPROM-based, and thus slower With EPROMs from the same generation, we ll need wait states, maybe even with RAM components Watchdog for non-decoded memory addresses CPE/EE 421/521 Microcomputers 83 CPE/EE 421/521 Microcomputers 84 Alex Milenkovich 21

22 How can we make it better? How can we make it better? Cont d CONTROL OF INTERRUPTS Use 74LS148 priority encoder to provide 7 levels of interrupt EXTERNAL BUS INTERFACE CPU can supply only the limited current to drive the bus SOLUTION: Bus drivers (buffers) Figure 4.46 CPE/EE 421/521 Microcomputers 85 CPE/EE 421/521 Microcomputers 86 DTACK* Generation DTACK* generator based on a shift register DTACK* Generation Shift register and its timing diagram Figure 4.72 CPE/EE 421/521 Microcomputers 87 CPE/EE 421/521 Microcomputers 88 Alex Milenkovich 22

23 DTACK* Generation Shift register and its timing diagram DTACK* Generation DTACK* generator based on a counter Figure 4.74 CPE/EE 421/521 Microcomputers 89 CPE/EE 421/521 Microcomputers 90 Outline Interrupt Processing Mechanism interface Timing diagram Minimal configuration using the Extensions Exception Processing Interrupt is an asynchronous event When an interrupt occur, the computer can: Service it Ignore it (for the time being) CPE/EE 421/521 Microcomputers 91 CPE/EE 421/521 Microcomputers 92 Alex Milenkovich 23

Interrupt Control Interface Interrupt processing mechanism, cont d low high p ri o ri t y Sequence of actions when an interrupt is being serviced: 1.

24 Interrupt Control Interface Interrupt processing mechanism, cont d low high p ri o ri t y Sequence of actions when an interrupt is being serviced: 1. The computer completes its current machine-level instruction 2. The contents of PC is saved (on stack) 3. The state of the processor (status word) is saved on the stack 4. Jump to the location of the interrupt handling routine Figure 4.9 CPE/EE 421/521 Microcomputers 93 CPE/EE 421/521 Microcomputers 94 Interrupt processing mechanism, cont d The interrupt is transparent to the interrupted program Interrupt request: Can be deferred or denied When it is deferred, it is said to be masked Special one: nonmaskable interrupt request (NMI) The NMI: IRQ7 (MSP430: RST*/NMI pin) Prioritized interrupts Vectored interrupts Requesting peripheral identifies itself, CPU doesn t have to poll the status of each device to discover the interrupter CPE/EE 421/521 Microcomputers 95 The Interrupt Interface CPE/EE 421/521 Microcomputers 96 Alex Milenkovich 24

25 The Interrupt Interface The Interrupt Interface Reset, bus error, address error, and trace exceptions take precedence over an interrupt A level 7 interrupt CAN interrupt level 7 interrupt CPE/EE 421/521 Microcomputers 97 CPE/EE 421/521 Microcomputers 98 Interrupt Timing Diagram Processing the Interrupt CPE/EE 421/521 Microcomputers 99 CPE/EE 421/521 Microcomputers 100 Alex Milenkovich 25

26 Exception Vectors Vectored Interrupts CPE/EE 421/521 Microcomputers 101 A vector is associated with each type of exception Vector is the 32-bit absolute address of the appropriate exception handling routine 256 exception vectors, 32 bits (4 bytes) each, extending from address $ to $00 03FF Vectors 0-63 : EXCEPTIONS Vectors : INTERRUPT HANDLING ROUTINES Difference between the reset vector and all other exceptions: It requires 2 longwords Located in SP space (FC = 110); others are in SD space (FC = 101) CPE/EE 421/521 Microcomputers 102 Privileged States and the Privileged States and the 68000, cont d User programs operate only An exception always forces the into the supervisor state CPE/EE 421/521 Microcomputers 103 CPE/EE 421/521 Microcomputers 104 Alex Milenkovich 26

The 68000 Exceptions Interrupts and Real-time Processing Multitasking (multiprogramming) concurrent execution multiple tasks (processes) resource sharing (multiple users using the same printer)

27 The Exceptions Interrupts and Real-time Processing Multitasking (multiprogramming) concurrent execution multiple tasks (processes) resource sharing (multiple users using the same printer) Multiprocessing parallel execution multiple PROCESSORS! CPE/EE 421/521 Microcomputers 105 CPE/EE 421/521 Microcomputers 106 Multitasking Real-Time Operating System Real time - meaningful time fast enough to influence the system at that moment space shuttle / chemical plant Operating system (to schedule activities) Interrupt mechanism (to switch between tasks) CPE/EE 421/521 Microcomputers 107 Real-time system Optimizes the response time to events Tries to use resources efficiently Multitasking system Optimizes resource utilization Tries to provide a reasonable response time CPE/EE 421/521 Microcomputers 108 Alex Milenkovich 27

28 Real-Time Kernel Scheduler is the kernel, nucleus, of a real-time OS Functions a first-level interrupt handler scheduler - the sequence in which tasks are executed READY BLOCKED interprocess communication Task States Ready Running RUNNING Blocked (dormant) Tasks Volatile portion (PC, status, registers) Task control block (TCB) Task ID Task block pointer PC SP status register other registers Task status run / ready / blckd Task priority Task time allocation how many slots Figure 6.25 CPE/EE 421/521 Microcomputers 109 CPE/EE 421/521 Microcomputers 110 Exception Handling and Tasks Preemptive real-time OS: RTC generates periodic interrupts used by the kernel to locate and run the next task How to deal with other interrupts? Service them independently, subject to priority Integrate them into the real-time task structure Vectored interrupt Exception Real-time clock interrupt Turn on ready to run flag of appropriate task Turn on ready to run flag of appropriate task Call RT task scheduler and switch tasks RTE CPE/EE 421/521 Microcomputers 111 Alex Milenkovich 28

CPE/EE 421/521 Fall 2004 Chapter 4 The CPU Hardware Model. Dr. Rhonda Kay Gaede UAH. The CPU Hardware Model - Overview

CPE/EE 421/521 Fall 2004 Chapter 4 The 68000 CPU Hardware Model Dr. Rhonda Kay Gaede UAH Fall 2004 1 The 68000 CPU Hardware Model - Overview 68000 interface Timing diagram Minimal configuration using the