Using ASIC circuits. What is ASIC. ASIC examples ASIC types and selection ASIC costs ASIC purchasing Trends in IC technologies
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1 Using ASIC circuits What is this machine? ASIC examples ASIC types and selection ASIC ASIC purchasing Trends in IC technologies Turo Piila Turo Piila 2 What is ASIC Floorplan and layout of a SoC ASIC SoC=System-On-Chip ASIC = Application Specific Integrated Circuit = User Specific Integrated Circuit Designed specially for one product or application Optimal implementation (price,, performance...) User specifies the circuit User pays the development and tooling Only the user can buy the ASIC Turo Piila Turo Piila 4
2 FPGA GATE ARRAY ASIC circuit types ANALOG ARRAY User Logic only Logic only Analogue only Maximum 5 M Maximum gates 50M gates transistors STANDARD CELL Analogue and logic 50M gates + up, memory + analogue FULL CUSTOM Analogue and logic 500M transistors No prototype Low prototype Low prototype High protot. High protot. High product. Medium prod. Medium prod. Low product. Low product. USER PROGR. SEMICUSTOM CIRCUITS CUSTOM CIRCUITS No masks Some masks (1-10) All masks (15-30) ASIC terminology IC Integrated Circuit wafer cm diameter silicon slice on which the ICs are manufactured chip, die single (unpackaged, naked) IC Fab IC manufacturing factory NRE Non Recurring Engineering, Cost of IC manufacturing tools (masks, test program, prototype processing) ASP Average Sales Price (of an IC) wafer sort testing of all ICs on a wafer Turo Piila Turo Piila 6 IC technologies Technologies: CMOS, BiCMOS, SiGe, GaAs, Bipolar IC process line width (feature size) in microns (µm) µm (500 gates/mm g/mm2) Smaller line width gives a smaller (=cheaper) chip with more speed and less power NRE are higher for smaller line widths New process (technology) generation every second year Similar technologies from different fabs are not identical, design cannot be transferred as such Process complexity grows Turo Piila Turo Piila 8
3 0.18um CMOS circuit, 2 million transistors Technology selection 1 Performance issues packing density speed high or low voltage memories analog components (R,C,L,npn, zener) package options reliability operating conditions (car, space,military..) Turo Piila 9 Technology selection 2 Stability issues semiconductor process lifetime 5-10 years new process can be unstable design support for new processes is limited mature process may be discontinued too early match process lifecycle with your product lifetime Turo Piila 10 Technology selection 3 Cost structure Cost issues process age / packing density process maturity vs. peak production vendor size, optimum production volume currency risks country risks (taxes and tolls, earthquakes, wars) general semiconductor market situation Total = fixed + variable x amount Fixed design NRE Variable silicon processing packaging testing Turo Piila Turo Piila 12
4 Medium size ASIC-project Feasibility study, specification 1-2 months Circuit design and verification 6-9 months Layout design 1-3 months Prototype manufacturing, test design 2-3 months Prototype testing 2-4 months (redesign, improvements, new prototypes 0-5 months) Production test, characterization 1-3 months total time months design 0,2-1 M EUR NRE- 0,1-1 M EUR Design complexity grows Turo Piila Turo Piila 14 NRE Design data checking and formatting manufacturing Prototype wafer processing (10-25 pcs) Optionally also Production test development Prototype wafer testing Encapsulation Characterization ASIC circuit Rough estimates for calculating ASIC Silicon (wafer) 0.1 $ / mm2 Yield (die size dependent) 50-95% Wafer test 0.03 $ / s Packaging 0.02 $ / pin Final test 0.03 $ / s QA 1-5% General and profit % Turo Piila Turo Piila 16
5 ASIC trends Packaging density - Moore s law Wafer size inch Yield - defect density, process Semiconductor fab investment Fab variable Semiconductor market fluctuations design productivity Design risk ASIC risk management experienced designers proper EDA tools (Design software, CAE) test runs, MPW (MultiProject Wafer) Manufacturing risk suitable and stable vendor security stock second sourcing Turo Piila Turo Piila 18 Vendor selection Production security same size category with your company truly interested and motivated to serve sufficient design support level sufficient selection of technologies sufficient investment in development similar cultural background multiple sources with exactly the same process one vendor, several fabs no (or little) extra second source another vendor and process price competition possible almost double design and mask security storage protecting production agreement Turo Piila Turo Piila 20
6 Storage storage size, enough for 6-12 months big investment if big production financing 5-10% of stock value storage time vs. quality deterioration storage conditions (vacuum packs, nitrogen) level of completion untested wafers (cheapest phase) tested and packaged circuits risk of surplus when production ends Purchase agreement necessary, but doesn t add much security main points parties and products prices and price changes payment terms delivery terms delay penalties quality level, acceptance criteria, returns termination, last time buy Turo Piila Turo Piila 22 ASIC trends Semiconductor industry annual growth rates and market size SoC - System-on-Chip, very large circuits IP - Intellectual Property functions (up, MPEG4, ) Very deep submicron processes (<0,2 um) packing density up to gates / mm2 supply voltage goes down to 1V operating frequency in GHz range NRE increase dramatically wafer size increases, huge amount of circuits / lot Moore s law, packing density doubles in 18 months Cyclical nature of semiconductor business Turo Piila Turo Piila 24
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