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1 technology Leadership MARK BOHR INTEL SENIOR FELLOW, TECHNOLOGY AND MANUFACTURING GROUP DIRECTOR, PROCESS ARCHITECTURE AND INTEGRATION SEPTEMBER 19, 2017
2 Legal Disclaimer DISCLOSURES China Tech and Manufacturing Day 2017 occurs during Intel s Quiet Period, before Intel announces its 2017 third quarter financial and operating results. Therefore, presenters will not be addressing third quarter information during this year s program. Statements in this presentation that refer to forecasts, future plans and expectations are forward-looking statements that involve a number of risks and uncertainties. Words such as anticipates, expects, intends, goals, plans, believes, seeks, estimates, continues, may, will, would, should, could, and variations of such words and similar expressions are intended to identify such forward-looking statements. Statements that refer to or are based on projections, uncertain events or assumptions also identify forward-looking statements. Such statements are based on management s expectations as of September 19-20, 2017, and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in these forward-looking statements. Important factors that could cause actual results to differ materially from the company s expectations are set forth in Intel s earnings release dated July 27, 2017, which is included as an exhibit to Intel s Form 8-K furnished to the SEC on such date. Additional information regarding these and other factors that could affect Intel s results is included in Intel s SEC filings, including the company s most recent reports on Forms 10-K, 10-Q and 8-K reports may be obtained by visiting our Investor Relations website at or the SEC s website at
3 10 nm Hyper Scaling 22FFL technology Future Research
4 14 nm hyper Scaling features Fin Pitch Interconnect Pitch Cell Height Gate Pitch 60 nm 42 nm 80 nm 52 nm 840 nm 399 nm 90 nm 70 nm.70x.65x.48x.78x 22 nm 14 nm 22 nm 14 nm 22 nm 14 nm 22 nm 14 nm 14 nm uses aggressive feature scaling to deliver unprecedented 0.37x logic cell area scaling
5 14 nm products Wide range of 14 nm products in volume production on various derivative technologies
6 10 nm Hyper Scaling Fin Pitch Min Metal Pitch Cell Height Gate Pitch 42 nm 34 nm 52 nm 36 nm 399 nm 272 nm 70 nm 54 nm.81x.69x.68x.78x 14 nm 10 nm 14 nm 10 nm 14 nm 10 nm 14 nm 10 nm Double Quad Pattern Pattern 10 nm features aggressive pitch scaling - world s first self-aligned quad patterning
7 10 nm Hyper Scaling Fin Pitch Min Metal Pitch Cell Height Gate Pitch Dummy Gate Gate Contact 42 nm 34 nm 52 nm 36 nm 399 nm 272 nm 70 nm 54 nm Double Single Std COAG.81x.69x.68x.78x Contact Contact 14 nm 10 nm 14 nm 10 nm 14 nm 10 nm 14 nm 10 nm 14 nm 10 nm 14 nm 10 nm Double Quad Pattern Pattern Aggressive scaling & new features deliver 2.7x transistor density improvement
8 3 rd generation finfets 22 nm 14 nm 10 nm 53 nm 34 nm 10 nm fins are ~25% taller and ~25% more closely spaced than 14 nm
9 Gate Gate Contact Over Active gate Transistor Transistor Fins Contact Contact Contact over active gate is a revolutionary feature for another ~10% area scaling
10 Single dummy Gate Active Gate 14 nm 10 nm Dummy Gates Active Gate Single Dummy Gate Process innovations enable denser single dummy gate at cell borders
11 Cell Library Height Scaling 14 nm 399nm Height 10 nm 272nm Height (0.68x) Cell Height Cell Height Gate Pitch Gate Pitch Fin pitch and metal pitch scaling allow cell height to scale 0.68x from 14 nm
12 Logic Transistor density 1 45nm.49x Logic Area Metric 32nm.45x Gate Pitch Logic Area (relative) nm 14nm.37x.37x Logic Cell Height 10nm Logic Cell Width HVM Wafer Start Date Hyper scaling delivers better-than-normal logic area scaling
13 Logic Transistor density nm Intel 14nm 2.7x Transistor Density MTr / mm nm 22nm 2.1x 2.5x 60/40 NAND+SFF Density Metric 45nm 2.3x HVM Wafer Start Date Hyper scaling delivers better-than-normal transistor density improvement
14 Logic Transistor density 100 Intel 14nm 10nm Transistor Density MTr / mm nm 22nm MTr / mm 2 60/40 NAND+SFF Density Metric 45nm HVM Wafer Start Date 10 nm hyper scaling features result in transistor density above 100 MTr/mm 2
15 Intel 22FFL TSMC 20 nm Samsung 20 nm Intel 14 nm TSMC 16 nm Samsung 14 nm Intel 10 nm TSMC 10 nm Samsung 10 nm Logic Transistor density comparison Transistor Density (MTr/mm 2 ) 60/40 NAND+SFF Density Metric 10 20/22 nm 14/16 nm 10 nm Intel 10 nm is a full generation denser than other 10 nm
16 10 nm technology density Comparison Intel TSMC Samsung 10 nm 10 nm 10 nm Fin Pitch nm Gate Pitch nm Minimum Metal Pitch nm Logic Cell Height nm Logic Trans. Density MTr/mm 2 Logic Trans. Density 1x 0.48x 0.51x Relative Intel 10 nm is ahead of other 10 nm technologies on every density metric
17 SRAM AREA SCALING SRAM Cell Area (um 2 ) 0.1 HP.0441 LV.0367 HD.0312 um nm 32nm 22nm 14nm 10nm 7nm 10 nm offers a range of SRAM cells for density and power/performance SRAM cell area scaled ~0.6x from 14 nm
18 Transistor Performance (log scale) Dynamic Capacitance (log scale) Performance per Watt (log scale) Transistor performance and power Performance Power Performance per Watt 32nm 22nm 14nm Higher Performance 10nm Lower Power 10nm Better Perf/Watt 10nm 14nm 32nm 22nm 14nm 32nm 22nm Process Readiness Date Process Readiness Date Process Readiness Date 10 nm transistors provide improved performance per watt
19 Transistor Performance (log scale) Dynamic Capacitance (log scale) Performance per Watt (log scale) Transistor performance and power Performance Power Performance per Watt 32nm 22nm nm Higher Performance nm Lower Power 10nm Better Perf/Watt nm 14nm 32nm 22nm 14nm 32nm 22nm Process Readiness Date Process Readiness Date Process Readiness Date 10 nm enhancements improve performance and extend technology life
20 10nm performance and power Comparison Active Power Samsung ~30% TSMC ~20% Intel Lower Power Higher Performance Performance Intel 10 nm has a considerable performance lead over other 10 nm
21 Derivative technologies CPU SoC High Perf Transistors Yes Yes Low Leakage Transistors - Yes Analog/RF Transistors - Yes HV I/O Transistors - Yes High-Q Inductors - Yes Precision Resistors Yes Yes MIMCAP Yes Yes Device Options Low Cost Dense High Perf Interconnect Stack Options Multiple derivative options offered for each technology generation
22 10 nm Summary Intel s 10 nm process technology has the world s tightest transistor & metal pitches along with hyper scaling features for leadership density Intel s 10 nm technology is a full generation ahead of other 10 nm technologies Intel s 10 nm process technology is on track to commence manufacturing in 2H 17 Hyper scaling extracts the full value of multi-patterning schemes and allows Intel to continue the economic benefits of Moore s Law
23 10 nm Hyper Scaling 22FFL technology Future Research
24 Intel s new 22FFL technology 22FFL is the world s first FinFET technology for low power IOT and mobile products Advanced FinFET transistors based on proven 22 nm and 14 nm features >100x leakage power reduction with new ultra-low leakage transistor option Simplified interconnects and design rules based on 22 nm technology New levels of design automation Fully RF design enabled Cost competitive with other industry 28/22 nm planar technologies
25 22FFL dimensions 22 nm 22FFL 14 nm Transistor FinFET FinFET FinFET Fin Pitch nm Gate Pitch nm Metal Pitch nm Logic Cell Ht nm Trans. Density MTr / mm 2 SRAM Cell um 2 22FFL is based on proven 22 nm and 14 nm features
26 22FFL devices High performance transistors Ultra low leakage transistors Analog transistors High voltage I/O transistors High voltage power transistors Good device matching Low 1/F noise Deep N-well isolation Precision resistor MIM capacitor High resistance substrate High-Q inductors 22FFL offers a wide range of devices for digital and analog/rf design
27 FinFET Performance and leakage Advantage Transistor Gate Delay (normalized) % Faster 22 nm Tri-Gate 32 nm Planar 18% Faster Operating Voltage (V) Channel Current (normalized) Planar Reduced Leakage Tri-Gate 1E Gate Voltage (V) FinFETs provide a significant performance and leakage advantage over any planar transistor Intel 22 nm Tri-Gate announcement, April 2011
28 22FFl high performance transistors V 10 22GP >40% Higher Drive at Same Leakage 1 22FFL Total Leakage (na/um) 0.1 >18x Lower Leakage Lower Leakage Higher Performance Drive Current (ma/um) 22FFL provides high performance transistors with drive currents similar to 14nm++
29 22FFL Low leakage transistors V 10 22GP 1 22FFL Total Leakage (na/um) FFL Low Leakage >500x Lower Leakage >18x Lower Leakage Lower Leakage Higher Performance Drive Current (ma/um) 22FFL provides the lowest leakage transistors for any mainstream technology
30 Intel Custom Foundry s robust Ecosystem Design Service Design Tools & Flows Intel Custom Foundry Soft IP Foundation IP Advanced IP 22FFL is fully supported by a robust design ecosystem Other names and brands may be claimed as the property of others
31 22FFL technology 22FFL is an exciting new technology that provides a compelling combination of performance, power, density and ease-of-design for low power IOT and mobile products High transistor drive currents similar to Intel 14 nm Low leakage transistors with >500x lower total leakage than 22GP Die area scaling better than industry 28/22 nm technologies Wide range of advanced analog/rf devices Extensive use of single patterning for affordable ease-of-design Mature die yield with use of proven 22/14 nm features Cost competitive with other 28/22 nm planar technologies Industry standard PDK1.0 available now Production readiness in Q4 2017
32 10 nm Hyper Scaling 22FFL technology Future Research
33 Gate Innovation enabled technology pipeline 45 nm 32 nm 22 nm 14 nm 10 nm 7 nm 5 nm 3 nm Manufacturing Development Research Contact High-k Metal Gate FinFETs Contact over Gate SA Double Patterning SA Quad Patterning Intel has been the industry leader in bringing innovative technologies from research to high volume manufacturing
34 Gate Innovation enabled technology pipeline 45 nm 32 nm 22 nm 14 nm 10 nm 7 nm 5 nm 3 nm Manufacturing Development Research III-V Contact III-V Transistors 3D Stacking Material Synthesis High-k Metal Gate FinFETs Contact over Gate 2D Materials Nanowires EUV Patterning 10nm SA Double Patterning SA Quad Patterning Interconnects Beyond CMOS Dense Memory Future options subject to change We have a wide range of options in research to continue Moore s Law
35 Research projects Nanowire Transistors III-V Transistors 3D Stacking Dense Memory 10nm Dense Interconnects EUV Patterning Neuromorphic Computing Spintronics
36 Intel Oregon Campus Intel s main research & development site
37 Intel Oregon Campus Research Development Manufacturing Modeling Sort/Test Advanced Design Automation Reliability Technology leadership is the result of close collaboration at one site
38 Summary Hyper scaling on Intel 14 nm and 10 nm technologies provides better than normal scaling and delivers improved cost per transistor and performance per watt Intel s 10 nm technology is a full generation ahead of other 10 nm technologies 22FFL provides a compelling combination of performance, power, density and ease-of-design for low power IOT and mobile products Multiple technology options now in research will enable the continuation of Moore s Law for at least the next 10 years
Continuing Moore s law
Continuing Moore s law MARK BOHR INTEL SENIOR FELLOW, TECHNOLOGY AND MANUFACTURING GROUP DIRECTOR, PROCESS ARCHITECTURE AND INTEGRATION SEPTEMBER 19, 2017 Legal Disclaimer DISCLOSURES China Tech and Manufacturing
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