Typical applications where a CPLD may be the best design approach:

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1 By: Carlos Barberis, dba Bartek Technologies Description of Bartek s CPLD1 development board. For some of us CPLD s are familiar devices and for others just another acronym in the electronic device industry. CPLD devices are (Complex Programmable Logic Devices) that evolved from its early predecessor, the PAL (Programmable Array Logic) Although PAL s are now seldom used and are pretty much an obsoleted device, the CPLD has flourished and evolved so much that many CPLD s now rival much compatibility with FPGA devices. The difference between an FPGA and a CPLD device is mainly logic density; an FPGA is usually many times larger in gate density than the largest CPLD. On the other hand CPLD s are lower gate density devices, lower cost and typically a flash device that retains its configuration once programmed, most FPGA s are not flash memory devices and must load their programing configuration code from a local host device upon power-up. In recent years, there has been a blurry distinction separating both of these families as CPLD s are now coming very close to the density of FPGA s. Many CPLD s have recently introduced built in peripheral modules such as; UARTS, I2C, SPI and PWM functions and with some CPLD s you can actually create a processor core to emulate a full custom microcontroller something that previously could only be achieved with an FPGA Why use a CPLD? The first thing that comes to mind is probably speed. However, one great advantage that programmable logic has over a microcontroller is that unlike a microcontroller that operates, as a sequential logic machine that requires a program counter to execute the next instruction (indeterminate timing) the CPLD has no program counter or execution steps, all instructions or functions can be processed simultaneously (determinate timing). The fact that there is no sequential program counter makes the CPLD much less vulnerable to a missed instruction step or program lock-up more commonly associated with microprocessors or microcontrollers. Typical applications where a CPLD may be the best design approach: High-speed external glue logic circuitry. Safety monitor for critical controller applications. Invasive medical designs. I/O expansion.

2 Advantages using the CPLD1 Board: For most of us the quickest way to carry out a proof of concept design or do functional verification, before committing to initial PCB layout, is to utilize an off-the shelve microcontroller development board such as, the Microchip Explorer 16. In some applications, were we need to use a CPLD with our development board it is difficult to quickly interface due to the high number of pins and most of these devices are hard to interface at a breadboard level requiring you to do a PCB layout for the initial prototype. The CPLD1 breakout board is intended to quickly interface to the popular Explorer 16 or PIC32 development board from Microchip. The CPLD1 comes equipped with the Altera MAX pin TQFP device and offers breakout headers for all 76 programmable I/O pins, which can be easily interconnected, with the PicTail headers that connect the Explorer 16 or PIC32 development board I/O bus. Features and specifications for CPLD1: Altera MAX EPM7128AETC with 76 programmable logic I/O channels (100 pin device). On-board 50 MHz oscillator module usable gates, 128 Macrocells and eight Logic Array blocks. I/O pins are compatible with 5V, 3.3V or 2.5V logic via on-board selectable jumper. Simple jumper wire interconnects between the microcontroller and CPLD. Powered by Explorer 16 board or external DC input when using as a stand alone breadboard. JTAG interface connector for easy programming of CPLD or FPGA logic. USB Byte Blaster JTAG programmer and cables, and jumpers are included with the kit. Software design development with Altera s Quartus TM tools using the free downloadable web version or other HDL development tools supplied by 3 rd party vendors.

3 A simple project demonstration using the Explorer 16 and CPLD1 board As an example for a quick demonstration for the above boards, I have put together a very simple frequency divider application where the CPLD is controlled by the PIC24F on the Explorer 16 board to give you eight different frequencies derived from the 50.0 MHz clock on the CPLD board. The LCD display on the Explorer board will display the selected frequency in MHz and switches S3 will toggle the frequency output of the divider ON or OFF and switch S6 will just step through the eight discrete frequencies. Upon power up the LCD screen will display the following: CPLD Freq Source F= MHz Switch S6 will step through the following frequencies: MHz MHz MHz MHz MHz MHz MHz MHz Upon reaching the last frequency a subsequent press of S6 will return to the first frequency (2.50 MHz) When the program initializes the output of the frequency divider will be active, this can be toggled on or off via S3 The control connectivity between the Explorer 16 and the CPLD1 board is as follows: PICTAIL Access connector on CPLD1 CPLD1 Breakout Connector RA0 I/O 1 RA1 I/O 3 RA2 I/O 5 RA3 I/O 7 RA4 I/O 9 RA5 I/O 11 RA7 I/O 19 Frequency Output on CPLD1 board: I/O 42 Logic circuit description: The programmable frequency divider is composed of four logic blocks. The two divider blocks could have been chosen directly from the Altera Quartus

4 libraries which feature all type of counter function macros or equivalent 7400 TTL device function modules. However, for the sake of simplicity we have chosen to use two modules written in the Verilog HDL language to accomplish the same end function. The two other circuit elements are a D-type Flop for frequency synchronization and division and a simple AND gate, both of these elements are found in the Logic Primitives libraries for Quartus. For this circuit all we want is to take the MHz local oscillator on the CPLD1 board, divide it down to MHz and then be able to generate seven additional frequencies which will be output via I/O 42 on the CPLD1 breakout connector. The control of these frequencies and output control will be done by the Explorer 16 development board. Quartus Block Diagram Board Setup

5 Wiring Setup In order to assemble and compile both the PIC24 firmware and CPLD code we will need to use the CPLD1 project found on the CPLD1_ExplorerFirmware folder as well as the Altera Quartus files located in the Demo folder. Make sure to download the free version of Quartus II software from: You should also download all other pertinent information such as; Operating Hand Book, Installation Guide and tutorials from the same site. It is very important that you read through the Quartus II handbook to understand the basics of the IDE there is also many video tutorials available from Altera in the same web site, included here you will find a pdf file Intro_to_quartus2.pdf which will show you step by step how to build and run a project. In order to program the CPLD make sure to connect the ByteBlaster programmer to the CPLD JTAG connector (J11) and the other side of the ByteBlaster to your USB connector on your computer

6 Steps to compile and program CPLD using Altera Quartus II (V11.1) 1. Install and Run the Quartus II software. 2. In Quartus open project file: C:\CPLD1-Presentation\Demo\SimpleDivider.qpf 3. Compile project as shown below on Quartus II screen. Once the compilation is finished, you will see the following screen:

7 Step 4: Once the compilation has successfully completed, run the Byte-Blaster JTAG programmer from the TOOLS menu, select PROGRAMMER Under the Programmer window, select File, Open, then select the SimpleDivider.pof file. Make sure to highlight and place the check marks as shown below, then click on the first upper left-hand button marked Start This will begin the process of uploading the code to the CPLD device via the JTAG interface. Once the code is finish uploading, you will see the green progress bar (shown below) indicate 100% success Once the step above is completed, you may disconnect the JTAG programmer from the CPLD board if desired, or just simply leave it in place as once the programming cycle has taken place the JTAG programmer does not interfere with the CPLD functionality. Building and compiling CPLD1 firmware for Explorer 16 board (Requires ICD3 or any other debugger/programmer that must be configured under MPLAB) 1. Make sure you have a PIC24FJ256GB110 pim in the Explorer board; (other PIC devices may be used but will require modifications of the program). 2. Using MPLAB open the following project file: C:\CPLD1-Presentation\CPLD1_ExplorerFirmware\CPLD1.mcp 3. Compile load and run program on Explorer 16 board. You should now be ready to run the CPLD1 demo program from the explorer board.