Hybrid Memory Cube (HMC)

Transcription

1 23 Hybrid Memory Cube (HMC) J. Thomas Pawlowski, Fellow Chief Technologist, Architecture Development Group, Micron 2011 Micron Technology, I nc. All rights reserved. Products are warranted only to meet Micron s production data sheet specifications. I nformation, products, and/ or specifications are subject to change without notice. All information is provided on an AS IS basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. August 4, Micron Technology, Inc. 1

2 Outline Problems Goals HMC introduction New relationship between CPU and memory I nternal architecture Performance Summary August 4, Micron Technology, Inc. 2

3 Observed Problems: The Problems Latency (classic memory wall ) Bandwidth related issues Power / energy Many-core, Multi-threaded CPUs generate higher random request rates Memory capacity per unit footprint Future Problems: Scalability of bandwidth, densities, request rates and lower latencies Essential Underlying Issue: Direct control of memory must give way to memory abstraction Mitigate negative characteristics of next generation DRAM processes I ntroduction of future DRAM replacement technologies August 4, Micron Technology, Inc. 3

4 Historic Energy x Bandwidth I mprovement Per DRAM Generation Average = 4.5x per generation DDR DDR II DDR3 DDR Micron Technology, Inc. 4

5 Hybrid Memory Cube Goals 1. Higher bandwidth 2. Higher signaling rate 3. Lower energy per useful unit of work done 4. Lower system latency 5. I ncreased request rate, for many-core: 6. Higher memory packing density CONCURRENCY! 7. Abstracted interface 1. lighten CPU/ DRAM interaction 2. enable new DRAM management concepts 3. manage future process scaling and future technology introductions 8. Scalability for higher future bandwidths and density footprint 9. Reduce customer and Micron time to market August 4, Micron Technology, Inc. 5

6 Hybrid Memory Cube (HMC) Through-Silicon Vias (TSV) Abstraction Protocol DRAM DRAM DRAM DRAM Many Buses > 1Tb/ s Processor Logic Die High-Speed Links Notes: Tb/ s = Terabits / second HMC height is exaggerated 2011 Micron Technology, Inc. 6

7 HMC Near Memory MCM Configuration All links are between host CPU and HMC logic layer Maximum bandwidth per GB capacity TSVs Wide Data Path High-Speed Link DRAM CPU Logic Chip Notes: MCM = multi-chip module I llustrative purposes only; height is exaggerated 2011 Micron Technology, Inc. 7

8 Far memory HMC Far Memory Some HMC links connect to host, some to other cubes Serial links form networks of cubes the memory = the network Scalable to meet system requirements Can be in module form or soldereddown Can form a variety of topologies e.g., tree, ring, double-ring, mesh Future interfaces Higher speed electrical (SERDES) Optical Whatever the most appropriate interface for the job August 4, Micron Technology, Inc. 8

9 Processor Memory I nteraction Yesterday: multi-core CPU direct connection to DRAM-specific buses Complex scheduler, deep queues, high reordering especially writes Many DRAM timing parameters standardized across vendors Worst case everything Result is conservative, evolutionary, uncreative, slow performance growth Now: direct connect to HMC logic chip via abstracted high-speed interface No need for complex scheduler, just thin arbiter, shallow queues Only the high-speed interface, protocol, form-factor might be standardized NO TI MI NG constraints, overrun is prevented Great innovations can occur under the hood Maximize performance growth Logic layer flexibility allows HMC cubes to be designed for multiple platforms and applications without changing the high-volume DRAM HMC takes requests, delivers results in most advantageous order August 4, Micron Technology, Inc. 9

10 HMC Architecture Start with a clean slate DRAM August Micron Technology, Inc. 10

11 HMC Architecture Re-partition the DRAM and strip away the common logic DRAM August Micron Technology, Inc. 11

12 HMC Architecture Stack multiple DRAMs DRAM August Micron Technology, Inc. 12

13 HMC Architecture Re-insert common logic on to the Logic Base die 3DI & TSV Technology DRAM7 DRAM6 DRAM5 DRAM4 DRAM3 DRAM2 DRAM1 DRAM0 Logic Chip DRAM Vertical Slice Vertical Slices are managed to maximize overall device availability Optimized management of energy and refresh Self test, error detection, correction, and repair in the logic base layer Logic Base August Micron Technology, Inc. 13

14 Logic Base Slice Control Slice Control Slice Control Slice Control Memory Control Crossbar Switch HMC Architecture Add sophisticated switching and optimized memory control And now we have a whole new set of capabilities Link Interface Controller Link Interface Controller Processor Links Link Interface Controller Logic Base Wide, high-speed local bus for data movement Advanced memory controller functions DRAM control at memory rather than distant host controller Reduced memory controller complexity and increased efficiency Link Interface Controller Vertical Slice 3DI & TSV Technology Vertical Slices are managed to maximize overall device availability DRAM7 DRAM6 DRAM5 DRAM4 DRAM3 DRAM2 DRAM1 DRAM0 Logic Chip Optimized management of energy and refresh DRAM Self test, error detection, correction, and repair in the logic base layer Logic Base August Micron Technology, Inc. 14

15 Vastly More Responders Conventional DRAM DI MM example: 8 devices, 8 banks/ device Banks of all devices run in lock-step One of 8 potential responders will answer a typical request Not only does HMC give excellent concurrency HMC gen 1 example: 4 DRAMs * 16 slices * 2 banks = 128 One of 128 potential responders will answer a typical request Double that to 256 if 8 DRAMs are in the stack Vast improvement in response to random request stream Significant impact on system latency DRAM trc is lower by design Lower queue delays and higher bank availability further shortens latency Serial links slightly increase latency Net effect is a substantial system latency reduction August 4, Micron Technology, Inc. 15

16 Available Total Bandwidth Link Transmit Lanes ( differential) 16 Receive Lanes ( differential) 10 Gbps/ Lane 32 Lanes = 4 bytes 40 GBps per Link 4 Links per Cube 160 GBps per Cube 8 Links per Cube 320 GBps per Cube August 4, Micron Technology, Inc. 16

17 RAS Features Reliability, Availability, and Serviceability (RAS) features are built into HMC Systemic RAS features Array repair DRAM/ Logic I O interface repair I nternal ECC is utilized for detection and short term correction Upon detection, repair is scheduled so that ECC is not a perpetual crutch for an identified issue and is free to cover future errors Link I O has means to detect communication errors Worst case hard failure shuts down only one of many links 2011 Micron Technology, Inc. 17

18 I nternal DRAM Efficiency 4-8 High Stacks 100 % Memory Bandwidth Utilization (of 160GB/s) % 53% 55% 57% 67% 75% 100% 1:1 2:1 3:1 % Reads of Overall Traffic 4 High % Memory Bandwidth Utilization (of 160GB/s) 128 Byte 64 Byte 32 Byte High 128 Byte 64 Byte 32 Byte 0 50% 53% 55% 57% 67% 75% 100% 1:1 2:1 3:1 % Reads of Overall Traffic 2011 Micron Technology, Inc. 18

19 Effective Read/ Write External Link Efficiency 2011 Micron Technology, Inc. 19

20 Other Unique System Capabilities Request rate capability 3.2G operations per second (32 byte data transactions) Limited by external data links 2.3Gops at 128GB/ s, 2.9Gops at 160GB/ s Random request capability Historically this gets worse as bandwidth is increased DDR3 SDRAM is ~ 29% at BL8, DDR4 is worse, GDDR5 is worse yet HMC achieves 75% of peak bandwidth (64B data transactions) Network of HMCs E.g., double-ring or mesh of interconnected HMCs Average latency grows but is a constant regardless of the individual HMC s depth in the mesh 2011 Micron Technology, Inc. 20

21 HMC Gen1 : Technology Comparison Generation 1 ( memory configuration) Technology VDD I DD BW GB/ s Power ( W) mw/ GB/ s pj/ bit real pj/ bit SDRAM PC133 1GB Module DDR-333 1GB Module DDRII-667 2GB Module DDR GB Module DDR GB Module HMC, 4 DRAM w/ Logic Gb 50nm DRAM Array 90nm prototype logic 512MB total DRAM cube 128GB/ s Bandwidth 27mm x 27mm prototype Functional demonstrations! Reduced host CPU energy Simple calculation from I DD7 (SDRAM I DD4) HMC Gen 1 DRAM Real system, some with lower density modules August Micron Technology, Inc. 21

22 HMC Demonstration Platform August 4, Micron Technology, Inc. 22

23 Summary Revolutionary DRAM performance improvement demonstrated by Changing to abstracted high-speed buses Employing 3D packaging using a hybrid of DRAM and logic technologies Pulling in and improving the DRAM controller Marrying DRAM and logic together using many TSVs Completely rethinking DRAM architecture to exploit 3D Managing component health for robust system solutions Result is > 10x bandwidth, < 1/ 3 energy, lower latency Request rates far beyond 2 billion operations per second Logic layer flexibility allows HMC to be tailor-made for multiple platforms and applications Scalable to ANY performance level. I magine the possibilities. August 4, Micron Technology, Inc. 23

24 Energy x Bandwidth I mprovement Per DRAM Generation HMC DDR DDR II DDR3 DDR4 HMC Processor High Speed Links Logic Layer 2011 Micron Technology, Inc. 24