Real Digital Problem Set #6

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Myrtle Nichols
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1 Real igital Problem et #6. (2 points) ketch a block diagram for a magnitude comparator bit-slice circuit. Create K-maps to define the bit-slice circuit, and use them to find optimal logic equations. ketch the bit-slice circuit.

2 Real igital Problem et 6 2. (2 points) Modify the bit-slice block of problem by removing the logic gates and signals that form the EQ output. ketch a "block" circuit diagram for a 4-bit comparator that uses the modified bit slice blocks, and add a single gate to form the EQ output from the LT and GT outputs from the M (most significant bit). (4 points) Could you make the bit-slice modules even more efficient by leaving in the EQ logic and removing some other logic? Explain. 3. ( points) Complete truth tables and K-maps for H and F circuits, using XOR patterns where appropriate. Loop minimum OP equations, and sketch the circuits (assume all inputs and outputs are active high). Half dder Cout = Cout = Cout

3 Real igital Problem et 6 Full dder Cin Cout Cin = Cin Cout = Cout 4. ( points) ketch a block diagram for a full adder using two half-adder blocks and an OR gate. 5. (8 points) ketch an entire Carry-Propagate-Generate circuit that can form the carry-ins for all four bits of 5-bit CL.

4 Real igital Problem et 6 6. (2 points) esign a full-subtractor bit-slice circuit (orrow-ripple ubtractor). Label the inputs,, and in, and label the outputs and out. tart by completing the subtraction examples, then complete the truth table and K-maps, and then sketch the circuit in out in = in out = out

5 Real igital Problem et 6 7. (8 points) Complete the number conversions indicated. Note that all binary numbers are two s complement representations. -9 = = = - = 8. (22 points) Complete the four 2 s compliment arithmetic problems below assuming that all operations use an adder. howing both the decimal and binary numbers in each case (-7) + + Is the answer to the equation on the left correct in 8 bits? Explain. 9. ( points) ketch a circuit to convert a 4-bit binary number to its 2 s complement representation using only 3 XOR/XNOR gates and 2 N or OR gates.

6 Real igital Problem et 6. (8 points) Examine several examples of addition overflow and subtraction underflow, and sketch a circuit below that can output a whenever an addition or subtraction result is incorrect due to underflow or overflow. ssume that both operands and result of the addition and subtraction are N-bits. (Hint: compare the carry in and carry out signals of the most-significant bit).. (6 points) Fill in the squares below to show all signal values when and are multiplied. 2 3 P 3 P 22 P 3 P 2 P 2 P 2 P P 2 P P P P P P P P 2 P 2 P 3 P 3 P 23 P 32 P 3 P 3 P 2 P 2 P 22 P P 3 P 3 P 23 P 33 P R 7 R 6 R 5 R 4 R 3 R 2 R R

7 Real igital Problem et 6 2. (8 points) ketch a block diagram for a 4-bit LU built from bit-slice LU circuits that can implement the functions shown in the table. (Note: I m not looking for the circuits inside the bit-slice module, but rather a circuit that uses the bit-slices as blocks). Label all signals. Recall that inputs to the bit slices must come from the and input busses as well as from neighboring bit slices, and outputs from the slices must drive the F output bus as well as neighboring bit slices. To design the signals that communicate information between slices, you must understand the LU operations and the implications for information transfer (e.g., does the operation PLU require that information be transferred between slices? If so, what? oes the operation OR require that information be transferred?). Operation Code LU function PLU PLU MINU MINU XOR OR N (8 points) The LU operation table from the module has been reproduced below, but opcode 3 has been redefined as decrement. Complete the F and Cout table entries to define the decrement logic functions. Op Code Function F Cout + xor xor Cin ( and ) or (Cin and ( xor )) Inc xor Cin and Cin - xor xor Cin ( and ) or (Cin and ( xor ) ) ec XOR xor OR or N and

8 Real igital Problem et 6 3. (2 points) Complete the timing diagram below to illustrate the behavior of the counter. RT Cen CLK Cen 3 2 Cen CLK RT (2 points) Complete the circuit sketch for a four-bit counter by adding the required next-state logic gates in front of the flip-flops. Q Q Q 2 Q 3

Revision: August 31, E Main Suite D Pullman, WA (509) Voice and Fax

Revision: August 31, E Main Suite D Pullman, WA (509) Voice and Fax Exercise 7: Combinational rithmetic Circuits Revision: ugust 3, 29 25 E Main uite D Pullman, W 9963 (59) 334 636 Voice and Fax TUDENT I am submitting my own work, and I understand penalties will be assessed