Chapter 14. Motorola MC68HC11 Family MCU Architecture

Size: px

Start display at page:

Download "Chapter 14. Motorola MC68HC11 Family MCU Architecture"

Janel French
6 years ago
Views:

1 Chapter 14 Motorola MC68HC11 Family MCU Architecture

2 Lesson 1 68HC11 MCU Architecture overview 2

3 Outline CPU Registers, MCU Architecture overview Address and Data Buses Execution Unit- ALU Ports 3

4 CPU Registers ACCA and ACCB 16-bit Program Counter PC 16-bit Stack Pointer S 16-bit Index Registers IX and IY 8- bit CCR (Condition Code Register) 4

5 Microcontroller 68HC11 Internal RAM and ROM, RAM, Registers, EEPROM 8- bit Internal Bus 8 MHz XTAL Accumulators Stop Instruction ACCA and ACCB CC R Fully MOS- FET Based Clock Reducible to 0 16-bit Program Counter PC 16-bit Stack Pointer S 16-bit Index Registers IX and IY Decrease after push, increase before pop 5

6 Outline CPU Registers, MCU Architecture overview Address and Data Buses Execution Unit- ALU Ports 6

7 Fully static operation- MCU clock can be reduced to 0 being fully MOSFETs based Stop Instruction 7

8 Performance As per 8MHz XTL 2MHz E-Clock 8

9 68HC11 common 8-bit internal bus for the 16-bit addressing and 8-bit data Princeton architecture bus Bus interface for 8-bit data and instructions. Two interrupts Maskable Interrupt request (IRQ) and Initialization option as unmaskable (XIRQ) PC initialization using reset vector FFFEH-FFEFH Reset 9

10 68HC11 Architecture Overview 10

11 Port E AMUX S/H ADC IR ID Reset Osc Interrupt Control Outcompare In Capture TCNT COP Executio n unit Control and Sequencing Circuit AD0-AD8 PACN Port C T RTC SPI SC I DDRC DDRD CPU registers IO and internal devices Registers Internal RAM and ROM, RAM,EEPROM OPTION, COPRS, PPROG, HIPRO, INIT,CONFIG, TESTI A8-A15 Port B Port D Port A 11 ACCA, ACCB, IX,IY, PC, S, CCR

12 64 kb of linear address space Address 68HC11/12 IO and internal devices, System control Registers Internal RAM and ROM, RAM,EEPROM Memory Architecture Internal devices Registers Data and Program, constants, stored tables Common Memory 12

13 68HC11 Family Programming Address Space Model CPU Registers IO and internal devices Registers System Function Control Registers Internal RAM and ROM, RAM,EEPROM OPTION, COPRS, IPRO, INIT, CONFIG, TESTI 13

14 Instructions have 8 data type Few use 16- bit data types Processor operation of 16-bit data type is as per word alignment at memory in big endian [least significant byte stored as higher bits (address 1) of a word] 14

15 16-bit word alignment A 16bit word in memory Big Endian Byte1 (MSB) Byte0 (LSB) Address0 Address1 Address 15

16 Outline CPU Registers, MCU Architecture overview Address and Data Buses Execution Unit- ALU Ports 16

17 Internal and External Buses ACCA or ACCB IY IX CCR Internal Devices S PC MDR MAR AD0 AD7 A8 - A15 Bus Interface Unit Internal Bus 8-bit 17

18 Outline CPU Registers, MCU Architecture overview Address and Data Buses Execution Unit- ALU Ports 18

19 ACCA or ACCB used as 8-bit ACC or as16-bit ACCD (double accumulator) 8-bit ALU includes multiplier and divide 19

20 Execution Unit IR ID Control and Sequencer Circuits ACCA or ACCB IX IY Internal RAM and ROM, RAM, Registers, EEPROM Temp 1 Temp 2 +, -, x or Rotate/ Shift ALU CCR CMP, TST OR, AND, XOR 20

21 STAGE 1 Instruction Execution Instruction Fetch clock cycle (s) STAGE 2 Instruction Decode STAGE 3 to n Instruction Execute Time 21

22 Internal bus Fetch Decode Execution IR ID Control and Sequencer Circuits Control memory micro codes based - Implementation 22

23 Outline CPU Registers, MCU Architecture overview Address and Data Buses Execution Unit- ALU Ports 23

24 Address x 000H PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 IO O O O O I I I Option 1 Port PA OC1 OC2 OC3 OC4 OC5 IC1 IC2 IC3 Option 2 Outcompare TCNT In Capture PACN T Cnt O O O O I I I Option 3 24

25 Address x 004H Port PB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 O O O O O O O O Option 1 A15 A14 A13 A12 A11 A10 A9 A8 Option 2 25

26 Address x 007H Address x 005H STRA STRB Handshake signals for Port DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 IO IO IO IO IO IO IO IO Option 1 A7 A6 A5 A4 A3 A2 A1 A0 Option 2 D7 D6 D5 D4 D3 D2 D1 D0 Option 3 Port PC 26

27 Address x 009H DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 Address x 008H PD5 PD4 PD3 PD2 PD1 PD0 Port PD IO IO IO IO IO IO Option 1 SS SCLK MOSI MISO TxD RxD Option 2 Master SPI SS SCLK MISO MOSI SCI Option 3 Option 4 Slave SPI Receiving SCI RxD TxD 27 O p t i o n 5

28 Address x 00AH Port PE AMUX S/H ADC PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 I I I I I I I I AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 ADC Register sadc TL Register Option 1 Analog Input Option 2 28

29 Expanded Mode used for interfacing External Memory and Ports Expanded Mode looses Port B and Port B Recovered back by using 68HC24

30 E AS A15 A14 A13 A12 A11 A10 A9 A8 Port B Option 2 Mode A=0 Mode B=1 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Port C Options 2/3 Expansion Mode Latch An-A15 A15 Address Decoder Expansion to Ports and Memory A0-A15 CS CS D0-D7 30

31 E Reset R/W An- A15 PC0- PC7 D0- D7 Mode A=0 Mode B=1 Lost Ports Replacement Unit 68HC24 STRA STRB Port B Port C Handshake signals for Port Recovered Ports B and Port C 31

32 Summary

33 68HC11 family 8-bit processor PC, S, ACCA, ACCB, IX, IY, CCR Princeton architecture 8 bit data type Big endian 16-bit word alignment Two interrupts Maskable Interrupt request (IRQ) and Initialization option as unmaskable (XIRQ) PC initialization using reset vector

34 Internal and External Memory Addresses- IO/Devices Control and Status Registers System Function Control Registers Internal RAM Internal ROM EEPROM

35 Internal Devices TCNT with out compare, input capture, SPI, SCI RTC PACNT Port E with option of analog inputs multi channel AMUX, S/H, ADC Port B /A8-A15, Port C with DDRC / AD0-AD7/ Port A /IC1-IC3, OC1-OC5 Port D with DDRD/SCI/SPI Master/Slave

36 End of Lesson 1 on MCU Architecture overview

37 THANK YOU 37

Microcomputer Architecture and Programming

IUST-EE (Chapter 1) Microcomputer Architecture and Programming 1 Outline Basic Blocks of Microcomputer Typical Microcomputer Architecture The Single-Chip Microprocessor Microprocessor vs. Microcontroller