Siemens' C161 - Enter the 16-bit family of Microcontrollers with revolutionary price/performance ratio

Size: px

Start display at page:

Download "Siemens' C161 - Enter the 16-bit family of Microcontrollers with revolutionary price/performance ratio"

Alexina Peters
6 years ago
Views:

1 Siemens' C1 - Enter the -bit family of Microcontrollers with revolutionary price/performance ratio C1V, C1K and C1O - these new entry level members of the Siemens C6 family allow to enter the -bit class of microcontrollers, offering all the performance benefits - but at a price level that is normally associated with an 8-bit microcontroller. The three new microcontrollers provide similar performance to other derivatives of the C6 family and peripheral configurations tuned for cost sensitive applications. C6- A Growing Family Six years ago Siemens designed the founder member of their -bit microcontroller family, the SAB 80C6. The design target was to combine the high computational power of microprocessors with the optimised event handling capability of microcontrollers in a single architecture. The C6 family range has since been extended several times. With their extensive peripheral set the C7 versions are ideal for high-end automotive and industrial applications. The C5 and C3 processor oriented derivatives are generally found in the telecom- and dataprocessing segments. The C1 is the latest branch of the family currently consisting of the C1V, C1K and C1O devices. These devices are described in the following sections. For a device overview a block diagram (Figure 1) is provided illustrating the different on-chip components and the advanced, high bandwidth internal bus structure of the C1. The Key Features Table (Table 1) shows the key features of the three versions for quick reference. The C1's heart is in the right place...

2 The C1 devices are based around the same powerful central processing unit as their elder brothers (figure 2). The CPU core consists of a 4-stage instruction pipeline, a -bit arithmetic and logic unit (ALU) and dedicated Special Function registers (SFRs). Additional hardware is provided for a separate multiply/divide unit, a bit-mask generator and a barrel shifter. Given the above, most of the C1's instructions can be executed in just one machine cycle (125 ns at MHz CPU clock). Shift and rotate instructions, for example, are processed in one machine cycle irrespective of the number of shifts to be performed. The few multi-cycle instructions have also been optimised for fast execution. Branches execute in 1 or 2 cycles (1 if the branch is not taken and 2 if it is), a * bit multiplication in 5 cycles and a 32-/ bit division in 10 cycles. An additional pipeline optimisation (the "Jump Cache") reduces, even further (from 2 cycles to 1 cycle), the execution time of branches repeatedly performed in a loop. The CPU operates on a register bank consisting of word-wide General Purpose Registers (GPRs) which are physically located within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank (i.e. the bank being accessed by the CPU). The number of register banks is restricted only by the available internal RAM space. Fast and easy parameter passing can be achieved by allowing register banks to overlap. A system stack is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access to detect stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can be efficiently utilised by a programmer via the highly efficient C1 instruction set. The instruction set consists of either 2 or 4 byte instructions. Possible operand types are

3 bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands. No need to fear multiple Interrupts With an interrupt response time of just 375 ns (for the case of internal data and fastest external bus mode) the C1 is capable of rapid response to the occurrence of non-deterministic events. The C6 architecture supports several mechanisms for fast and flexible handling of service requests generated from various internal or external sources. Any of these interrupt requests can be programmed for service by the CPU (under the control of the Interrupt Controller) or by the Peripheral Event Controller (PEC). A PEC interrupt service contrasts with a standard interrupt service (see below) in that just one cycle is "stolen" from the current CPU activity. A PEC service allows a single byte or word data transfer between any two memory locations with an optional additional increment of either the PEC source or destination pointer. PEC services are ideal for the automatic transmission or reception of blocks of data and many other applications. The C1 provides 8 PEC channels providing excellent interruptdriven data transfer capabilities. Where an interrupt is processed by the CPU the current program execution is suspended and a branch to specific interrupt code is performed. The provision of a dedicated vector location for each of the possible interrupt sources allows interrupt handler code to be located wherever is desired. A separate interrupt control register is provided for each of the possible interrupt sources. This register contains an interrupt request flag, an interrupt enable flag and an interrupt priority bit-field. The priority bit-field allows each source to be programmed to one of sixteen interrupt priority levels. The processing of an Interrupt by the CPU can only be interrupted by a higher prioritised interrupt service request.

4 Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the "TRAP" instruction in combination with an individual trap (interrupt) number. The C1 provides an excellent mechanism ("Hardware Traps") for ensuring system integrity by identifying and processing exceptions or error conditions that might arise during run-time. An attempt by the CPU to execute an illegal operation (e.g. stack over/underflow, bad memory access) will cause a "Hardware Trap". This generates an immediate nonmaskable interrupt which is processed in a similar manner as for a standard interrupt service (branching via a dedicated vector table location). It s all in the Timing... For time related tasks (e.g. event timing and counting, pulse width and duty cycle measurements, pulse generation, pulse multiplication) the C1 contains a highly flexible multi-functional timer/counter structure. Two separate General Purpose Timer (GPT) units (GPT1 and GPT2) are available (GPT2 on C1O only). Each module contains a number of timers which may operate independently or be configured to operate in conjunction with another timer(or timers) of the same module. Each of the three GPT1 timers (T2, T3, T4 - see figure 3) can be configured individually for one of three basic modes of operation, Timer, Gated Timer, and Counter Modes. Timer Mode allows the timer to be clocked with a clock derived from the CPU clock (divided by a programmable prescaler). Counter Mode allows the timer to be clocked by external signal edges. Pulse width or duty cycle measurement can be performed using Gated Timer Mode where the operation of a timer (run or hold) is controlled by the "gate" level on an external input pin. To support these modes each timer has one associated port pin (TxIN) which serves as a gate or clock input. The count direction (up/down) for each timer is programmable by software or may additionally be dynamically controlled by an external signal applied

5 to a port pin (TxEUD) to facilitate, for example, position tracking. The maximum resolution of the timers in module GPT1 is 500 ns (@ -MHz CPU clock). Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on the T3OUT port pin (e.g. for time out monitoring of external hardware components) and/or may be used internally to clock timers T2 and T4 (e.g. to produce a 32 bit timer for measuring long time periods with high resolution). In addition to their basic operating modes, timers T2 and/or T4 may be configured as reload or capture registers for timer T3. When used as a capture register timers T2 or T4 are stopped, the value of timer T3 is captured into T2 or T4 in response to a signal edge at the associated input pin (TxIN). When used as a reload register timers T2 or T4 are stopped, timer T3 is reloaded with the value of T2 or T4 triggered either by an external signal edge (at the associated input pin TxIN) or by a selectable state transition of its toggle latch T3OTL. A PWM signal can be generated (without CPU intervention) when both T2 and T4 are configured as reload registers, reloading T3 on opposite state transitions of T3OTL (T2 and T4 contain the low and high times of the desired PWM). Please note that the C1V has no external connection for GPT1 (i.e. the related functions are not available). The GPT2 module available on the C1O (see figure 4), with a maximum resolution of 250 ns (@ MHz, provides even more precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock derived from the CPU clock via a programmable prescaler. The count direction (up/down) for each timer is programmable by software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of T6OTL can be used to clock timer T5. The overflows/underflows of timer T6 can cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be

6 cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. Connect the C1 to your application The C1 provides up to 63 I/O lines which are organised into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bi-directional ports which are switched to high impedance state when configured as inputs. The output drivers of three I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During reset all port pins are configured as inputs. Many port lines may be programmed for an associated alternate input or output function. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A21/19/17...A in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 6 provides optional chip select signals. Port 3 includes alternate functions of timers, serial interfaces and the optional bus control signal BHE. Port 5 is used for timer control signals. All port lines that are not used for these alternate functions may be used as general purpose I/O lines. Keeping a watchful eye on your system... The Watchdog Timer represents one of many fail-safe mechanisms which have been implemented to ensure system integrity over long periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled during processor configuration, i.e. before execution of the EINIT (end of initialisation) instruction. This ensures that the chip's start-up procedure is always monitored. System software must be designed to service the Watchdog Timer at a sufficient rate to prevent timer overflow. If the software fails to do so (e.g. due to hardware or software failure), the Watchdog Timer will overflow and generate an internal

7 hardware reset. This reset will also pull the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer consists of a -bit timer, clocked with the system clock divided either by a programmable pre-scalar of 2 or 128. Each time the watchdog is serviced by the CPU the high byte of the Watchdog Timer register is reloaded with the value from the programmable reload register (WDTREL) and the low byte is cleared. This scheme (in conjunction with the programmable pre-scalar) allows flexible selection of time-out intervals between 32 µs and 524 ms (@ MHz CPU Clock). The default Watchdog Timer interval after reset is 8.19 ms (@ MHz). Let your components talk to each other! Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by an Asynchronous/Synchronous Serial Channel (ASC0) and an independent High-Speed Synchronous Serial Channel (SSC). ASC0 is upward compatible with the serial ports of the Siemens 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 500 KBaud and half-duplex synchronous communication at up to 2 MHz CPU clock. A dedicated baud rate generator allows selection of all standard baud rates without oscillator tuning. For transmission, reception and error handling 4 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake up bit mode). A number of optional hardware error detection capabilities have been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows recognition of data frames with missing stop bits. An overrun error will be generated

8 if reception of a new character is complete before the last character received has been read out of the receive buffer register. In synchronous mode ASC0 transmits or receives bytes (8 bits) synchronously with a shift clock which is generated by ASC0. ASC0 always shifts the LSB first. A loop back option is available for testing purposes. The SSC supports full-duplex synchronous communication at up to 4 MHz CPU clock. It may be configured to interface with serially linked peripheral components. A dedicated baud rate generator allows selection of all standard baud rates without oscillator tuning. For transmission, reception and error handling 3 separate interrupt vectors are provided. The SSC transmits or receives characters of 2... bits in length synchronously to a shift clock. The shift clock can be generated by the SSC (master mode) or by an external master (slave mode). For maximum flexibility the bit order of the data (LSBit first or MSBit first), selection of shifting and latching clock edges, and clock polarity are programmable. A number of optional hardware error detection capabilities have been included to increase the reliability of data transfers. Transmit and receive errors are generated if the data buffer is not correctly handled. Phase and baudrate errors are also detected. Sophisticated Development Tools Due to close co-operation between Siemens and a number of well-known third-party tool suppliers, a large range of efficient development tools are available for and designed around the needs of the C6 family architecture. Development engineers can therefore choose from low cost starter kits, high optimisation compilers, assemblers, HLL debuggers or powerful in-circuit emulators, real-time operating systems and logic analysers.

9 Further application support from Siemens is ensured by availability of competent engineers and reliable and detailed documentation. In addition training can be arranged by the MicroConsult GmbH (which has derived from the Siemens School for Microelectronics in Munich). Author: Axel Wolf Dipl.-Ing. (BA), Siemens AG, Abteilung HL MCB AT Tel. 089/

10 Figures: Internal ROM Area Instr./Data 32 C6-Core CPU Core CPU Data Data Dual Port Internal RAM 1KByte (C1O: 2 KByte) 4 6 OSC (input: MHz; prescaler or direct drive) X- Peripheral Area Port 6 Port 0 Port 4 XBUS (-bit NON MUX Data / Addresses) Port 1 External Bus and XBUS Control, CS Logic (0-4 CS) External Instr./Data Interrupt Controller General Purpose Timer Unit 1 T 2 T 3 Port 5 T 4 Peripheral Data General Purpose Timer Unit 2 (C1O only) T 5 T 6 PEC 6-10 ext. IR Interrupt Bus USART Port 3 Synchronous Serial Channel (SSC) Watchdog Timer Port C1VKO RA Figure 1: Block Diagram of the C1 Versions

11 C1V C1K C1O Max. CPU Clock MHz Instruction Cycle Time 125 ns Internal RAM Size (IRAM) 1 KByte 1 KByte 2 KBytes Address Range 4 MB Max. I/O Lines 63 Chip Select Signals Bus Modes MUX MUX / Demux MUX / Demux Power Saving Modes --- yes yes External Interrupts General Purpose Timer Unit 1 yes GPT1 (3 Timers) Input / Output Functionality of --- yes yes GPT1 General Purpose Timer Unit yes GPT2 (2 Timers) Serial I/O USART+SSC On-chip Bootstrap Loader yes yes --- Package P-MQFP 80 Table 1: Key Features of the three C1 derivatives C1V, C1K, C1O CPU On-Chip Static RAM On-Chip ROM/ Flash EPROM 32 SP STK OV STK UV Exec. Unit Instr. Ptr. Instr. Reg. 4-Stage Pipeline MDH MDL Mul./Div.-HW Bit-Mask Gen. ALU -bit Barrel-Shift R15 General Purpose Registers R15 Data Page Ptr. PSW SYSCON Code Seg. Ptr. Context Ptr. R0 R0 Figure 2: CPU Block Diagram of the C1

12 Figure 3: GPT1 Block Diagram Semiconductor

13 CPU Clock 2 n n=2...9 T5 Mode Control Clear GPT2 Timer T5 Interrupt Request Capture CAPIN GPT2 CAPREL Interrupt Request Interrupt Request CPU Clock 2 n n=2...9 T6 Mode Control GPT2 Timer T6 T6OTL Figure 4: GPT2 Block Diagram

Infineon C167CR microcontroller, 256 kb external. RAM and 256 kb external (Flash) EEPROM. - Small single-board computer (SBC) with an

Infineon C167CR microcontroller, 256 kb external. RAM and 256 kb external (Flash) EEPROM. - Small single-board computer (SBC) with an Microcontroller Basics MP2-1 week lecture topics 2 Microcontroller basics - Clock generation, PLL - Address space, addressing modes - Central Processing Unit (CPU) - General Purpose Input/Output (GPIO)