cxt200 1 Datasheet, Revision 1.0

Transcription

1 cxt200 SoC OVERVIEW The Creator cxt200 is a system-on-chip device targeted for use in wireless connected products. It includes: 550 MHz dual core, dual thread MIPS interaptiv CPU Base band functions required for supporting ac 2x2 Wi-Fi (including AFE). DDR2/3 interface for use of external RAM Digital audio inputs and outputs CPU capable of encoding / decoding various audio codecs at the same time as running other functions required of the SoC. Peripherals and interface logic to allow connectivity to a range of external devices. 17 x 17mm, 0.8 mm pitch, LFBGA package MAJOR FEATURES Baseband for Wi-Fi standards (802.11ac 2x2) Digital audio input/output (I 2 S, S/PDIF) Connectivity: USB OTG, Ethernet 10/100, UART, SPI, SD Host, I 2 C. External memory: DDR2/3, Quad-SPI Flash or SPI Flash, SD Card or emmc TYPICAL APPLICATIONS IoT hub Home automation Wireless speaker Wireless AV system Wireless soundbar BLOCK DIAGRAM I2C I2C I2C I2C UART UART USB 2.0 Wi- Fi RF interface cxt200 Wi-Fi AFE Ensigma Volt RPU I2C 0 I2C 1 UART 0 UART 1 USB Phy USB OTG SDCard Host SD Card Wi- Fi RF interface Wi- Fi SPI Wi- Fi Fast Write Bluetooth SPI Bluetooth Data Path Audio I 2 S in ( 12 channel) Audio I 2 S out ( 12 channel) Stereo Line Out BT AFE Wi-Fi AFE BT Modem I2S Audio In (x12) I2S Audio Out (x12) Audio DAC UCC LTP240 Code/ Data RAM GRAM Parallel Audio Out Watchdog I2C 2 I2C 3 MIPS interaptiv Dual-core CPU CPU Core 32kB L1 D$ 32kB L1 I$ FPU CPU Core 32kB L1 D$ 32kB L1 I$ Coherency Manager (512kB L2 Cache) PWM PDM Serial Flash/SPI SPI 0 PWM Flash Screen/ External Peripheral S/ PDIF in S/ PDIF out JTAG 1v2 1v8 S/PDIF In S/PDIF Out JTAG Test & Debug PwrOn Reset Event Timers efuse Ctrl efuse Counters PLLs x7 DMA Clock Controller XO 16kB ROM SoC Fabric 64kB RAM DDR Ctrl DDR Phy GPIO & Pinmuxing Aux ADC InfraRed Ethernet RMII General Purpose Sensors Remote Control Ethernet Phy 3v3 Key: : Digital Analogue. Imagination. Core IP 52MHz Crystal DDR cxt200 1 Datasheet, Revision 1.0

2 HARDWARE OVERVIEW Physical Ambient temperature o -20 C to +85 C Maximum die temperature o 125 C Technology CPU Frequency o 550 / 320 / 160 / 104 / 80 / 26 / 13 MHz RPU o 550 MHz MIPS CPU o 350 MHz DDR 2/3 Controller MIPS interaptiv dual core, dual thread with FPU On-die memory MIPS 32 KiB L1 dcache per core: 64 KiB MIPS 32 KiB L1 icache per core: 64 KiB MIPS L2 cache: 512 KiB RPU Meta Core Code/Data: 304 KiB RPU MCP Code: 168 KiB RPU GRAM: 540 KiB System ROM: 24 KiB System RAM: 64 KiB DDR memory DDR2/3 256 MiB Maximum off-chip or up to 64MiB maximum in-sip External memory Power 1x 16-bit DDR2/3 o DDR2/3-400 to DDR2/3-800 o 16 MiB to 256 MiB 16-bit data Single rank 4 or 8 banks 14 rows 10 columns Quad-SPI Flash or SPI Flash emmc or SD Card (via SD Host) Core: 1.1V -5%/+9% Digital IO: 3.3V ± 10% Wi-Fi AFE: 1.1V -5%/+9% 1.8V ± 5% PLLVDD: 3.3V ± 5% USB PHY: 3.3V ± 10% 1.1V -5%/+9% DDR PHY: 1.5V ± 5% 1.8V ± 5% DDR IO: 1.8V ± 5% Boot Boot from SPI Flash Boot from SPI slave Boot via JTAG Interfaces Analogue Audio Out o Produced by stereo audio DAC 24-bit 48KHz I 2 S Audio In o 12x channel audio input I 2 S Audio Out o 12x channel audio output SPDIF Audio Input o 2x SPDIF audio input (2 inputs muxed to single SPDIF decoder) SPDIF Audio Output o 1x SPDIF audio output I 2 C x 4 o Each interface can be a master or a slave for interaction with a host controller or for general control DDR o 16-bit DDR2-800 / 16-bit DDR3-800 PDM DAC o 4 output channels, independently switched with PWM for control of e.g. display backlight PWM DAC o 4 output channels independently switched with PDM for control of e.g. RF AGC Aux ADC o 4 input channels for e.g. light sensor UART x2 o For general communication and debug GPIO o 12 dedicated GPIO o 81 digital outputs can be selected for use as GPIO IR-in (slave operation only) o For remote control via internal embedded decoder SPFI Master 0 o SPI master for peripheral interfacing SPFI Master 1 o Flash memory or as a SPI master for general peripheral control using individual Chip-Selects SPI Slave o SPI slave for host interfacing SD Host o Support for 1 slot or emmc. o An emmc or SD Card can be attached for external storage USB o USB 2.0 High Speed OTG Ethernet RMII (requires external 10/100 Mbps PHY Transceiver) o 10/100 Mbps MAC with RMII output WiFi baseband TXIQ and RXIQ compatible with common RF Transceivers JTAG o 5 wire JTAG Debug access MIPS Trace Interface o External trace bus with 8-bit wide data bus o Data bus width is not run-time configurable cxt200 2 Datasheet, Revision 1.0

3 Software upgrade Flash upgrade via USB DFU or USB MSC or Network upgrade Audio Inputs Digital o 6 stereo pair I2S inputs Supports 12 audio channels. Slave only Accepts clocks from an external source or from I2S audio output block. o 2x S/PDIF inputs muxed internally to a single S/PDIF decoder block. Analogue o No analogue audio input. Audio Outputs Digital o 6 stereo pair I2S outputs Supports 12 audio channels Master or Slave Accepts clocks from an external source or internally generated clocks. o 1x SPDIF output. Analogue o Stereo analogue line-output via mid performance DAC Human Interface Support LCD, Character or Dot-matrix display o SPI or I2C. IR remote control ADC: o 10-bit resolution o 1M samples/sec sampling rate o Internal mux: For monitoring of up to 6 external inputs, e.g.: Battery levels Ambient light levels Keypad Rotary encoder For monitoring of internal functions: Die temperature Core voltage GPIO o LED o Rotary encoder o Audio control o PWM/PDM o USB switch Power-On-Reset block Automatically asserts System Reset (RESET_N) output when power supplies are stable Connectivity Wi-Fi [requires suitable external RF Transceiver (e.g. KIWLANT65R2D22B) and Front-End Modules (e.g. Skyworks SKY85806)]: o b/g/a/n/ac o 2.4 / 5 GHz o Supports 2x2 MIMO o 20/40/80 MHz channels Bluetooth 4.1 (supported over UART): o BR/EDR Controller o LE Controller o Host o Low Duty Cycle Directed Advertising o L2CAP Connection Oriented Channels o Dual Mode Topology and Link Layer Topology Software Features Ethernet 10/100 Mbps o RMII (requires external 10/100 Mbps PHY Transceiver) USB o OTG o HS o FS SD Host / SDIO cxt200 3 Datasheet, Revision 1.0

4 PACKAGE BALL-OUT cxt200 4 Datasheet, Revision 1.0

5 cxt200 5 Datasheet, Revision 1.0

6 POWER SUPPLIES The power supply ball names of cxt200 are listed in the table below. Functional area Power ball names Suggested power supply name Min (V) Typ (V) Max (V) Abs max (V) Reference ball names Digital I/O (including SD Card / emmc interfaces) Digital and WiFi AFE cores Crystal oscillator Fractional PLL WiFi Fractional PLL VDD_IO_0, 1, 24 3V3_DIG VSS_IO_0, 1,...27 VDD_CORE_0, 1, 3, 4, 21 1V1_DIG VSS_CORE_0, 1, 2, 4, 24 OSC_VDD 3V3_DIG OSC_VSS PLLFRAC_VDDHV_0, 1 3V3_PLL PLL_AVSS_LAINT_0, 1 PLLFRAC_AVDD_WIFI 1V1_PLL PLLFRAC_AVSS_WIFI Integer PLL PLL_AVDD_LAINT_0, 1 1V1_PLL PLL_AVSS_LAINT_0, 1 WiFi IQ ADC reference WLAN0_IQADC_VREFP WLAN1_IQADC_VREFP 1V1_ANA via 3k3/1uF lowpass filter WLAN0_IQADC_VREFN WLAN1_IQADC_VREFN WiFi AFE ADC analogue WiFi AFE DAC analogue WLAN0_IQADC_AVDD, 0, 1, 2 WLAN1_IQADC_AVDD, 0, 1, 2 WLAN0_IQDAC_AVDDHV WLAN1_IQDAC_AVDDHV 1V1_ANA WLAN0_IQADC_AGND0, 1 WLAN1_IQADC_AGND0, 1 1V8_ANA WLAN0_IQDAC_AGND WLAN1_IQDAC_AGND BT AFE BTAFE_VDDA 1V1_ANA BTAFE_VSSA DDR core DDR_VDD_0, 1, 2, 3 1V1_DIG DDR_VSS_0, 1, 2, 20 DDR IO DDR_VDDQ_0, 1,.15 DDR_IO DDR_VSS_0, 1, 2, Audio DAC ADAC_AVDD_L ADAC_AVDD_R AVDD3V / ADAC_AVSS_L ADAC_AVSS_R Aux ADC analogue Aux ADC digital AUX_ADC_AVDD AVDD1V AUX_ADC_AVSSREF AUX_ADC_DVDD 1V1_DIG AUX_ADC_AVSS USB USB_VDD330_0 3V3_DIG USB_VSSA_0, 1, 2 USB core USB_DVDD 1V1_DIG VSS_CORE_0, 1, 2, 4, 24 A suggested power supply architecture, involving both linear and switch-mode regulators, is shown in Figure 1. Note that the current capability of each regulator is chosen to meet the requirements of cxt200 only, with some margin. However if, in a given user application, the regulators are used to power external circuitry as well, then the consumption of the external circuitry will have to be taken account and regulators with higher current capability may have to be chosen. The AVDD3V3 regulator may be omitted and the ADAC_AVDD_L / ADAC_AVDD_R balls powered from AVDD1V8 instead. This will save the cost of the AVDD3V3 regulator, but the maximum output voltage swing available from the DAC outputs (ADAC_DACOUT_L / ADAC_DACOUT_R) will be reduced from 1.8V ptp to 0.97V ptp. The process limits of the cxt200 place a limit on the absolute maximum (abs max) voltages that can be tolerated without permanent degradation. Typically, they might be exceeded during power-on if a regulator overshoots briefly, or when a positive-going transient occurs due to a sudden heavy current cxt200 6 Datasheet, Revision 1.0

7 demand during normal operation. The transient performance of the regulators must be carefully checked to ensure that any transients are safely below the absolute maximum levels specified in the table above. With the architecture suggested in Figure 1, the maximum expected current drawn from each power supply rail is given in the table below. These figures are based on limited samples and should only be considered as a guide to aid selection of the regulators and their associated components. Power supply rail Maximum average current draw (ma) Maximum peak current draw (ma) 3V3_DIG V8_ANA 10 1V1_ANA 80 AVDD1V8 1 AVDD3V3 1 3V3_PLL 1 1V1_PLL 10 1V1_DIG 1200 (at 1.175V) 1800 (at 1.175V) DDR_IO 135 (at 1.5V) 220 (at 1.8V) 220 (at 1.5V) cxt200 7 Datasheet, Revision 1.0

8 5V0_IN SMPS ma 3V3_DIG LDO 1 1.8V 150 ma 1V8_ANA LDO 2 1.1V 150 ma 1V1_ANA LDO 3 1.8V 50 ma AVDD1V8 LDO 4 3.3V 50 ma AVDD3V3 LDO 5 3.3V 50 ma 3V3_PLL Very high PSRR Low noise LDO 6 1.1V 50 ma 1V1_PLL SMPS 2 1.1V 2 Amp 1V1_DIG SMPS 3 1.5V or 1.8V 500 ma DDR_IO Figure 1 Suggested power supply architecture (sequencing details not included) In order that the RESET_N signal output from cxt200 is asserted cleanly by its Power-on-Reset block, it is essential that the 1V1_DIG, 3V3_DIG and AVDD1V8 supplies are sequenced in that order; it is also recommended that the DDR_IO, 1V1_ANA and 1V8_ANA supplies are sequenced as indicated. A suitable implementation is shown in Figure 2 and the timing diagram is shown in Figure 3. The 5ms sequencing delay is recommended as a minimum. cxt200 will assert RESET_N about 0.6ms after AVDD1V8 has risen, as indicated in Figure 3. 52MHz CLOCK The cxt200 requires a 52MHz clock for its operation. In order that cxt200 can generate this internally, an external crystal, with suitable loading capacitors, can be connected to the OSC_XI and OSC_XO inputs. However, if an RF Transceiver is included in the system, then this will also require a 52MHz clock, which it will be capable of generating from a crystal connected to its own XI and XO inputs. A buffered version of this clock is likely to be available from the Transceiver which can be used to provide a 52MHz clock directly to the OSC_XI input of cxt200, thus avoiding the need for a second crystal exclusively for the cxt200. The crystal must have a tolerance of ±10ppm at 25 C and a maximum variation of ±15ppm/ C over the temperature range 0 to 85 C. cxt200 8 Datasheet, Revision 1.0

9 5V0_IN SMPS 2 1V1_DIG VOLTAGE DETECTOR Delay 5 ms SMPS 1 3V3_DIG VOLTAGE DETECTOR Delay 5 ms LDO 3 AVDD1V8 SMPS 3 DDR_IO LDO 1 1V8_ANA LDO 2 1V1_ANA Figure 2 Recommended power supply sequencing implementation 1V1_DIG 3V3_DIG 5 ms AVDD1V8 DDR_IO 1V1_ANA 1V8_ANA 5 ms ~0.6 ms RESET_N (output from cxt200) Figure 3 Power supply sequencing timing. (cxt200 asserts RESET_N about 0.6ms after AVDD1V8 has risen.) cxt200 9 Datasheet, Revision 1.0

10 PACKAGE INFORMATION cxt Datasheet, Revision 1.0