TECHNOLOGY BRIEF. Double Data Rate SDRAM: Fast Performance at an Economical Price EXECUTIVE SUMMARY C ONTENTS

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1 TECHNOLOGY BRIEF June 2002 Compaq Computer Corporation Prepared by ISS Technology Communications C ONTENTS Executive Summary 1 Notice 2 Introduction 3 SDRAM Operation 3 How CAS Latency Affects System Performance 5 Double Data Rate SDRAM 6 Differences between Standard SDRAM and DDR SDRAM 6 2n-Prefetch Architecture 6 Strobe-based Data Bus 7 Signaling Technology 7 Reduced Power Requirements 8 DDR SDRAM DIMMs 8 DDR SDRAM Performance 8 The Future of DDR SDRAM 9 Conclusion 9 EXECUTIVE SUMMARY Memory technology is continually evolving to keep pace with the bandwidth demands of processors and server I/O interconnects For some years synchronous DRAM has been the most widely accepted memory technology due to its high performance (1 GB/s at 133 MHz) The evolution from SDRAM to DDR SDRAM actually began in 1999, but its adoption was slowed by what appeared to be more promising revolutionary memory technologies DDR SDRAM is now becoming more widely accepted in the server industry because of its faster performance (up to 27 GB/s at 166 MHz), power savings (25V compared to 33V for SDRAM), and lower cost than competing memory technologies The JEDEC Solid State Technology Association (once known as the Joint Electron Device Engineering Council) is now finalizing the specification for the next version of DDR SDRAM The new version, to be called DDR SDRAM II, will be backward compatible with DDR SDRAM and will improve bus utilization to increase performance and bandwidth to yield a theoretical peak bandwidth of 64 GB/s at 400 MHz Please direct comments regarding this communication to the ISS Technology Communications Group at this Internet address: TechCom@hpcom 1

2 TECHNOLOGY BRIEF (cont) N OTICE Compaq shall not be liable for technical or editorial errors or omissions contained herein The information is provided as is without warranty of any kind and is subject to change without notice The warranties for Compaq products are set forth in the express limited warranty statements accompanying such products Nothing herein should be construed as constituting an additional warranty Compaq and the Compaq logo are trademarks of Compaq Information Technologies Group, LP in the US and/or other countries All other product names mentioned herein may be trademarks of their respective companies 2002 Compaq Information Technologies Group, LP Compaq Computer Corporation is a wholly-owned subsidiary of Hewlett-Packard Company First Edition (June 2002) Document Number TC020603TB 2

3 TECHNOLOGY BRIEF (cont) INTRODUCTION SDRAM: synchronous dynamic random access memory DDR: double data rate Double Data Rate SDRAM has been around for awhile, but it has been in a battle for its very survival At first, it was thought that DDR SDRAM would simply prolong the life of SDRAM technology until a revolutionary memory technology came to market DDR SDRAM has not only survived, but it is becoming more widely accepted DDR SDRAM delivers twice the bandwidth of SDRAM, yet DDR SDRAM has the same core design as regular SDRAM Therefore, it has been easier and cheaper for memory manufacturers to convert production lines to DDR than to retool to adopt a revolutionary memory technology like Rambus DRAM These factors translate into much faster performance from DDR SDRAM at a lower cost The JEDEC Solid State Technology Association, the semiconductor engineering standardization body of the Electronic Industries Alliance, is currently developing the next-generation DDR SDRAM technology, called DDR SDRAM II This paper begins with a description of synchronous DRAM operation because it is a prerequisite to understanding the evolution of DDR SDRAM Readers already familiar with SDRAM may choose to skip forward to the section entitled Double Data Rate SDRAM SDRAM OPERATION Computers use two types of system memory cache memory and main memory Cache memory consists of very fast static RAM chips The most prevalent type of main memory used today is SDRAM As shown in Figure 1, SDRAM chips are installed on 168-pin dual inline memory modules (DIMMs) Each SDRAM chip consists of an array (columns and rows) of capacitors, which act as memory cells that store data A charged capacitor represents a 1 data bit, and an uncharged capacitor represents a 0 data bit SDRAM is dynamic because the capacitors need to be recharged (refreshed) by electric pulses thousands of times per second to retain the data On the periphery of the array of memory cells are transistors that read, amplify, and transfer the data from the memory cells to the memory bus Figure 1 Main Memory The memory bus is a circuit that consists of two parts: the data bus and the address bus The data bus is a set of lines (traces) that carry the actual data to and from SDRAM Each trace carries one data bit at a time The throughput (bandwidth) of the data bus depends on its width (in bits) and its frequency Today s computers have a 64-bit wide data bus, which means that the bus transports 64 bits (one data word) at a time The address bus is a set of traces that carry signals identifying the location of data in memory and the type of memory access (read or write) The address bus also 3

4 TECHNOLOGY BRIEF (cont) carries control signals that enable devices to negotiate for use of the memory bus The width of the address bus controls how much system memory the processor can read or write to; but unlike the data bus, its width has no direct impact on performance The memory subsystem operates at the memory bus speed, which has the same frequency (in MHz) as the main system bus clock When the processor needs to access (read or write) data in SDRAM, the memory controller first sends control signals that gain use of the data bus and then sends address signals that identify the location of the data in SDRAM When the address signals arrive at SDRAM, they go to a row address selector (RAS) and a column address selector (CAS) The RAS activates the entire row of the target cell and the CAS selects the specific cell that contains the data The controller sends another signal to designate whether data will be written or read By way of the transistors on the periphery of the cells, data is then transferred from the memory bus to the target cell or vice versa, depending on the type of access While SDRAM cells are being refreshed, they cannot be accessed until the refresh is completed SDRAM divides memory into two to four banks so that one memory bank can be accessed while the other bank is being refreshed This division allows continuous data flow SDRAM differs from earlier types of memory in that it runs synchronously to the system clock If you think of the numerous devices and circuits in the computer as musicians in an orchestra, then the system clock is like a conductor that keeps perfect time to coordinate their performance The system clock is an electronic signal that alternates between two voltages, designated as 0 and 1, at a specific pace or frequency (Figure 1) During each tick (cycle) of the clock, the voltage signal transitions from "0" to "1" and back to "0" The rising edge marks the start of the clock cycle when it transitions from 0 to 1 and the falling edge marks the end of the clock cycle when it transitions from 1 to 0 Because these transitions are not instantaneous, the rise time and fall time measure how long it takes to transition from 0 to 1 and 1 to 0, respectively A complete clock cycle is measured from one rising edge to the next rising edge Data transfer along the memory bus can be triggered on either the rising edge or falling edge of the clock signal Figure 2 Representation of a bus clock signal 4

5 TECHNOLOGY BRIEF (cont) SDRAM uses a process called data bursting to achieve greater data throughput than previous DRAM technologies The initial data word is usually transferred on the sixth clock cycle after the request is received (see Figure 3) Using burst mode access, data is burst out (or in) with every clock cycle after the first access After the memory controller sends the initial CAS, up to four consecutive 64-bit data words can be accessed before it has to send another CAS Figure 3 Burst mode access of SDRAM (top) Data transfer is triggered on the rising edge of the clock How CAS Latency Affects System Performance Unbuffered DIMMs do not use any buffer logic chips By eliminating propagation delay of the logic buffer during the first read/write operation, unbuffered DIMMs achieve slightly faster operation (by one clock cycle at the initial access) PC100: a DIMM that is rated at 8 ns and has other internal timing characteristics that allow it to function properly in a 100 MHz system Now let's review a typical SDRAM access using a memory bus speed of 100 MHz (10 ns per clock cycle) First, the controller activates the row and bank using the RAS signal After a period of time, the target cell is selected with the CAS signal Then it takes a period of time, called the column access time (t CAC ), for the data to be transported to the output transistor where it can be transferred to the bus on the next clock cycle At this point, the time needed for the first piece of data to become available is the CAS latency 2 or 3 clock cycles for unbuffered DIMMs and 3 or 4 clock cycles for buffered DIMMs Subsequent transfers are performed in burst mode (every clock cycle) up to the programmed burst length of 1, 2, 4, or 8 data words Why is CAS latency important? To guarantee compliance with the PC100 specification, vendors must specify the CAS latency of SDRAM DIMMs The specification only allows for CAS latency values of 1, 2, or 3 The CAS latency (CL) is based on the column access time, the time it takes to transfer data to the output transistors from the time the CAS line is activated CL is determined using the equation: CL * t CLK >= t CAC In plain English, this means that the time it can take to transfer data from the cell to the output transistor (t CAC ) has to be less than one clock cycle times the CAS latency For example, if t CLK is 10 ns (cycle time for a 100-MHz system clock) and t CAC is 20 ns, then the CL must be 2 But if t CAC is 25 ns, then CL must be 3 Some vendors refer to these values as CAS2 and CAS3, respectively For memory to be certified at 100 MHz, the CAS latency cannot be higher than 3 A CAS2 is slightly faster than a CAS3, which theoretically makes it function better in systems faster than 100 MHz 5

6 TECHNOLOGY BRIEF (cont) D OUBLE D ATA R ATE SDRAM Processors today operate much faster than the memory subsystem; therefore, increasing the speed of the memory bus would improve overall system performance more than further increasing the speed of the processor System designers can speed up the memory bus by increasing the system clock frequency; however, this creates several issues regarding signal integrity As the system clock frequency increases, the timing becomes tighter Tighter timing increases both the interference between signals and the hardware costs because circuits must be made more precise to deal with the higher speeds So system designers came up with an innovative way to double the memory bus bandwidth without increasing the clock frequency by using both the rising and falling edges of the clock to trigger data transfer This technology, known as double transition clocking, is not new Accelerated Graphics Port (AGP) technology uses it to double I/O performance over conventional PCI buses Similarly, DDR SDRAM uses double transition clocking to deliver twice the bandwidth of standard DRAM without increasing the clock frequency (Figure 4) DDR SDRAM has peak data transfer rates of 16 and 21 GB/s at clock frequencies of 100 MHz and 133 MHz, respectively Figure 4 Representation of DDR SDRAM transferring data on the rising and falling edges of the clock The following section will summarize at a high level the basic differences between DDR SDRAM and standard SDRAM This section will clarify the challenges faced by system designers in implementing DDR SDRAM and describe the technical advances and physical differences that make it incompatible with standard SDRAM The subsequent section will describe plans for DDR SDRAM II Differences between Standard SDRAM and DDR SDRAM DDR SDRAM has the same core design as standard SDRAM, but DDR SDRAM has some enhancements that enable it to achieve higher data rates: 2n-Prefetch Architecture, a strobe-based data bus, different signaling technology, and reduced power requirements Because DDR SDRAM uses the rising and falling edges of the clock, CAS latency for DDR SDRAM is 2 and 25 instead of 2 and 3 2n-Prefetch Architecture The DDR SDRAM design uses a 2n-prefetch architecture, which, at a high level, means that its internal data bus is twice the width of the external data bus This means that a single read access fetches two data words instead of just one as with standard SDRAM Similarly, two data words are combined and written to the DDR SDRAM core during a single write access A more detailed description is outside the scope of this paper More information on the 2n-prefetch architecture is available in the JEDEC standard JESD79, Double Data Rate (DDR) SDRAM Specification 6

7 TECHNOLOGY BRIEF (cont) Strobe-based Data Bus In a synchronous system, data output and capture are referenced to transitions in the system clock When the clock signal transitions, an operation is signaled to begin; however, a period of time must pass before the signal stabilizes As shown in Figure 5, access time (t AC ) is the amount of time it takes to "open" the output line from the prior clock "tick t AC is specified as a maximum value because one DDR DRAM chip may have a t AC =4 ns while another chip may have a t AC =6 ns To be able to send data out on every clock cycle, t AC must be fast enough to allow the signal to stabilize before beginning the actual output operation Figure 5 Representation of the data valid window, or data eye, for DDR SDRAM Because of possible distortion (skew) in the SDRAM chips and printed circuit board, as the bus frequency increases, it can become more difficult for components to capture data using a clock This is especially true for DDR SDRAM because its data capture rate is twice the clock frequency The issue is that the region where the data is valid (called a data eye) is so small that it is very difficult to meet setup and hold timing (the period of time that must pass to allow the signal to stabilize) For example, if the bus frequency is increased to 200 MHz, the clock cycle (transition) is only 5 ns In an ideal world, each data word (64 bits) sent by the source device would arrive at the capturing device at exactly the same time so they could be captured every 5 ns However, because of real factors such as trace length differences and variations in temperature, voltage, and manufacturing processes, the data eye may move in relation to the fixed clock signal As a result, the time the data is stable is 5 ns minus the extra delays To assist with the tight timing requirements, the source device sends a reference signal called a strobe with the data The data strobe signal helps the capturing device to locate data more accurately and resynchronize incoming data from different DIMMs During a write operation, the memory controller places the rising and falling edge of the strobe in the middle of the data eye so it can be used to capture the data at the SDRAM For read accesses, SDRAM also sends data with a strobe, but the strobe edge is aligned with the data The device receiving the read data must shift the strobe to the center of the data eye Read and write accesses have different strobe alignment so that the delay circuitry can be centralized in one place (the controller) and does not have to be replicated in every DRAM device in the system Although tight system timing requirements were alleviated on the data bus by using bi-directional strobes, they were not removed for the command bus The command bus does not use a strobe and must still meet setup times to a synchronous clock Signaling Technology Another difference between SDRAM and DDR SDRAM is the signaling technology DDR SDRAM uses Stub Series Terminated Logic (SSTL) instead of the Low Voltage Transistor-to- Transistor Logic (LVTTL) that standard SDRAM uses This signaling interface change, in addition to using data strobes, allows DDR SDRAM to run at faster speeds than traditional SDRAM 7

8 TECHNOLOGY BRIEF (cont) Reduced Power Requirements DDR SDRAM has another significant improvement The voltage supply for DDR SDRAM uses only 25 V, instead of 33 V The lower voltage and the lower capacities inside the memory chips lead to a significantly reduced power consumption, which makes DDR SDRAM a good choice for density-optimized servers DDR SDRAM DIMMs DDR SDRAM DIMMs come with 184 pins instead of the 168 pins used by standard SDRAM DIMMs Figure 6 shows a photo of an unbuffered DDR SDRAM DIMM Note that the DDR DIMM has one notch instead of the two notches found in SDRAM DIMMs DDR SDRAM DIMMs cannot be used in servers that support standard SDRAM DIMMs Figure 6 Unbuffered DDR SDRAM DIMM DDR SDRAM Performance Initially, DDR SDRAM that operates at 100 MHz was named PC200 and DDR SDRAM that operates at 133-MHz was named PC266 The numbering for PC200 and PC266 referred to the effective clock of the data transfer Then, Rambus used PC600 and PC800 to describe their 300- MHz and 400-MHz RDRAM modules PC600 and PC800 may sound faster than PC200 and PC266, but they are not Therefore, the memory industry developed a numbering system based on the actual peak data transfer rate in MB/s; for example, PC1600 and PC2100 Thus, PC200 is the same as PC1600 (64 bits * 2 * 100 MHz = 1600 MB/s) and PC266 is the same as PC 2100 (64 bits * 2 * 133 MHz = 2133 MB/s) Table 1 summarizes the naming conventions of various types of DDR SDRAM and their theoretical bandwidths Table 1 Naming Conventions and Theoretical Bandwidths of DDR SDRAM Component Naming Convention Module Naming Convention Type Bus Speed Peak Bandwidth DDR200 PC1600 DDR-I 100MHz 16 GB/s DDR266 PC2100 DDR-I 133 MHz 21 GB/s DDR333 PC2700 DDR-I 166 MHz 27 GB/s DDR400 PC3200 DDR-II 200 MHz 32 GB/s DDR533 PC4300 DDR-II 266 MHz 43 GB/s DDR667 PC5300 DDR-II 333 MHz 53 GB/s DDR800 PC6400 DDR-II 400 MHz 64 GB/s 8

9 TECHNOLOGY BRIEF (cont) THE F UTURE OF DDR SDRAM The JEDEC Solid State Technology Association is currently developing the next-generation DDR SDRAM technology, called DDR SDRAM II This next generation technology will be backward compatible with DDR SDRAM but not with standard SDRAM DDR SDRAM II will improve bus utilization to double the bandwidth, yielding a theoretical peak bandwidth of 64 GB/s (see Figure 7) It is also expected to provide improvements in cost, power requirements, I/O, packaging, and clocking Figure 7 Comparison of bandwidths for standard SDRAM, Rambus DRAM, DDR SDRAM, and DDR SDRAM II C ONCLUSION SDRAM continues to provide good performance in servers and workstations; but for memory subsystem performance to keep up with future processors, the memory bus bandwidth must continue to increase Compared to revolutionary memory technologies, DDR SDRAM delivers faster performance at lower cost, which is necessary for industry-wide adoption While the basic principle of DDR SDRAM is simple transfer data on both the rising and falling edges of the system clock signal the reality is that system designers had to solve several technical issues regarding signal integrity at the higher bus speeds System designers were successful; however, the technical advances that enable DDR SDRAM to achieve higher data rates also make it incompatible with standard SDRAM The next version, DDR SDRAM II, promises to push the performance of the memory subsystem to even higher levels DDR SDRAM II will be backward compatible with DDR SDRAM and will improve bus utilization to increase performance and bandwidth, yielding a theoretical peak bandwidth of 64 GB/s 9