Memory Interfacing & decoding. Intel CPU s

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1 Memory Interfacing & decoding in Intel CPU s

2 Outline Address decoding Chip select Memory configurations

3 Minimum Mode - - A19 - A19 - Simplified Drawing of 8088 Minimum Mode MEMORY MEMW When Memory is selected?

4 Minimum Mode 2 20 bytes or 1MB - - A19 - A19 - Simplified Drawing of 8088 Minimum Mode MEMORY MEMW

5 What are the memory locations of a 1MB (2 20 bytes) Memory? A19 to (HEX) FFFFF Example 34F

6 Interfacing a 1MB Memory to the 8088 Microprocessor FFFFD FFFFE FFFFF A19 A19 CX BX AX F1C FCA1 DX D 13 ES DS SS F4 8A BP SP SI IP DI MEMW

7 Instead of Interfacing 1MB, what will happen if you interface a 512KB Memory?

8 What are the memory locations of a 512KB (2 19 bytes) Memory? to (HEX) FFFF

9 Interfacing a 512KB Memory to the 8088 Microprocessor AX BX CX DX SS DS ES BP SP 3F1C FCA A19 What do we do with A19? 7FFFF 36 7FFFE 7FFFD D SI DI IP MEMW

10 What if you want to read physical address 023? AX BX CX DX SS DS ES BP SP 3F1C FCA1 00 A19 7FFFF 36 7FFFE 7FFFD D SI DI IP MEMW

11 What if you want to read physical address 023? A19 to (HEX) A19 is not connected to the memory so even if the 8088 microprocessor outputs a logic 1, the memory cannot t see this.

12 What if you want to read physical address 20023? to (HEX) For memory it is the same as previous For memory it is the same as previous one.

13 Interfacing two 512KB Memory to the 8088 Microprocessor CX BX AX F1C FCA1 DX A19 7FFFD 7FFFE 7FFFF ES DS SS D 13 MEMW BP SP SI IP DI FFFD 7FFFE 7FFFF 33 2C A D4

14 Interfacing two 512KB Memory to the 8088 Microprocessor Problem Bus Conflict. The two memory chips will provide data at the same time when microprocessor performs a memory read. Solution Use address line A19 as an arbiter. If A19 outputs a logic 1 the upper memory is enabled (and the lower memory is disabled) and vice-versa.

15 Interfacing two 512KB Memory to the 8088 Microprocessor CX BX AX F1C FCA1 DX A19 7FFFD 7FFFE 7FFFF ES DS SS D 13 MEMW BP SP SI IP DI FFFD 7FFFE 7FFFF 33 2C A D4

16 What are the memory locations of two consecutive 512KB (2 19 bytes) Memory? A19 to (HEX) FFFF FFFFF

17 Interfacing two 512KB Memory to the 8088 Microprocessor AX BX CX DX SS DS ES BP SP SI DI IP 3F1C FCA A19 MEMW When the P outputs an address between to FFFFF, 7FFFF, this memory is selected 7FFFF 36 7FFFE 25 7FFFD D FFFF 12 7FFFE 98 7FFFD 2C A D

18 Interfacing two 512KB Memory to the 8088 Microprocessor CX BX AX F1C FCA1 DX A19 7FFFD 7FFFE 7FFFF ES DS SS D 13 MEMW BP ES SP SI IP DI FFFD 7FFFE 7FFFF 33 2C A D4

19 Interfacing two 512KB Memory to the 8088 Microprocessor CX BX AX F1C FCA1 DX A19 7FFFD 7FFFE 7FFFF A19 ES DS SS D 13 MEMW BP ES SP SI IP DI FFFD 7FFFE 7FFFF 33 2C A D4

20 What if we remove the lower memory? CX BX AX F1C FCA1 DX A19 7FFFD 7FFFE 7FFFF ES DS SS D 13 MEMW BP SP SI IP DI FFFD 7FFFE 7FFFF 33 2C A D4

21 What if we remove the lower memory? AX BX CX DX SS DS ES BP SP SI DI IP 3F1C FCA A19 MEMW When the P outputs an address between to FFFFF, 7FFFF, no memory this memory chip is is selected! 7FFFF 36 7FFFE 25 7FFFD D

22 Full and Partial Decoding Full Decoding When all of the useful address lines are connected the memory/device to perform selection Partial Decoding When some of the useful address lines are connected the memory/device to perform selection Using this type of decoding results into roll-over addresses

23 Full Decoding CX BX AX F1C FCA1 DX A19 7FFFD 7FFFE 7FFFF ES DS SS D 13 MEMW BP SP SI IP DI

24 Full Decoding A19 to (HEX) FFFFF A19 should be a logic 1 for the A19 should be a logic 1 for the memory chip to be enabled

25 Full Decoding A19 to (HEX) FFFF Therefore if the microprocessor outputs an address between to 7FFFF, whose A19 is a logic 0, the memory chip will not be selected

26 Partial Decoding CX BX AX F1C FCA1 DX 7FFFF 36 A19 ES DS SS FFFD 7FFFE BP SP D 13 MEMW SI IP DI

27 Partial Decoding A19 to (HEX) FFFF FFFFF The value of A19 is INSIGNIFICANT to the The value of A19 is INSIGNIFICANT to the memory chip, therefore A19 has no bearing whether the memory chip will be enabled or not

28 Partial Decoding A19 to (HEX) FFFF FFFFF ACTUAL ADDRESS

29 Partial Decoding A19 to (HEX) FFFF FFFFF ACTUAL ADDRESS

30 Interfacing two 512K Memory Chips to the 8088 Microprocessor 8088 Minimum Mode A19 MEMW 512KB #2 512KB #1

31 Interfacing one 512K Memory Chips to the 8088 Microprocessor 8088 Minimum Mode A19 MEMW 512KB

32 Interfacing one 512K Memory Chips to the 8088 Microprocessor (version 2) 8088 Minimum Mode A19 MEMW 512KB

33 Interfacing one 512K Memory Chips to the 8088 Microprocessor (version 3) 8088 Minimum Mode A19 MEMW 512KB

34 Interfacing four 256K Memory Chips to the 8088 Microprocessor 256KB A19 256KB #4 256KB # Minimum Mode MEMW 256KB #2 256KB #1 #1

35 Interfacing four 256K Memory Chips to the 8088 Microprocessor 256KB A19 256KB #4 256KB # Minimum Mode MEMW 256KB #2 256KB #1 #1

36 Memory chip# is mapped to A19 to (HEX)

37 Interfacing four 256K Memory Chips to the 8088 Microprocessor 256KB A19 256KB #4 256KB # Minimum Mode MEMW 256KB #2 256KB #1 #1

38 Interfacing four 256K Memory Chips to the 8088 Microprocessor 256KB A19 256KB #4 256KB # Minimum Mode MEMW 256KB #2 256KB #1

39 Interfacing four 256K Memory Chips to the 8088 Microprocessor 256KB A19 256KB #4 I1 I0 O3 256KB # Minimum Mode MEMW O2 256KB #2 O1 256KB #1 O0

40 Interfacing several 8K Memory Chips to the 8088 P A19 A16 A15 A14 A13 A12 8KB #? 8088 Minimumi Mode A12 MEMW A12 8KB #2 A12 8KB #1

41 Interfacing 128 8K Memory Chips to the 8088 P A19 A16 A15 A14 A13 A12 8KB # Minimumi Mode A12 MEMW A12 8KB #2 A12 8KB #1

42 Interfacing 128 8K Memory Chips to the 8088 P A19 A16 A15 A14 A13 A12 8KB # Minimum Mode A12 MEMW A12 8KB #2 A12 8KB #1

43 Memory chip# is mapped to A19 to (HEX)

44 Memory Terms Capacity Kbit, Mbit, Gbit Organization Address lines Data lines Speed / Timing Access time Write ability ROM RAM

45 ROM Variations Mask Rom PROM OTP EPROM UV_EPROM EEPROM Flash memory

46 RAM Variations SRAM DRAM NV-RAM SRAM CMOS Internal lithium battery Control circuitry to monitor Vcc

47 Memory Chip 8K SRAM to be specific 8Kx88 bits SRAM A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 OE WE 1 2

48 6264 Block Diagram

49 6264 Function Table

50 Memory Chip 8K EPROM to be specific 8Kx88 bits EPROM A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 G P C VPP

51 2764 Block Diagram Chip enable Output enable

52 Operating Modes

53 Programming 2764 after each erasure for UV-EPROM) all bits of the M2764A are in the 1" state. The only way to change a 0" to a 1" is by ultraviolet light erasure. Programming mode when VPP input is at 12.5V E and P are at TTL low. The data to the data output pins. The levels required for the address and data inputs are TTL.

54 Interfacing 128 8K Memory Chips to the 8088 P A19 A16 A15 A14 A13 A12 8KB # Minimum Mode A12 MEMW A12 8KB #2 A12 8KB #1

8051 INTERFACING TO EXTERNAL MEMORY

8051 INTERFACING TO EXTERNAL MEMORY Memory Capacity The number of bits that a semiconductor memory chip can store Called chip capacity It can be in units of Kbits (kilobits), Mbits (megabits), and so on