DDR3 Memory for Intel-based G6 Servers

Transcription

1 DDR3 Memory for Intel-based G6 Servers March Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.

2 New memory technology with G6; DDR-3 Bandwidth doubles 667 to 1333MHz DDR2; 4 channels DDR3; 6 channels Flexibility Unbuffered DIMMs Registered DIMMs Larger memory footprints Increased slot counts with G6 DDR-3 Energy efficiency Thermal temperature sensors powers down when idle Voltage reduced from 1.8V to 1.5V Lower latency DDR2 DDR2 667 CL5 = 15.0ns DDR3 (10-13% lower) DDR CL9 = 13.5ns DDR CL7 = 13.1ns DDR3 800 CL6 = 15.0ns Address error detection 24GB with UDIMMs 144GB with RDIMMs Enabled with DDR3 (RDIMMs) 2 24 March 2009

3 DDR3 memory; lower power, improved bandwidth Next generation memory for all Intel G6 ProLiants Reduced power architecture, due to lower core voltage (from 1.8V to 1.5V; 17% savings) >25% power savings over DDR2 (DDR2-800 vs. DDR3-800) >35% higher bandwidth per watt (DDR2-667 vs. DDR3-1066) 3 24 March 2009 Data from Intel Developer Forum.

4 Customer choice with DDR3 If uncertain, go with RDIMM for more flexibility Maximum capacity 4 24 March 2009 DDR3 Technology Comparison RDIMMs Higher capacity, memory register, address parity 144GB max capacity (18 slots; 8GB dual rank DIMMs) UDIMMs Smaller capacity, lower price points, basic ECC 24GB max capacity (12 slots; 2GB dual rank DIMMs) Capacities at launch 2GB, 4GB, 8GB 1GB, 2GB Max. DIMMs/channel 3 Dual Rank 2 Dual Rank Low power option Address parity Lower cost 4GB Quad-Rank (memory register) Ranks/DIMM support 1, 2, 4 1, 2 DRAM support x4, x8 x8 Latency DIMM power (smaller capacities) 1 clock advantage 1 watt less (no register)

5 More channels & more slots Platform configurations (18 DIMMs) Up to 3 channels per Up to 3 DIMMS per channel Memory types supported DDR3 1333, 1066 & 800MHz Registered (RDIMM) Unbuffered (UDIMM) Single-rank, dual-rank, quad-rank Up to 3 channels per System memory speed set by BIOS depending on capability DIMM types used memory speed, U/RDIMM, SR/DR/QR) DIMMs populated per channel slot configuration Up to 3 DIMMs per channel 12-slot configuration also available 5 24 March 2009 Note that UDIMMs are limited to 2 DIMMs/channel & 24GB maximum.

6 DDR3 RDIMM population scenarios Maximum capacity 800MHz across 6 channels (to 29GB/s^) Up to 3 DPC (18 DIMMs total) Capacity: 144GB (w/ 8GB RDIMMs) Virtualization environments Balanced performance 1066MHz across 6 channels (to 36GB/s^) Up to 2 DPC (12 DIMMs) Capacity: 96GB (w/ 8GB RDIMMs) General purpose enterprise workload Maximum bandwidth 1333MHz across 6 channels (to 40GB/s^) 1 DPC (6 DIMMs); 95watt needed Capacity: 24GB (w/ 4GB RDIMMs)* HPC technical computing ^ - measured bandwidth #s 6 24 March 2009 Tip for best performance, go wide before deep. Spread DIMMs across channels, starting farthest from the s. *; 4GB DIMMs required to get 1333MHz; 8GB DIMMs are 1066MHz max. Note that UDIMMs are limited to 2 DIMMs/channel & 24GB maximum.

7 Reliability configuration options RAS; Reliability, Availability, Serviceability Independent channel mode Online spares mode Mirrored channel mode Lockstep channel mode # of Channels spare 2 2 Must Populate Identically? Max Memory supported (8GB DDR3-800) No Yes Yes Yes 144GB 96GB 48GB 96GB Maximum memory shown is full 2 servers Spares Mirroring Lockstep Spare chnl not usable by system memory 7 24 March 2009 Spares mode not supported at initial announce (coming with Westmere update). Ch 1 & 2 mirror each other Ch 3 unused Diagrams reflect just one (of 2 possible) s Ch 1 & 2 operate in lockstep Ch 3 unused correct up to an 8-bit error, vs. only 4-bit errors.

8 Optimizing your ProLiant G6 Memory performance guidelines & configurations Use identical DIMM types (same HP part #) throughout the server Same size, speed, and number of ranks Use a balanced platform configuration Populate the same for each channel and each socket Maximize # of channels populated for highest bandwidth 8 24 March 2009 Note that UDIMMs are limited to 2 DIMMs/channel & 24GB maximum.

9 Update footnote to reflect 800MHz specific s G6 server memory capacities RDIMM maximum capacity 144GB (8GB 2Rank) UDIMM maximum capacity 24GB (2GB 2Rank) 9 24 March Watt processors needed to run 1333MHz. See population rules for additional guidelines.

10 Slot diagrams for G6 servers Follow the detailed population rules for guidelines Online configuration tool; Tip for best performance, spread DIMMs across channels, starting farthest from the s. Note the population order does this. DIMM Type Max memory capacities from HP options Notes Single rank No single rank RDIMM offered RDIMM UDIMM Dual rank 144GB (18x 8GB DIMMs) Quad rank 48GB (12x 4GB DIMMs) QR limited to 2DPC Single rank 12GB (12x 1GB DIMMs) Dual rank 24GB (12x 2GB DIMMs) UDIMM limited to 2DPC March 2009

11 DDR3 DIMM population rules Loading goes from heaviest load (quad-rank) to lightest load (single-rank) within a channel. Heaviest load (DIMM with most ranks) within a channel goes furthest from the chipset. You can only install two quad-rank DIMMs per channel. You can only have up to 8 ranks installed per channel. It is not required, but it is recommended to spread DIMMs uniformly across channels, starting farthest from first. Only two UDIMMs per channel can be installed. The third socket in the channel will remain empty. UDIMMs and RDIMMs cannot be mixed within a system - even on the other processor. Also, when QR DIMMs are installed, all channels are limited to 2 DIMMs per channel. If only one processor is installed, only 1/2 of the DIMM sockets are available. For mirroring, channel 2 remains unpopulated. Channels 0 and 1 are populated identically All three channels per processor are populated identically when using online spare mode. ML330 supports up to 18 DIMMs only with optional processor riser card and 2nd processor installed If using lock-step mode, channel 2 must be unpopulated. DIMMs in channels 0 and 1 will be installed in pairs. The paired slots will be 1,4; 2,5; 3,6 on a 3DPC system or 1,3; 2,4 on a 2DPC system. If clock speeds are mixed, system will run at lowest speed installed. Efficiency: If possible, use UDIMMs unless you can't for desired system capacity. Otherwise, fewer DIMMs is better. Also, if possible, use LP or LV DIMMs when available. Virtualization: Load as few high-capacity DIMMs as possible to meet the memory requirement. Lowest latency: Load DIMMs in sets of 3 keeping the channels balanced. Load all sockets with identical memory part numbers. Overall, this will provide the lowest latency. Quad rank can be mixed within a channel with other RDIMMs. 95 Watt processors (X-series) needed to run 1333MHz (when populated with 1DPC). Online spares not supported at initial announce; expected with Westmere updates. Subject to change and update March 2009 How are channels labeled; 0,1,2 or 1,2,3? Update footnote to reflect 800MHz specific s

12 G6 server specific memory highlights Server s DIMM Slots Max. Memory (w RDIMM) Online Spares (after announce) Advanced Memory Protection Memory Mirroring Lock Step BL280c G6 2 12* 96 GB yes yes yes BL460c G6 2 12* 96 yes yes yes BL490c G yes yes yes DL160 G no no no DL180 G6 2 12* 96 no no no DL360 G yes yes yes DL380 G yes yes yes ML150 G6 2 12* 48^ no no no ML350 G yes yes yes ML370 G yes yes yes March 2009 Notes: Online spares not supported at initial launch (Westmere update). ^ - ML150 G6 does not support 8GB DIMMs. * - 12-slot servers will not support 3DPC.

13 DDR3 memory part numbers (at launch) Registered Dimms (RDIMMs); up to 144GB RDIMMs offer larger capacities than UDIMMs and include address parity protection B21 HP 2GB 2Rx8 PC R-9 Kit (1333MHz; 1Gb) B21 HP 4GB 2Rx4 PC R-9 Kit (1333; 1Gb) B21 HP 4GB 4Rx8 PC3-8500R-7 LP Kit (1067; 1Gb) B21 HP 8GB 2Rx4 PC3-8500R-7 Kit (1067; 2Gb) Unbuffered with ECC DIMMs (UDIMMs); up to 24GB UDIMMs offer lower latency and power consumption than RDIMMs, but are limited in capacity B21 HP 1GB 1Rx8 PC E-9 Kit (1333; 1Gb) B21 HP 2GB 2Rx8 PC E-9 Kit (1333; 1Gb) March 2009 Part numbers shown are for initial G6 launch only.

14 DDR3 part number description format Rank 1R = single 2R = dual 4R = quad Memory Type PC3 = DDR3 DIMM Type E = unbuffered with ECC R = registered CAS latency 7 = = = Future speeds may be two digits HP ggggg erxff PC3v-wwwwwm-aa-bb-ccd Kit Capacity 1GB 2GB 4GB 8GB 16GB March 2009 Data width x8 = 8 x4 = 4 Voltage Blank = 1.5V L = 1.35V U = TBD; ~1.25V Module Bandwidth 8500 MB/s (DDR3-1066) MB/s (DDR3-1333) Above format becomes; HP 8GB 2Rx4 PC3-8500R-7 Kit Additional characteristics in some categories will come after initial G6 launch (example; higher bandwidth speeds). Special Descriptor (if needed) LP (low power)

15 DDR3 part number format Format taken from JEDEC Committee: JC-45 Committee Item Number: a HP ggggg erxff PC3v-wwwwwm-aa-bb-ccd Kit ggggg = Module total capacity, in bytes 256MB, 512MB, 1GB, 2GB, 4GB, etc. er = Number of ranks of memory installed 1R = 1 rank of DDR3 SDRAM installed 2R = 2 ranks 4R = 4 ranks xff = Device organization (bit width) of DDR3 SDRAMs used on this assembly x4 = x4 organization (4 DQ lines per SDRAM) x8 = x8 organization x16 = x16 organization (not supported by ISS) v = SDRAM and support component supply voltage (VDD) Blank = 1.5V operable L = 1.35V operable, 1.5V operable U = 1.TBDV operable, 1.TBDV endurant [expect ~1.25V] wwwww = Module bandwidth in MB/s 6400 = 6.40 GB/s (DDR3-800 SDRAMs, 8 byte primary data bus) 8500 = 8.53 GB/s (DDR SDRAMs, 8 byte bus) = GB/s (DDR SDRAMs, 8 byte bus) = GB/s (DDR SDRAMs, 8 byte bus) = GB/s (DDR SDRAMs, 8 byte bus) = GB/s (DDR SDRAMs, 8 byte bus) m = Module Type E = Unbuffered DIMM ("UDIMM"), with ECC (x72 bit module data bus) F = Fully Buffered DIMM ( FB-DIMM") L = Load Reduction DIMM ( LR-DIMM ) M = Micro-DIMM N = Mini-RDIMM R = Registered DIMM ("RDIMM") S = Small Outline DIMM ("SO-DIMM") U = Unbuffered DIMM ("UDIMM"), no ECC (x64 bit module data bus) aa = DDR3 SDRAM CAS Latency in clocks at maximum operating frequency bb = JEDEC SPD Revision Encoding and Additions level used on this DIMM cc = Reference design file used for this design (if applicable) A = Reference design for raw card A is used for this assembly B = Reference design for raw card B is used for this assembly AC = Reference design for raw card AC is used for this assembly ZZ = None of the reference designs were used for this assembly d = Revision number of the reference design used 0 = Initial release 1 = First revision 2 = Second revision P = Pre-release or Engineering sample Z = To be used when field cc = ZZ March 2009 Format directly matches JEDEC format. Not all parts/spaces/codes will apply to ISS server memory.

16 Memory technology cheat sheet DDR3 is the third generation of Double Data Rate (DDR) SDRAM memory. It is a continuing evolution of DDR memory technology that delivers higher speeds, lower power consumption and heat dissipation. It is an ideal memory solution for bandwidth hungry systems equipped with dual and quad core processors. Capacities available include 1, 2, 4 & 8GB (16GB available in the future). HP DDR3 option kits consist of single dimms. DIMM type UDIMMs with ECC offer lower latency and power consumption than RDIMMs, but are limited in capacity. Unbuffered with ECC identified with an E in the manufacturer s module name (example PC3-8500E). RDIMMs also have ECC and offer larger capacities than UDIMMs and include address parity protection. Registered identified with an R in the module manufacturer s name (example PC3-8500R). Speed indicates the data rate of the DRAM chips and the Memory Module that uses those chips. HP offers two base speeds; DDR DRAM operates at 1066 Mbits/s. A DIMM with DDR DRAM is called PC (1066 x 8 Bytes ~= 8500 MBytes/s) DDR DRAM operates at 1333 Mbits/s. A DIMM with DDR DRAM is called PC (1333 x 8 Bytes ~=10600 MBytes/s) System realized speeds will depend on how the server is populated with memory. Rank DDR3 will support Single, Dual and Quad rank DIMMs. Rank refers to DRAM chips that are ganged together to provide 64 bits (8 Bytes) of data on the memory bus. All chips in a rank are controlled simultaneously by the same Chip Select, Address and Command signals. Data width x4 and x8 indicate the number of data outputs per DRAM. Eight x8 DRAMs make one rank. Sixteen x4 DRAMs make one rank. 64 bits in each case. Unbuffered ECC as well as Registered DIMMs will have: 9 DRAMs (x8) or 18 DRAMs (x4) per rank. Density Describes the number of storage locations in a DRAM chip. DDR3 will launch with 1Gb and 2Gb-based DRAM. No 512Mb in DDR3. Voltage Over time, DDR3 memory will consist of three voltage ratings; Standard at announce (1.5V); future plans call for Low Voltage (1.35V) and Ultra Low Voltage (TBD; ~1.25V) DDR3 has lower power architecture, due to lower core voltage >25% power savings over DDR2 (DDR2-800 vs. DDR3-800) DDR consumes less power than DDR CAS latency - Column Address Strobe latency refers to the DRAM read response time in number of bus clocks from the Column Address to the DRAM providing data on the memory bus. A lower number will yield a performance increase for March 2009 most applications.

17 Resources coming with G6/DDR3 (URL not active until announce date) March 2009

18 Technology for better business outcomes