ST7920 has wide operating voltage (2.7V to 5.5V) and low power consumption suitable for battery power portable device.

Transcription

1 ST Sitronix ST792 Chinese Fonts built in LCD controller/driver Main Features Voltage operating range: to 5.5V Support 8 bit, 4 bit, serial bus MPU interface 64 x 6-bits character display RAM (max. 6 chars x 4 lines, LCD display range 6 char. X 2 lines 64 x 256-bits graphic display RAMGDRAM 2M-bits Chinese fonts ROM (CGROM) supporting 892 Chinese fonts (6x6 dot matrix) 6K-bits half height ROM (HCGROM) supporting 26 character set (6x8 dot matrix) 64 x 6-bits character generation RAM (CGRAM) 32-common x 64-segment (2 lines display) LCD drivers Automatic power on reset External reset pin (XRESET) With extension segment drivers display area can up to 6x2 lines RC oscillator built in (with external R) Low power design Normal mode (45uA Typ VDD=5V) Standby mode (3uA Max VDD=5V) VLCD (V~ Vss): max 7V Graphic and character mix modes display Multiple instructions - Display clear - Return home - Display on/off - Cursor on/off - Display character blink - Cursor shift - Display shift - Vertical line scroll - By_line reverse display - Standby mode Built in voltage booster (2 times) /32 Duty Function Description ST792 LCD controller/driver IC can display alphabets, numbers, Chinese fonts and self-defined characters. It supports 3 kinds of bus interface, namely 8 bit/ 4bit and serial. All functions, including display RAM, character generator ROM, LCD display drivers and control circuits are all in a one-chip solution. With a minimum system configuration, a Chinese character display system can easily achieved. ST792 includes character ROM with 892 6X6 dots Chinese fonts and 26 6X8 dots half height alphanumerical fonts. Also for graphic display it supports 64x256 dots graphic display areagdram. Mix mode display with both character and graphic data is possible. ST792 has built in 4 sets CGRAM providing software programmable 6X6 font. ST792 has wide operating voltage (2.7V to 5.5V) and low power consumption suitable for battery power portable device. ST792 LCD driver consists of 32 common and 64 segments. Together with extension segment driver ST792, ST792 can support up to 32 common x 256 segments display. Product ST792-A ST792-B ST792-C Font type BIG-5 code traditional character set GB code simplified character set GB code,big-5 code and Japanese code V3.3 /42 24/3/29

2 ST792 ST792 Specification Revision History Version Date Description C.7 2/2/5 C.8 2/3/. VCC changed to VDD. 2. VLCD changed from VCC-V5 to V-VSS. 3. DC characteristics input High voltage (Vih) changed to.7vdd. 4. DC characteristics output High voltage (Voh) changed to.8vdd.. Chip Size changed. 2. ICON 256 dots changed to 24 dots. 3. XOFF normal high sleep Low changed to normal low sleep High. 4. Added XOFF application. 5. Modified application of ST792 4,5,6 PIN floating. (4,5,6 test pin) 6. Modified voltage doubler CAPP, CAPM, CAP2M capacitors polarity C.9 2/5/28 C2. 2/7/3. Icon RAM TABLE changed. (TABLE-6) 2. Booster description modified. (PAGE-29) 3. AC Characteristics modified. 4. Added 2Line 6 Chinese Word (32Com X 256Seg) application circuit. 5. Added oscillation resistor s relation to power consumption and frequency.. Added Register initial values. 2. Voltage booster CAPM CAPP polarity changed. (PAGE-3) V2. 2/8/7. Modified Table 7. (PAGE-4) 2. Change to English version. V2.c 2//8. Modified page-38 Serial interface timing diagram V2.d 22/5/9. Add the standard code (JapanGB codebig-5 code) V3. 22//. Delete sleep mode function V3. 23/4/. Modified GDRAM Address (AC5 AC, h 3Fh) V3.2 23/9/9.Add the CGROM and HCGROM test application circuit V3.3 24/3/29.Updat the using method for ICON. V3.3 2/5 24/3/29

3 ST792 System Block diagram PSB Reset Circuit RESI RESO CL CL2 M CLK Timing Generator DOUT RS RW E DB4 to DB7 DB to DB3 MPU Interface Input/ Output Buffer Instruction Register (IR) Instruction Decoder Data Register (DR) Address Counter Display Data RAM (DDRAM) 6 x 6 bits 64-bit shift register 33/49- bit shift register 64-bit latch circuit Common Signal Driver Segment Signal Driver LCD Drive Voltage Selector COM to COM32 SEG to SEG64 Busy Flag Graphic RAM (GRAM) 24 x 6 bits Half size Character ROM (HCGROM) 24x6 bits Character Generator RAM (CGRAM) 24 bits Character Generator ROM (CGROM) 2M bits Cursor Blink Scroll Controller Vss Parallel/Serial converter and Attribute Circuit VDD XRESET V V V2 V3 V4 XOFF V3.3 3/5 24/3/29

4 ST792 Pads diagram 3 3 ST ST792 (,) origin: center of chip coordinates: from pad center chip size: 535 X 474 Pad open: 9 X 9 Pad pitch: 25 unit: m * chip substrate must connect to VSS V3.3 4/5 24/3/29

5 ST792 Pin coordinates unit: um V3.3 5/5 24/3/29

6 ST792 V3.3 6/5 24/3/29

7 ST792 Pin Description Name No. I/O Connects to Function XRESET I System reset low active PSB 23 I Interface selection: : serial mode : 8/4-bits parallel bus mode RS(CS*) 7 I MPU Register select : select instruction write, busy flag read, address counter read : select data write, read (Chip select) for serial mode : chip enable : chip disable RW(SID*) 8 I MPU Read write control : write : read (serial data input) E(SCLK*) 9 I MPU Enable trigger (serial clock) D4 to D7 283 I/O MPU Higher nibble data bus for 8 bit interface and data bus for 4 bit interface D to D I/O MPU Lower nibble data bus for 8 bit interface CL 2 O Extension segment drv. Latch signal for extension segment drivers CL2 3 O Extension segment drv. Shift clock for extension segment drivers M 5 O Extension segment drv. AC signal for extension segment drivers voltage inversion DOUT 6 O Extension segment drv. Data output for extension segment drivers COM to COM32 47 O LCD Common signals SEG to SEG O LCD Segment signals V to V4 3 LCD bias voltage 7,8 V - V4 7 V VDD,4 I Power VDD : 2.7V to 5.5V Vss 9,2 I Power VSS: V OSC, OSC2 2,22 I, O Resistors For internal oscillation resistor 5.V R=33K 2.7V R=8K use OSC for external clock input VOUT 33 O Resistors LCD voltage doubler output *note: The OSC pin must have the shortest wiring pattern of all other pins.to prevent noise from other signal lines, it should also be enclosed with the largest GND pattern possible. Poor noise characteristics on the OSC line will result in malfunction, or adversely affect the clock s duty ratio. V3.3 7/5 24/3/29

8 ST792 Pin description Name No. I/O Connects to Description CAP3M CAPP CAPM CAP2M I/O Capacitors Capacitor pins for voltage doubler XOFF 32 O Reserved (no connection) CAP2P 37 Reserved (no connection) VD2 39 I Reference voltage Voltage doubler reference voltage N.C. N.C. N.C I Test pins (no connection) Note:. VDD>=V>=V>=V2>=V3>=V4 must be maintained 2. Two clock options: 3.When using voltage doubler for VOUT it is recommended that the total sum of bleeder resistors R~R5 should be larger than 2K Ohm R=33K (VDD=5.V) R=8K (VDD=2.7V) OSC OSC2 OSC OSC2 R Clock external resistor & Frequency (VDD=5V) V3.3 8/5 24/3/29

9 ST792 Voltage doubler Vss reference voltage CapM CapP VD2 Vout x Cap2M Cap2P Cap3M Vout Vout VD2 Reference voltage Unit: V Doubler voltage mode VD2 & Vout output characteristic Notes: Follower loading resistor total 2k(ohm) Boostaer Cap use 4.7uf Panel size 8mm * 28mm (check display) V3.3 9/5 24/3/29

10 ST792 Function Description : System interface ST792 supports 3 kinds of bus interface to MPU. 8 bits parallel, 4 bits parallel and clock synchronized serial interface. Parallel interface is selected by PSB= and serial interface by PSB=. 8 bit / 4 bit interface is selected by function set instruction DL bit. Two 8 bit registers (data register DR, instruction register IR) are used in ST792 s write and read operation. Data RegisterDRcan access DDRAM/CGRAM/GDRAM and IRAM s data through the address pointer implemented by Address Counter (AC). Instruction Register (IR) stores the instruction by MPU to ST modes of read/write operation specified by RS and RW RS RW Description L L MPU write instruction to instruction registerir L H MPU read busy flagbfand address counterac H L MPU write data to data registerdr H H MPU read data from data registerdr Busy FlagBF Internal operation is in progress when BF=, ST792 is in busy state. No new instruction will be accepted until BF=. MPU must check BF to determine whether the internal operation is finished and new instruction can be sent. Address counterac Address counterac is used for address pointer of DDRAM/CGRAM/IRAM/GDRAM. (AC) can be set by instruction and after data read or write to the memories (AC) will increase or decrease by according to the setting in entry mode set. When RS= and RW=and E= the value ofacwill output to DB6DB. 6x6 character generation ROM (CGROM) and 8x6 half height ROMHCGROM ST792 provides character generation ROM supporting x 6 character fonts and 26 8 x 6 alphanumeric characters. It is easy to support multi languages application such as Chinese and English. Two consecutive bytes are used to specify one 6x6 character or two 8x6 half-height characters. Character codes are written into DDRAM and the corresponding fonts are mapped from CGROM or HCGROM to the display drivers. Character generation RAM (CGRAM) ST792 provides RAM to support user-defined fonts. Four sets of 6x6 bit map area are available. These user-defined fonts are displayed the same ways as CGROM fonts through writing character cod data to DDRAM. V3.3 /5 24/3/29

11 ST792 Display data RAMDDRAM There are 64x2 bytes for display data RAM area. Can store display data for 6 characters(6x6) by 4 lines or 32 characters(8x6) by 4 lines. However, only 2 lines can be displayed at a time. Character codes stored in DDRAM point to the fonts specified by CGROMHCGROM and CGRAM. ST792 display half height HCGROM fonts, user-defined CGRAM fonts and full 6x6 CGROM fonts. Data codes H6H are for CGRAM user-defined fonts. Data codes 2H7FH are for half height alpha numeric fonts. Data codesa4d75fare for BIG5 code and (AAF7FF) are for GB code.. display HCGROM fontswrite 2 bytes data to DDRAM to display two 8x6 fonts. Each byte represents character font. The data of each byte is 2H7FH. 2. display CGRAM fontswrite 2 bytes data to DDRAM to display one 6x6 font. Only H2H 4H6H are allowed. 3. display CGROM fontswrite 2 bytes data to DDRAM to display one 6x6 font. A4HD75FH are for (BIG5) code, AAHF7FFH are for (GB) code. Higher byted5d8are written first and then lower byted7d. Refer to Table 5 for address map CGRAM fonts and CGROM fonts can only be displayed in the start position of each address. (Refer totable 4) A 8B 8C 8D 8E 8F H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L S i t r o n i x S T ( )... Incorrect position Table 4 V3.3 /5 24/3/29

12 ST792 Graphic RAMGDRAM Graphic display RAM supports 64x256 bits bit-mapped memory space. GDRAM address is set by writing 2 consecutive bytes for vertical address and horizontal address. Two-bytes data write to GDRAM for one address. Address counter will automatically increase by one for the next two-byte data. The procedure is as followings.. Set vertical addressyfor GDRAM 2. Set horizontal addressxfor GDRAM 3. Write D5D8 to GDRAM (first byte) 4. Write D7D to GDRAM (second byte) Graphic display memory map please refer to Table-8 LCD driver LCD driver have 33 common and 64 segments to drive the LCD panel. Segment data from CGRAM /CGROM /HCGROM are shifted into the 64 bits segment latches to display. Extended segment driver ST792 can be used to extend the segment drivers to 256. V3.3 2/5 24/3/29

13 ST792 DDRAM data (char. code) B B B B5~ B4 3 2 B B 5 X X X X CGRAM Addr. B B B B CGRAM data CGRAM data (higher byte) (lower byte) B D D D D D D D D D D D D D D D D Table 5DDRAM datacharacter code CGRAM data / address map Note. DDRAM data (character code) bit and bit2 are the same as CGRAM address bit4 and bit5. 2. CGRAM address bit to bit3 specify total 6 rows. Row6 is for cursor display. The data in row 6 will be logical OR to the cursor. 3. CGRAM data for each address is 6 bits. 4. DDRAM data to select CGRAM bit4 to bit5 must be. Bit and bit3 value are don t care. V3.3 3/5 24/3/29

14 ST792 Table 6 6x8 half-height characters V3.3 4/5 24/3/29

15 ST b5 b4 b3 b Table 7 GDRAM display coordinates and corresponding address V3.3 5/5 24/3/29

16 ST792 Instructions Instruction set : (RE=: basic instruction) code Ins RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB CLEAR Description Fill DDRAM with "2H", and set DDRAM address counter ACto "H" Exec time (54KHZ).6 ms HOME X Set DDRAM address counteracto "H", and put cursor to origin the content of DDRAM are not changed 72us ENTRY MODE DISPLAY ON/OFF CURSOR DISPLAY CONTROL FUNCTION SET SET CGRAM ADDR. SET DDRAM ADDR. I/D S D C B S/C R/L X X DL X RE X X Set cursor position and display shift when doing write or read operation D=: display ON C=: cursor ON B=: blink ON Cursor position and display shift control the content of DDRAM are not changed DL= 8-BIT interface DL= 4-BIT interface RE=: extended instruction RE=: basic instruction Set CGRAM address to address counterac AC5 AC4 AC3 AC2 AC AC Make sure that in extended instruction SR= (scroll or RAM address select) AC6 AC5 AC4 AC3 AC2 AC AC Set DDRAM address to address counterac AC6 is fixed to READ BUSY FLAGBF Read busy flagbffor completion of internal operation, also BF AC6 AC5 AC4 AC3 AC2 AC AC Read out the value of address counterac & ADDR. WRITE RAM READ RAM D7 D6 D5 D4 D3 D2 D D D7 D6 D5 D4 D3 D2 D D Write data to internal RAM (DDRAM/CGRAM/GDRAM) Read data from internal RAM (DDRAM/CGRAM/GDRAM) 72us 72 us 72 us 72 us 72 us 72 us us 72 us 72 us V3.3 6/5 24/3/29

17 ST792 Instruction set 2: (RE=: extended instruction) code Inst. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB STAND BY SCROLL or RAM ADDR. SELECT SR REVERSE R R EXTENDED FUNCTION SET SET IRAM or SCROLL ADDR SET GRAPHIC RAM ADDR. DL X RE G description Enter stand by mode, any other instruction can terminate (Com..32 halted) SR=: enable vertical scroll position SR=: enable CGRAM address(basic instruction) Select out of 4 line ( in DDRAM) and decide whether to reverse the display by toggling this instruction R,R initial value is DL= 8-BIT interface DL= 4-BIT interface RE=: extended instruction set RE=: basic instruction set G= :graphic display ON G= :graphic display OFF Exec. time (54KHZ) AC5 AC4 AC3 AC2 AC AC SR=: AC5~AC the address of vertical scroll 72 us Set GDRAM address to address counterac First set vertical address and the horizontal address by AC3 AC2 AC AC consecutive writing AC5 AC4 AC3 AC2 AC AC Vertical address range AC5...AC Horizontal address range AC3 AC 72 us 72 us 72 us 72 us 72 us Note. Make sure that ST792 is not in busy state by reading the busy flag before sending instruction or data. If use delay loop instead please make sure the delay time is enough. Please refer to the instruction execution time. 2. REis the selection bit of basic and extended instruction set. Each time when altering the value of RE it will remain. There is no need to set RE every time when using the same group of instruction set. V3.3 7/5 24/3/29

18 ST792 Initial setting(register flag) (RE=: basic instruction) code Inst. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Description ENTRY I/D S MODE SET Cursor move to right,ddram address counteracplus DISPLAY STATUS D C B Display, cursor and blink ALL OFF CURSOR DISPLAY S/C R/L X X SHIFT X X No cursor or display shift operation FUNCTION SET DL X RE X X 8 BIT MPU interface, basic instruction set Initial setting(register flag) (RE=: extended instruction set) code Inst. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB SCROLL OR RAM ADDR. SELECT SR description Allow IRAMaddress or set CGRAM address REVERSE R R Begin with normal and toggle to reverse EXTENDED DL X RE FUNCTION G SET Graphic display OFF V3.3 8/5 24/3/29

19 ST792 Description of basic instruction set CLEAR RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code Fill DDRAM with "2H"(space code). And set DDRAM address counter AC to"h". Set entry mode I/D bit to be "". Cursor moves right and AC adds after write or read operation. HOME RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code x Set DDRAM address counteracto "H". Cursor moves to origin. Then content of DDRAM is not changed. ENTRY MODE SET RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code I/D S Set the cursor movement and display shift direction when doing write or read operation. I/D :address counter increase / decrease When I/D = "", cursor moves right, DRAM address counteracadd by. When I/D = "", cursor moves left, DRAM address counteracsubtract by. S: Display shift S I/D DESCRIPTION H H Entire display shift left by H L Entire display shift right by V3.3 9/5 24/3/29

20 ST792 DISPLAY STATUS RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code D C B Controls display, cursor and blink ON/OFF. D : Display ON/OFF control bit When D = "", display ON When D = "",display OFF, the content of DDRAM is not changed C : Cursor ON/OFF control bit When C = "", cursor ON. When C = "", cursor OFF. B : Blink ON/OFF control bit When B = "", cursor position blink ON. Then display data in cursor position will blink. When B = "", cursor position blink OFF CURSOR AND DISPLAY SHIFT CONTROL RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code S/C R/L x x Instruction to move the cursor or shift the entire display. The content of DDRAM is not changed. S/C R/L Description AC Value L L Cursor moves left by AC=AC- L H Cursor moves right by AC=AC+ H L Display shift left by, cursor also follows to shift. AC=AC H H Display shift right by, cursor also follows to shift. AC=AC V3.3 2/5 24/3/29

21 ST792 FUNCTION SET RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code DL X RE x x DL : 4/8 BIT interface control bit When DL = "", 8 BIT MPU bus interface When DL = "", 4 BIT MPU bus interface RE : extended instruction set control bit When RE = "", extended instruction set When RE = "", basic instruction set In same instruction cannot alter DL and RE at once. Make sure that change DL first then RE. SET CGRAM ADDRESS RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB AC5 AC4 AC3 AC2 AC AC Code Set CGRAM address to address counterac AC range is H..3FH Make sure that in extended instruction SR= (scroll address or RAM address select) SET DDRAM ADDRESS RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB AC6 AC5 AC4 AC3 AC2 AC AC Code Set DDRAM address to address counterac. First line AC range is 8H..8FH Second line AC range is 9H..9FH Third line AC range is AH..AFH Fourth line AC range is BH..BFH Please note that only 2 lines can be display at a time. READ BUSY FLAGBFAND ADDRESS RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB BF AC6 AC5 AC4 AC3 AC2 AC AC Code Read busy flagbfcan check whether internal operation is finished. At the same time the value of address counter V3.3 2/5 24/3/29

22 ST792 ACis also read. When BF = new instruction will not be accepted. Must wait for BF = for new instruction. WRITE DATA TO RAM RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code D7 D6 D5 D4 D3 D2 D D Write data to internal RAM and alter the (AC) by Each RAM address (CGRAM,DDRAM,IRAM..) must write 2 consecutive bytes for 6 bit data. After the second byte the address counter will add or subtract by according to the entry mode set control bit. READ RAM DATA RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code D7 D6 D5 D4 D3 D2 D D Read data from internal RAM and alter the (AC) by After address set to read (CGRAM,DDRAM,IRAM..)a DUMMY READ is required. There is no need to DUMMY READ for the following bytes unless a new address set instruction is issued. V3.3 22/5 24/3/29

23 ST792 Description of extended instruction set STAND BY RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code Instruction to enter stand by mode. Any other instruction follows this instruction can terminate stand by. The content of DDRAM remain the same. VERTICAL SCROLL OR RAM ADDRESS SELECT RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code SR When SR = "", the vertical scroll address set is enabled. When SR = "", the IRAM address set (extended instruction) and CGRAM address set(basic instruction) is enabled. REVERSE RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code R R Select out of 4 lines to reverse the display and to toggle the reverse condition by repeating this instruction. R,R initial vale is. When set the first time the display is reversed and set the second time the display become normal. R R Description L L First line normal or reverse L H Second line normal or reverse H L Third line normal or reverse H H Fourth line normal or reverse Please note that only 2 lines out of 4 line display data can be displayed. V3.3 23/5 24/3/29

24 ST792 EXTENED FUNCTION SET RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code DL x RE G x DL : 4/8 BIT interface control bit When DL = "", 8 BIT MPU interface When DL = "", 4 BIT MPU interface RE : extended instruction set control bit When RE = "", extended instruction set When RE = "", basic instruction set G : Graphic display control bit When G = "", graphic display ON When G = "", Graphic display OFF In same instruction cannot alter DL, RE and G at once. Make sure that change DL or G first and then RE. SET SCROLL ADDRESS RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB AC5 AC4 AC3 AC2 Code SR=: AC5~AC is vertical scroll displacement address SET GRAPHIC RAM ADDRESS AC AC RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB AC5 AC4 AC3 AC2 AC AC Code Set GDRAM address to address counterac. First set vertical address and then horizontal address(write 2 consecutive bytes to complete vertical and horizontal address set) Vertical address range is AC5...AC Horizontal address range is AC3 AC The address counteracof graphic RAM(GRAM) only increment after write for horizontal address. After horizontal address =FH it will automatically back to H. However, the vertical address will not increase as the result of the same action. V3.3 24/5 24/3/29

25 ST792 Parallel interface : ST792 is in parallel mode by pulling up PSB pin. And can select 8 bit or 4-bit bus interface by function set instruction DL control bit. MPU can control ( RS, RW, E, and DB..DB7 ) pins to complete the data transmission. In 4-bit transfer mode, every 8 bits data or instruction is separated into 2 parts. Higher 4 bitsdb7~db4data will transfer First and placed into data pinsdb7~db4. Lower 4 bitsdb3~dbdata will transfer second and placed into data pins DB7~DB4. (DB3~DB) data pins are not used. RS R/W E DB-DB7 Instruction Dummy RAM Timing Diagram of 8-bit Parallel Bus Mode Data Transfer RS R/W E DB-DB7 Upper Low Upper Low Upper Low 4-bit 4-bit 4-bit 4-bit 4-bit 4-bit Instruction Dummy RAM Timing Diagram of 4-bit Parallel Bus Mode Data Transfer V3.3 25/5 24/3/29

26 ST792 Serial interface : ST792 is in serial interface mode when pull down PSB pin. Two pins (SCLK and SID) are used to complete the data transfer. Only write data is available. When connecting several ST792, chip selectcs must be used. Only whencs is high the serial clocksclk can be accepted. On the other hand, when chip selectcsis low ST792 serial counter and data will be reset. Transmission will be terminated and data will be cleared. Serial transfer counter is set to the first bit. For a minimal system with only one ST792 and one MPU, only SCLK and SID pins are necessary. CS pin should pull to high. ST792 s serial clocksclk is asynchronous to the internal clock and is generated by MPU. When multiple instruction/data is transferred instruction execution time must be considered. Must wait for the previous instruction to finish before sending the next. ST792 has no internal instruction buffer area. When starting a transmission a start byte is required. It consists of 5 consecutive sync character. Serial transfer counter will be reset and synchronized. Following 2 bits for read/writerw and register/data selectrs. Last 4 bits is filled by After receiving the sync character and RW and RS bits, every 8 bits instruction/data will be separated into 2 groups. Higher 4 bitsdb7~db4will be placed in first section followed by 4. And lower 4 bitsdb3~dbwill be placed in second section followed by 4. CS SCLK SID RW RS D7 D6 D5 D4 D3 D2 D D Synchronizing Bit string Higher data Lower data st byte 2 nd byte Timing Diagram of Serial Mode Data Transfer V3.3 26/5 24/3/29

27 ST demo program for serial interface ; ; Write data from A into INSTRUCTION Register ; WRINS: SETB CS SETB SID ; SID = CLR SID ; SID = MOVBIT SID, A.7 ; SID = A.7 MOVBIT SID, A.6 ; SID = A.6 MOVBIT SID, A.5 ; SID = A.5 MOVBIT SID, A.4 ; SID = A.4 CLR SID ; SID = MOVBIT SID, A.3 ; SID = A.3 MOVBIT SID, A.2 ; SID = A.2 MOVBIT SID, A. ; SID = A. MOVBIT SID, A. ; SID = A. CLR SID ; SID = CLR CS CALL DLY8 RET V3.3 27/5 24/3/29

28 ST792 ; ; Write data from A into DATA Register ; WRDATA: SETB CS SETB SID ; SID = CLR SID ; SID = SETB SID ; SID = CLR SID ; SID = MOVBIT SID, A.7 ; SID = A.7 MOVBIT SID, A.6 ; SID = A.6 MOVBIT SID, A.5 ; SID = A.5 MOVBIT SID, A.4 ; SID = A.4 CLR SID ; SID = MOVBIT SID, A.3 ; SID = A.3 MOVBIT SID, A.2 ; SID = A.2 MOVBIT SID, A. ; SID = A. MOVBIT SID, A. ; SID = A. CLR SID ; SID = CLR CS CALL DLY8 RET V3.3 28/5 24/3/29

29 ST792 Application circuit for testing CGROM and HCGROM: We can use the function of CHECK SUM to check the CGROM is right or error. See the following notes: Useing IC Pad (Pin4CLK, Pin5TT, Pin6TT2) to do the CHECK SUM function. The application circuit is at Page49. Timing Diagram for checking CGROM (TT=, TT2=) The ST792 check sum process: In the first place: Resetting the internal counter (set TT and TT2 to Height) In the second place: Setting CGROM mode (set TT to Low, TT2 to Height). In the third place: CLK starts to count times. In the final place: Finishing the counting, read the last four bytes to CHECK SUM (reading only when the CLK is Height). ST792 check sum circuit: Data is available when CLK is height; if CLK is low then the data is always FFH. The last four bytes are Y, Y, Y2, and Y3. The table below is a comparing table of CGROM for different versions. Version (Font) CGROM Last four bytes Y Y Y2 Y3 Big5 (A) CC F 2 GB (B) 9D C FD 6F B5 85 V3.3 29/5 24/3/29

30 ST792 Timing Diagram for checking HCGROM (TT=, TT2=) The ST792 check sum process: In the first place: Resetting the internal counter (set TT and TT2 to Height) In the second place: Setting CGROM mode (set TT to Height, TT2 to Low). In the third place: CLK starts to count 24 times. In the final place: Finishing the counting, read the last four bytes to CHECK SUM (reading only when the CLK is Height). ST792 check sum circuit: Data is available when CLK is height; if CLK is low then the data is always FFH. The last four bytes are Y, Y, Y2, and Y3. The table below is a comparing table of HCGROM for different versions. Version HCGROM last four bytes (Font) Y Y Y2 Y3 Big5 (A) B5 B5 2 GB (B) B5 B5 3 C B5 B5 V3.3 3/5 24/3/29

31 ST792 Testing Step:. Composing TT and TT2 to make the Reset action, and clear the internal counter. 2. Selecting the test mode by setting TT and TT2 (CGROM or HCGROM). 3. After setp and setp2, entering some impulse signals through Pin4 (CLK). 4. Reading the CHECK SUM data through D to D7. 5. Comparing CHECK SUM with the Code Table (upper table) to check if the data is correct or not. TT TT2 No. of counts Status -- RESET CGROM 24 HGROM Test process flow: V3.3 3/5 24/3/29

32 ST792 V3.3 32/5 24/3/29 85 CGROMHCGROM illustrative test program

33 ST792 V3.3 33/5 24/3/29

34 ST792 V3.3 34/5 24/3/29

35 ST792 8 bit interface POWER ON Wait time >4ms XRESET LOW HIGH Function set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB X X X Wait time >us Function set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB X X X Wait time >37uS Display ON/OFF control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB D C B Wait time >us Display clear RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB Wait time >ms Entry mode set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB I/D S Initialization end V3.3 35/5 24/3/29

36 ST792 4 bit interface Function set POWER ON Wait time >4ms XRESET LOW HIGH RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB X X X X Function set Wait time >us RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB X X X X X X X X X X X Wait time >us Display ON/OFF control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB X X X X D C B X X X X Display clear Wait time >us RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB X X X X X X X X Wait time >ms Entry mode set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB X X X X I/D S X X X X Initialization end V3.3 36/5 24/3/29

37 ST792 Built in voltage booster Vout Vss VDD 5.4V CapM CapP VD2 VD2 2.7V x Cap2M Cap2P Vout Cap3M Vout Vss External reset timing VDD Tres XRESET Trw XRESET pulse width Trw us RESET start time Tres 5ns V3.3 37/5 24/3/29

38 ST792 LCD driving wave form (/33 duty, /5 bias ) When oscillation frequency is 54KHZ, clock cycle time =.85us frame =.85us x 3 x 33 = 835us=8.3ms 3 clocks COM V V V2 V3 V4 VSS COM2 V V V2 V3 V4 VSS COM33 V V V2 V3 V4 VSS SEGx off V V V2 V3 V4 VSS SEGx on V V V2 V3 V4 VSS frame V3.3 38/5 24/3/29

39 ST792 Absolute Maximum Ratings Characteristics Symbol Value Power Supply Voltage V DD -.3V to +5.5V LCD Driver Voltage V LCD -.3V to +7.V Input Voltage V IN -.3V to V DD +.3V Operating Temperature T A -2 o C to + 85 o C Storage Temperature T STO -55 o C to + 25 o C DC Characteristics ( T A = 25 o C, V DD = 2.7 V 4.5 V ) Symbol Characteristics Test Condition Min. Typ. Max. Unit V DD Operating Voltage V V LCD LCD Voltage V-V SS V I CC Power Supply Current f OSC = 53KHz, V DD =3.V Rf=8K ma V IH V IL V IH2 V IL2 V OH V OL V OH2 V OL2 Input High Voltage (Except OSC) -.7V DD - V DD V Input Low Voltage V (Except OSC) Input High Voltage - V DD - V DD V (OSC) Input Low Voltage V (OSC) Output High Voltage I OH = -.ma.8v DD - V DD V (DB - DB7) Output Low Voltage I OL =.ma - -. V (DB - DB7) Output High Voltage I OH = -.4mA.8V DD - V DD V (Except DB - DB7) Output Low Voltage I OL =.4mA - -.V DD V (Except DB - DB7) I LEAK Input Leakage Current V IN = V to V DD - - µa I PUP Pull Up MOS Current V DD = 3V µa V3.3 39/5 24/3/29

40 ST792 DC Characteristics ( T A = 25 o C, V DD = 4.5 V V ) Symbol Characteristics Test Condition Min. Typ. Max. Unit V DD Operating Voltage V V LCD LCD Voltage V-V SS V I CC Power Supply Current f OSC = 54KHz, V DD =5V Rf=33K ma V IH V IL V IH2 V IL2 V OH V OL V OH2 V OL2 Input High Voltage (Except OSC) -.7V DD - V DD V Input Low Voltage V (Except OSC) Input High Voltage - V DD - - V DD V (OSC) Input Low Voltage V (OSC) Output High Voltage I OH = -.ma.8v DD - V DD V (DB - DB7) Output Low Voltage I OL =.ma V (DB - DB7) Output High Voltage I OH = -.4mA.8V DD - V DD V (Except DB - DB7) Output Low Voltage I OL =.4mA - -.V DD V (Except DB - DB7) I LEAK Input Leakage Current V IN = V to V DD - - µa I PUP Pull Up MOS Current V DD = 5V µa V3.3 4/5 24/3/29

41 ST792 AC Characteristics (T A = 25 o C, V DD = 4.5V) Parallel Mode Interface Symbol Characteristics Test Condition Min. Typ. Max. Unit Internal Clock Operation f OSC OSC Frequency R = 33KΩ KHz External Clock Operation f EX External Frequency KHz Duty Cycle % T R,T F Rise/Fall Time µs Write Mode (Writing data from MPU to ST792) T C Enable Cycle Time Pin E ns T PW Enable Pulse Width Pin E ns T R,T F Enable Rise/Fall Time Pin E ns T AS Address Setup Time Pins: RS,RW,E - - ns T AH Address Hold Time Pins: RS,RW,E ns T DSW Data Setup Time Pins: DB - DB ns T H Data Hold Time Pins: DB - DB ns Read Mode (Reading Data from ST792 to MPU) T C Enable Cycle Time Pin E ns T PW Enable Pulse Width Pin E ns T R,T F Enable Rise/Fall Time Pin E ns T AS Address Setup Time Pins: RS,RW,E - - ns T AH Address Hold Time Pins: RS,RW,E ns T DDR Data Delay Time Pins: DB - DB7 - - ns T H Data Hold Time Pins: DB - DB ns Interface Mode with LCD Driver(ST792) T CWH Clock Pulse with High Pins: CL, CL ns T CWL Clock Pulse with Low Pins: CL, CL ns T CST Clock Setup Time Pins: CL, CL ns T SU Data Setup Time Pin: D ns T DH Data Hold Time Pin: D ns T DM M Delay Time Pin: M - - ns V3.3 4/5 24/3/29

42 ST792 AC Characteristics (T A = 25 o C, V DD = 2.7V) Parallel Mode Interface Symbol Characteristics Test Condition Min. Typ. Max. Unit Internal Clock Operation f OSC OSC Frequency R = 8KΩ KHz External Clock Operation f EX External Frequency KHz Duty Cycle % T R,T F Rise/Fall Time µs Write Mode (Writing data from MPU to ST792) T C Enable Cycle Time Pin E ns T PW Enable Pulse Width Pin E ns T R,T F Enable Rise/Fall Time Pin E ns T AS Address Setup Time Pins: RS,RW,E - - ns T AH Address Hold Time Pins: RS,RW,E ns T DSW Data Setup Time Pins: DB - DB ns T H Data Hold Time Pins: DB - DB ns Read Mode (Reading Data from ST792 to MPU) T C Enable Cycle Time Pin E ns T PW Enable Pulse Width Pin E ns T R,T F Enable Rise/Fall Time Pin E ns T AS Address Setup Time Pins: RS,RW,E - - ns T AH Address Hold Time Pins: RS,RW,E ns T DDR Data Delay Time Pins: DB - DB ns T H Data Hold Time Pins: DB - DB ns Interface Mode with LCD Driver(ST792) T CWH Clock Pulse with High Pins: CL, CL ns T CWL Clock Pulse with Low Pins: CL, CL ns T CST Clock Setup Time Pins: CL, CL ns T SU Data Setup Time Pin: D ns T DH Data Hold Time Pin: D ns T DM M Delay Time Pin: M - - ns V3.3 42/5 24/3/29

43 ST792 8 bit interface timing diagram MPU write data to ST792 RS VIH VIL TAS TAH R/W TPW TAH E DB-DB7 TR TDSW TH TC MPU read data from ST792 RS R/W E DB-DB7 VIH VIL TR TAS TDDR TPW TAH TAH TH TC V3.3 43/5 24/3/29

44 ST792 AC Characteristics (T A = 25 o C, V DD = 4.5V) Serial Mode Interface Symbol Characteristics Test Condition Min. Typ. Max. Unit Internal Clock Operation f OSC OSC Frequency R = 33KΩ KHz External Clock Operation f EX External Frequency KHz Duty Cycle % T R,T F Rise/Fall Time µs TSCYC Serial clock cycle Pin E ns TSHW SCLK high pulse width Pin E ns TSLW SCLK low pulse width Pin E ns TSDS SID data setup time Pins RW ns TSDH SID data hold time Pins RW ns TCSS CS setup time Pins RS ns TCSH CS hold time Pins RS ns AC Characteristics (T A = 25 o C, V DD = 2.7V) Serial Mode Interface Symbol Characteristics Test Condition Min. Typ. Max. Unit Internal Clock Operation f OSC OSC Frequency R = 8KΩ KHz External Clock Operation f EX External Frequency KHz Duty Cycle % T R,T F Rise/Fall Time µs TSCYC Serial clock cycle Pin E ns TSHW SCLK high pulse width Pin E ns TSLW SCLK low pulse width Pin E ns TSDS SID data setup time Pins RW ns TSDH SID data hold time Pins RW ns TCSS CS setup time Pins RS ns TCSH CS hold time Pins RS ns V3.3 44/5 24/3/29

45 ST792 Serial interface timing diagram MPU write data to ST792 CS SCLK SID V3.3 45/5 24/3/29

46 ST792 I/O pin diagram Input PAD: E (No Pull-up) Input PAD: RS, RW(with Pull-up) Output PAD: CL, CL2, M, D Enable DATA I/O PAD: DB DB7 V3.3 46/5 24/3/29

47 ST792 V3.3 47/5 24/3/29 LCD 32 COM x 6 SEG LCD Voltage VCC A B C D D C B A Title Number Revision Size B Date: -Mar-2 Sheet of File: D:\Buffer-2\792V.DDB Drawn By: V V 2 V2 3 VXA 4 VXB 5 VXC 6 V3 7 V4 8 VSS 9 VDD XRESET CL 2 CL2 3 VDD 4 M 5 DOUT 6 RS 7 RW 8 E 9 VSS 2 OSC 2 OSC2 22 PSB 23 D 24 D 25 D2 26 D3 27 D4 28 D5 29 D6 3 D7 3 XOFF 32 VOUT 33 CAP3M 34 CAPP 35 CAPM 36 CAP2P 37 CAP2M 38 VD2 39 C 4 C2 4 C3 42 C4 43 C5 44 C6 45 C7 46 C8 47 C9 48 C 49 C 5 C2 5 C3 52 C4 53 C5 54 C6 55 C7 56 C8 57 C9 58 C2 59 C2 6 C22 6 C23 62 C24 63 C25 64 C26 65 C27 66 C28 67 C29 68 C3 69 C3 7 C32 7 C33 72 S64 73 S63 74 S62 75 S6 76 S6 77 S59 78 S58 79 S57 8 S56 8 S55 82 S54 83 S53 84 S52 85 S5 86 S5 87 S49 88 S48 89 S47 9 S46 9 S45 92 S44 93 S43 94 S42 95 S4 96 S4 97 S39 98 S38 99 S37 S36 S35 2 S34 3 S33 4 S32 5 S3 6 S3 7 S29 8 S28 9 S27 S26 S25 2 S24 3 S23 4 S22 5 S2 6 S2 7 S9 8 S8 9 S7 2 S6 2 S5 22 S4 23 S3 24 S2 25 S 26 S 27 S9 28 S8 29 S7 3 S6 3 S5 32 S4 33 S3 34 S2 35 S 36 U ST792 S5 S5 2 S52 3 S53 4 S54 5 S55 6 S56 7 S57 8 S58 9 S59 S6 S6 2 S62 3 S63 4 S64 5 S65 6 S66 7 S67 8 S68 9 S69 2 S7 2 S7 22 S72 23 S73 24 S74 25 S75 26 S76 27 S77 28 S78 29 S79 3 S8 3 S8 32 S82 33 S83 34 S84 35 S85 36 S86 37 S87 38 S88 39 S89 4 S9 4 S9 42 S92 43 S93 44 S94 45 S95 46 S96 47 S48 48 S47 49 S46 5 S45 5 S44 52 S43 53 S42 54 S4 55 S4 56 S39 57 S38 58 S37 59 S36 6 S35 6 S34 62 S33 63 S32 64 S3 65 S3 66 S29 67 S28 68 S27 69 S26 7 S25 7 S24 72 S23 73 S22 74 S2 75 S2 76 S9 77 S8 78 S7 79 S6 8 S5 8 S4 82 S3 83 S2 84 S 85 S 86 S9 87 S8 88 S7 89 S6 9 S5 9 S4 92 S3 93 S2 94 S 95 V 96 V2 97 V3 98 VSS 99 VDD CL SHL 2 SHL2 3 CL2 4 DL 5 DR 6 DL2 7 DR2 8 M 9 S49 U2 ST792 C8 C7 2 C6 3 C5 4 C4 5 C3 6 C2 7 C 8 S 9 S2 S3 S4 2 S5 3 S6 4 S7 5 S8 6 S9 7 S 8 S 9 S2 2 S3 2 S4 22 S5 23 S6 24 S7 25 S8 26 S9 27 S2 28 S4 29 S42 3 S43 3 S44 32 S45 33 S46 34 S47 35 S48 36 S49 37 S5 38 S5 39 S52 4 S53 4 S54 42 S55 43 S56 44 S57 45 S58 46 S59 47 S6 48 S8 49 S82 5 S83 5 S84 52 S85 53 S86 54 S87 55 S88 56 S89 57 S9 58 S9 59 S92 6 S93 6 S94 62 S95 63 S96 64 S97 65 S98 66 S99 67 S 68 S2 69 S22 7 S23 7 S24 72 S25 73 S26 74 S27 75 S28 76 S29 77 S3 78 S3 79 S32 8 S33 8 S34 82 S35 83 S36 84 S37 85 S38 86 S39 87 S4 88 C7 89 C8 9 C9 9 C2 92 C2 93 C22 94 C23 95 C24 96 C9 97 C 98 C 99 C2 C3 C4 2 C5 3 C6 4 S2 5 S22 6 S23 7 S24 8 S25 9 S26 S27 S28 2 S29 3 S3 4 S3 5 S32 6 S33 7 S34 8 S35 9 S36 2 S37 2 S38 22 S39 23 S4 24 S6 25 S62 26 S63 27 S64 28 S65 29 S66 3 S67 3 S68 32 S69 33 S7 34 S7 35 S72 36 S73 37 S74 38 S75 39 S76 4 S77 4 S78 42 S79 43 S8 44 S 45 S2 46 S3 47 S4 48 S5 49 S6 5 S7 5 S8 52 S9 53 S 54 S 55 S2 56 S3 57 S4 58 S5 59 S6 6 S7 6 S8 62 S9 63 S2 64 S4 65 S42 66 S43 67 S44 68 S45 69 S46 7 S47 7 S48 72 S49 73 S5 74 S5 75 S52 76 S53 77 S54 78 S55 79 S56 8 S57 8 S58 82 S59 83 S6 84 C32 85 C3 86 C3 87 C29 88 C28 89 C27 9 C26 9 C25 92 L WDG63P C JP HEADER 6 2 JA CON2 2 JK CON2 2 3 J CON3 R 4.7K R2 4.7K R3 2.2K R4 4.7K R5 4.7K R6 33K R7 2K R9 33 R8 33 VCC VCC VCC VCC 2 JP2 HEADER 2 VCC VCC C C2 C3 C4 C5 C6 C7 C8 C9 C C C2 C3 C4 C5 C6 C7 C8 C9 C2 C2 C22 C23 C24 C25 C26 C27 C28 C29 C3 C3 C32 S39 S4 S4 S42 S43 S44 S45 S46 S47 S48 S49 S5 S5 S52 S53 S54 S55 S56 S57 S58 S59 S6 S6 S62 S63 S64 S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 S34 S35 S36 S37 S38 S65 S66 S67 S68 S69 S7 S7 S72 S73 S74 S75 S76 S77 S78 S79 S8 S8 S82 S83 S84 S85 S86 S87 S88 S89 S9 S9 S92 S93 S94 S95 S96 S97 S98 S99 S S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 S34 S35 S36 S37 S38 S39 S4 S4 S42 S43 S44 S45 S46 S47 S48 S49 S5 S5 S52 S53 S54 S55 S56 S57 S58 S59 S6 C25 C26 C27 C28 C29 C3 C3 C32 C C2 C3 C4 C5 C6 C7 C8 C9 C C C2 C3 C4 C5 C6 C7 C8 C9 C2 C2 C22 C23 C24 S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 S34 S35 S36 S37 S38 S39 S4 S4 S42 S43 S44 S45 S46 S47 S48 S49 S5 S5 S52 S53 S54 S55 S56 S57 S58 S59 S6 S6 S62 S63 S64 S65 S66 S67 S68 S69 S7 S7 S72 S73 S74 S75 S76 S77 S78 S79 S8 S8 S82 S83 S84 S85 S86 S87 S88 S89 S9 S9 S92 S93 S94 S95 S96 S97 S98 S99 S S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 S34 S35 S36 S37 S38 S39 S4 S4 S42 S43 S44 S45 S46 S47 S48 S49 S5 S5 S52 S53 S54 S55 S56 S57 S58 S59 S6 Paul Yung.2 Sitronix ST792 LCM R K

48 ST792 V3.3 48/5 24/3/29 LCD 32 COM x 6 SEG LCD Voltage VCC x 2Voltage doubler is used*vlcd should not over 7v A B C D D C B A Title Number Revision Size B Date: 7-Aug-2 Sheet of File: D:\adom\Documents\sch\792_B~3.DDB Drawn By: V V 2 V2 3 VXA 4 VXB 5 VXC 6 V3 7 V4 8 VSS 9 VDD XRESET CL 2 CL2 3 VDD 4 M 5 DOUT 6 RS 7 RW 8 E 9 VSS 2 OSC 2 OSC2 22 PSB 23 D 24 D 25 D2 26 D3 27 D4 28 D5 29 D6 3 D7 3 XOFF 32 VOUT 33 CAP3M 34 CAPP 35 CAPM 36 CAP2P 37 CAP2M 38 VD2 39 C 4 C2 4 C3 42 C4 43 C5 44 C6 45 C7 46 C8 47 C9 48 C 49 C 5 C2 5 C3 52 C4 53 C5 54 C6 55 C7 56 C8 57 C9 58 C2 59 C2 6 C22 6 C23 62 C24 63 C25 64 C26 65 C27 66 C28 67 C29 68 C3 69 C3 7 C32 7 C33 72 S64 73 S63 74 S62 75 S6 76 S6 77 S59 78 S58 79 S57 8 S56 8 S55 82 S54 83 S53 84 S52 85 S5 86 S5 87 S49 88 S48 89 S47 9 S46 9 S45 92 S44 93 S43 94 S42 95 S4 96 S4 97 S39 98 S38 99 S37 S36 S35 2 S34 3 S33 4 S32 5 S3 6 S3 7 S29 8 S28 9 S27 S26 S25 2 S24 3 S23 4 S22 5 S2 6 S2 7 S9 8 S8 9 S7 2 S6 2 S5 22 S4 23 S3 24 S2 25 S 26 S 27 S9 28 S8 29 S7 3 S6 3 S5 32 S4 33 S3 34 S2 35 S 36 U ST792 S5 S5 2 S52 3 S53 4 S54 5 S55 6 S56 7 S57 8 S58 9 S59 S6 S6 2 S62 3 S63 4 S64 5 S65 6 S66 7 S67 8 S68 9 S69 2 S7 2 S7 22 S72 23 S73 24 S74 25 S75 26 S76 27 S77 28 S78 29 S79 3 S8 3 S8 32 S82 33 S83 34 S84 35 S85 36 S86 37 S87 38 S88 39 S89 4 S9 4 S9 42 S92 43 S93 44 S94 45 S95 46 S96 47 S48 48 S47 49 S46 5 S45 5 S44 52 S43 53 S42 54 S4 55 S4 56 S39 57 S38 58 S37 59 S36 6 S35 6 S34 62 S33 63 S32 64 S3 65 S3 66 S29 67 S28 68 S27 69 S26 7 S25 7 S24 72 S23 73 S22 74 S2 75 S2 76 S9 77 S8 78 S7 79 S6 8 S5 8 S4 82 S3 83 S2 84 S 85 S 86 S9 87 S8 88 S7 89 S6 9 S5 9 S4 92 S3 93 S2 94 S 95 V 96 V2 97 V3 98 VSS 99 VDD CL SHL 2 SHL2 3 CL2 4 DL 5 DR 6 DL2 7 DR2 8 M 9 S49 U2 ST792 C8 C7 2 C6 3 C5 4 C4 5 C3 6 C2 7 C 8 S 9 S2 S3 S4 2 S5 3 S6 4 S7 5 S8 6 S9 7 S 8 S 9 S2 2 S3 2 S4 22 S5 23 S6 24 S7 25 S8 26 S9 27 S2 28 S4 29 S42 3 S43 3 S44 32 S45 33 S46 34 S47 35 S48 36 S49 37 S5 38 S5 39 S52 4 S53 4 S54 42 S55 43 S56 44 S57 45 S58 46 S59 47 S6 48 S8 49 S82 5 S83 5 S84 52 S85 53 S86 54 S87 55 S88 56 S89 57 S9 58 S9 59 S92 6 S93 6 S94 62 S95 63 S96 64 S97 65 S98 66 S99 67 S 68 S2 69 S22 7 S23 7 S24 72 S25 73 S26 74 S27 75 S28 76 S29 77 S3 78 S3 79 S32 8 S33 8 S34 82 S35 83 S36 84 S37 85 S38 86 S39 87 S4 88 C7 89 C8 9 C9 9 C2 92 C2 93 C22 94 C23 95 C24 96 C9 97 C 98 C 99 C2 C3 C4 2 C5 3 C6 4 S2 5 S22 6 S23 7 S24 8 S25 9 S26 S27 S28 2 S29 3 S3 4 S3 5 S32 6 S33 7 S34 8 S35 9 S36 2 S37 2 S38 22 S39 23 S4 24 S6 25 S62 26 S63 27 S64 28 S65 29 S66 3 S67 3 S68 32 S69 33 S7 34 S7 35 S72 36 S73 37 S74 38 S75 39 S76 4 S77 4 S78 42 S79 43 S8 44 S 45 S2 46 S3 47 S4 48 S5 49 S6 5 S7 5 S8 52 S9 53 S 54 S 55 S2 56 S3 57 S4 58 S5 59 S6 6 S7 6 S8 62 S9 63 S2 64 S4 65 S42 66 S43 67 S44 68 S45 69 S46 7 S47 7 S48 72 S49 73 S5 74 S5 75 S52 76 S53 77 S54 78 S55 79 S56 8 S57 8 S58 82 S59 83 S6 84 C32 85 C3 86 C3 87 C29 88 C28 89 C27 9 C26 9 C25 92 L WDG63P + C3 4.7u + C2 4.7u C JP HEADER 6 2 JA CON2 2 JK CON2 2 3 J CON3 R 4.7K R2 4.7K R3 2.2K R4 4.7K R5 4.7K R6 33K R7 2K R9 33 R8 33 VCC VCC VCC 2 JP2 HEADER 2 VCC VCC C C2 C3 C4 C5 C6 C7 C8 C9 C C C2 C3 C4 C5 C6 C7 C8 C9 C2 C2 C22 C23 C24 C25 C26 C27 C28 C29 C3 C3 C32 S39 S4 S4 S42 S43 S44 S45 S46 S47 S48 S49 S5 S5 S52 S53 S54 S55 S56 S57 S58 S59 S6 S6 S62 S63 S64 S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 S34 S35 S36 S37 S38 S65 S66 S67 S68 S69 S7 S7 S72 S73 S74 S75 S76 S77 S78 S79 S8 S8 S82 S83 S84 S85 S86 S87 S88 S89 S9 S9 S92 S93 S94 S95 S96 S97 S98 S99 S S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 S34 S35 S36 S37 S38 S39 S4 S4 S42 S43 S44 S45 S46 S47 S48 S49 S5 S5 S52 S53 S54 S55 S56 S57 S58 S59 S6 C25 C26 C27 C28 C29 C3 C3 C32 C C2 C3 C4 C5 C6 C7 C8 C9 C C C2 C3 C4 C5 C6 C7 C8 C9 C2 C2 C22 C23 C24 S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 S34 S35 S36 S37 S38 S39 S4 S4 S42 S43 S44 S45 S46 S47 S48 S49 S5 S5 S52 S53 S54 S55 S56 S57 S58 S59 S6 S6 S62 S63 S64 S65 S66 S67 S68 S69 S7 S7 S72 S73 S74 S75 S76 S77 S78 S79 S8 S8 S82 S83 S84 S85 S86 S87 S88 S89 S9 S9 S92 S93 S94 S95 S96 S97 S98 S99 S S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 S34 S35 S36 S37 S38 S39 S4 S4 S42 S43 S44 S45 S46 S47 S48 S49 S5 S5 S52 S53 S54 S55 S56 S57 S58 S59 S6 Paul Yang.4 Sitronix ST792 LCM (Booster) R K

49 ST792 LCD 2Line 6Chinese Word (32 COM x 256 SEG) V3.3 49/5 24/3/29

50 ST792 LCD 2Line 2 Chinese Word (32 COM x 244 SEG) +4 ICON (USE4 SEG and COM) EX V3.3 5/5 24/3/29

51 ST792 V3.3 5/5 24/3/29