3D & Advanced Packaging

Transcription

1 Tuesday, October 03, 2017 Company Overview March 12, 2015

2 3D & ADVANCED PACKAGING IS NOW WITHIN REACH

3 WHAT IS NEXT LEVEL INTEGRATION? Next Level Integration blends high density packaging with advanced interconnect to quickly deliver miniaturized solutions Next Level Integration Semiconductor Level Integration System Level Integration Going forward, ISI believes that packaging technology will play as big a role as transistor evolution in advancing Moore s Law

4 DEVELOPING IC PACKAGES SINCE 1987 KEY MILESTONES 1993 Developed 557 I/O PPGA for 48 Watt GaAs die 2001 Invested in equipment & clean room to provide IC assembly services 2010 Significantly increased 3D & stacked die capabilities

5 IC PACKAGING 101 Die Attach & Wire Bond Flip Chip & Underfill ISI designs multi-die modules utilizing both Wire Bond and Flip Chip die.

6 PACKAGING TECHNOLOGIES 3D Die Stacking Multiple processes qualified Utilize standard die - no TSVs (through silicon vias) required Examples:

7 PACKAGING TECHNOLOGIES Thermoset Overmolding Multiple packaged ICs, bare die, and passive components can be molded into single, monolithic component Thermoset epoxy is same type of material used in standard BGA and QFP packages Does not melt or soften during subsequent reflow processes Ultra-fine particle size can underfill BGAs and flip chips and also provide wirebond encapsulation Ideal for rugged environments Cross-Section

8 PACKAGING TECHNOLOGIES 3D Substrate Stacking ISI designs and manufactures high-density z-axis interconnect to facilitate stacking of thin substrates 0.4mm pitch and above (area array) Precision dimensions / thin walls minimize keep-out area Substrate Stacking Stacked Substrates using Bare Die Stacked Substrates using Packaged Devices

9 ADVANCED PACKAGING EXAMPLES System in Package 45x45mm BGA 2 Flip Chip Die 3 Wire Bond Die 2 Packaged ICs Multiple Passives mm.5 10mm 45 x 45 mm (1.77 x 1.77 ) Final assembly is a BGA package with heat spreader

10 ADVANCED PACKAGING EXAMPLES Atom + DDR3 Module 40x45mm BGA (1) Intel Atom Processor (9) SDRAM DDR3L x8 (x72 bank) Integrated Heat Spreader Overmolded for High Reliability applications mm.5 10mm 40 x 45 mm (1.57 x 1.77 ) Final assembly is a BGA package with heat spreader

11 ADVANCED PACKAGING EXAMPLES System in Package (SiP) 4 Die Stack: Processor DDR Flash ADC VR Die & Passives HiLo Connector for Stacking mm.5 10mm 22 x 22 mm (.86 x.86 ) 22x22mm Module Shown prior to encapsulation

12 ISI FC512 CONFIGURATOR BGA Package 13x13mm body size 9 die module 224 balls 0.8mm pitch 13x13mm BGA 27-Up Array 9-Up Array

13 ADVANCED PACKAGING EXAMPLES Micro FPGA Compute Node Flip Chip FPGA Die (2) Multi-Die DDR3 packages Power management Card Edge Interface mm.5 10mm 21 x 29 mm (.82 x 1.14 )

14 ADVANCED PACKAGING EXAMPLES 32 Node Compute Cluster Each Micro FPGA Compute Node is enclosed in a heat spreader 32 nodes are inserted into water-cooled Master Module Master Module interfaces to system board through custom 2368 pin ISI HiLo socketing system

15 ADVANCED PACKAGING EXAMPLES Chip on Flex 3 wire bond die Passives Embedded in smart credit card mm.5 10mm 32.3 x 28.2 mm (1.27 x 1.11 ) 22 x 23 mm (.86 x.90 ) Chip on Rigid-Flex Dual die design Flex portion allows 90 orientation of sensors

16 ADVANCED PACKAGING EXAMPLES High Density Memory Module 5 DDR3 Die Long wirebonds to reach center-of-die pads mm.5 10mm 32 x 25 mm (1.25 x.98 )

17 ADVANCED PACKAGING EXAMPLES Liquid Crystal on Silicon (LCoS) Package Large LCoS die (30mm+) Precise mechanical tolerances to provide alignment to optical system Very flat heatsink (+/ ) to prevent image distortion Material set Engineered to be stable over operating temp range High volume cost-sensitive application mm.5 10mm 61.6 x 67.3 mm (2.42 x 2.64 )

18 ADVANCED PACKAGING EXAMPLES Multi Die Module 9 die in module smaller than credit card Less than 20% of the size of discrete component design mm.5 10mm 55 x 39 mm (2.16 x 1.53 )

19 HIGH-DENSITY MEMORY SOLUTIONS Five-Chip Memory Module Bumped substrate is wirebonded to memory die to make CSP building block Three CSP building blocks are embedded in the base The top substrate has BGA pads allowing for placement of two additional packaged memories Unique memory solution using die and packaged devices The bottom side of module has BGA spheres for assembly to the board BGA Package in Package (PiP) and Package on Package (PoP) Flash Stacks PoP PiP with embedded BGA Two High Four High Doubles SDRAM density in same PCB footprint Up to 4X Density

20 3D DDR3 MODULE Customer s Challenge Customer required high density compute nodes for HPC application ISI s Solution Placed overmolded 3D-DIMM modules on bottom side of PCB, directly under the FPGA Eliminated 14 layers on customer PCB by mapping 3D-DIMM module pin-out directly to FPGA pins, connect by though-hole via Lower profile design increased airflow, and allowed compute nodes to be stacked together on a tighter pitch Freed up massive real estate Improved signal integrity by dramatically reducing trace length from FPGA to DDR3 4 memories on bottom of top board 1 memories + register + misc on top of bottom board 4 Memories on Topside of Module Heat spreader can be added to center of module if required Void-free overmold / underfill between module substrates

21 MMCM: MOLDED MULTI-COMPONENT MODULES Complex, multiple components integrated in a single module MMCM Bare or packaged die + passive electronic components overmolded with thermoset epoxy 3D Stacked BGA module and x-ray Ideal for miniaturized, rugged applications in harsh environments An affordable way to ruggedize electronic modules 3D Stacked BGA module and x-ray Modules can be designed to directly replace obsolete devices 40-pin DIP module and x-ray

22 MULTI COMPONENT PACKAGES 350 BGA MMCM 240 QFP MMCM Top View Top View Internal components include: Modern FPGA in small BGA package Level translators for IO Voltage regulation Decoupling caps, etc. Bottom View

23 40-PIN DIP PACKAGE FOR AVIONICS Customer s Challenge Avionics customer faced obsolescence on part, needed alternative IC package Redesigning avionics main board would mean requalification Due to high temp and vibration requirements, a standard nonovermolded adapter would not be an option ISI s Solution SMT CSP Laminate substrate Overmold encapsulant Etched Leadframe, PDIP40 After in-depth cost analysis, customer determined it would be more cost effective to design an ISI overmolded 40-pin DIP package to replace current IC package The rugged overmolded design consisted of off-the-shelf packaged parts on an FR4 PCB with ISI lead frame pins Non-molded prototypes delivered and tested within 4-6 weeks Molded prototypes met customer qualifications and delivered within 2 weeks after approval ISI solution flexible to meet any of the customer s future redesign issues

24 THANK YOU! Contact ISI to engage on your next project: Address: Phone: Website: 741 Flynn Road / Camarillo, California (805) Dave Gagnon Western USA Office: Cell: (714) (714) dave.gagnon@molex.com» Bob Garon Midwest USA Cell: (630) bob.garon@molex.com» Brian Witzen Eastern USA Cell: (919) brian.witzen@molex.com