ECE 699: Lecture 9. Programmable Logic Memories
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1 ECE 699: Lecture 9 Programmable Logic Memories
2 Recommended reading XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices Chapter 7, HDL Coding Techniques Sections: RAM HDL Coding Techniques ROM HDL Coding Techniques 2
3 Memory Types 3
4 Memory Types Memory ROM RAM Memory Single port Dual port Memory With asynchronous read With synchronous read 4
5 Memory Types specific to Xilinx FPGAs Memory Distributed (MLUT-based) Block RAM-based (BRAM-based) Memory Inferred Instantiated Manually Using Vivado 5
6 Programmable Logic (PL) CLBs and IOBs Source: The Zynq Book
7 Programmable Logic (PL) BRAMs and DSP units Source: The Zynq Book
8 FPGA Distributed Memory
9 Location of Distributed RAM Logic resources (CLB slices) RAM blocks Multipliers DSP units Logic Logic resources blocks Graphics based on The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 9
10 SLICEL 10
11 Fast Carry Logic u u Each SliceL and SliceM contains separate logic and routing for the fast generation of sum & carry signals Increases efficiency and performance of adders, subtractors, accumulators, comparators, and counters Carry logic is independent of normal logic and routing resources MSB LSB Carry Logic Routing 11
12 Accessing Carry Logic u All major synthesis tools can infer carry logic for arithmetic functions Addition (SUM <= A + B) Subtraction (DIFF <= A - B) Comparators (if A < B then ) Counters (count <= count +1) 12
13 ECE 448 FPGA and ASIC Design with VHDL 13
14 SLICEM ECE 448 FPGA and ASIC Design with VHDL 14
15 Xilinx Multipurpose LUT (MLUT) 16-bit 32-bit SR x 1 RAM 4-input 64 x 1 ROM LUT (logic) The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 15
16 Single-port 64 x 1-bit RAM 16
17 Single-port 64 x 1-bit RAM 17
18 Memories Built of Neighboring MLUTs Memories built of 2 MLUTs: Single-port 128 x 1-bit RAM: RAM128x1S Dual-port 64 x 1-bit RAM : RAM64x1D Memories built of 4 MLUTs: Single-port 256 x 1-bit RAM: RAM256x1S Dual-port 128 x 1-bit RAM: RAM128x1D Quad-port 64 x 1-bit RAM: RAM64x1Q Simple-dual-port 64 x 3-bit RAM: RAM64x3SDP (one address for read, one address for write) 18
19 Dual-port 64 x 1 RAM Dual-port 64 x 1-bit RAM : 64x1D Single-port 128 x 1-bit RAM: 128x1S 19
20 Dual-port 64 x 1 RAM Dual-port 64 x 1-bit RAM : 64x1D Single-port 128 x 1-bit RAM: 128x1S 20
21 FPGA Block RAM 21
22 Location of Block RAMs Logic resources (CLB slices) RAM blocks Multipliers DSP units Logic Logic resources blocks Graphics based on The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 22
23 Block RAM Configured as 1 x 36 kbit RAM or 2 x 18 kbit RAMs 23
24 Block RAM Simple Dual Port (SDP) = one port for read, one port for write (write_a-read_b, read_a_write_b) True Dual Port (TDP) = both ports can be used for read or write (read_a-read_b, read_a-write_b, write_a-read_b, write_a-write_b) 24
25 Block RAM can have various configurations (port aspect ratios) k x 2 4k x 4 4,095 16k x 1 8, k x (8+1) 16, x (16+2) 25
26 26
27 27
28 18k Block RAM Port Aspect Ratios 28
29 Block RAM Interface 29
30 Block RAM Ports 30
31 Cascadable Block RAM 31
32 Block RAM Waveforms READ_FIRST mode 32
33 Block RAM Waveforms WRITE_FIRST mode 33
34 Block RAM Waveforms NO_CHANGE mode 34
35 Features of Block RAMs 35
36 Inference vs. Instantiation 36
37 37
38 Generic Inferred ROM 38
39 Distributed ROM with asynchronous read LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; Entity ROM is generic ( w : integer := 12; -- number of bits per ROM word r : integer := 3); -- 2^r = number of words in ROM port (addr : in std_logic_vector(r-1 downto 0); dout : out std_logic_vector(w-1 downto 0)); end ROM; 39
40 Distributed ROM with asynchronous read architecture behavioral of rominfr is type rom_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); constant ROM_array : rom_type := (" ", " ", " ", " ", " ", " ", " ", " "); begin dout <= ROM_array(to_integer(unsigned(addr))); end behavioral; 40
41 Distributed ROM with asynchronous read architecture behavioral of rominfr is type rom_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); constant ROM_array : rom_type := (X"0C4", X"4D2", X"4DB", X"6C2", X"0F1", X"7D6", X"4D0", X"F9F"); begin dout <= ROM_array(to_integer(unsigned(addr))); end behavioral; 41
42 Generic Inferred RAM 42
43 Distributed versus Block RAM Inference Examples: 1. Distributed single-port RAM with asynchronous read 2. Distributed dual-port RAM with asynchronous read 3. Block RAM with synchronous read (no version with asynchronous read!) More excellent RAM examples from XST Coding Guidelines. 43
44 Distributed single-port RAM with asynchronous read LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 6); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr; 44
45 Distributed single-port RAM with asynchronous read architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type := (others => (others => '0')); begin process (clk) begin if rising_edge(clk) then if (we = '1') then RAM(to_integer(unsigned(a))) <= di; end if; end if; end process; do <= RAM(to_integer(unsigned(a))); end behavioral; 45
46 Distributed dual-port RAM with asynchronous read library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 6); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(r-1 downto 0); dpra : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); spo : out std_logic_vector(w-1 downto 0); dpo : out std_logic_vector(w-1 downto 0)); end raminfr; 46
47 Distributed dual-port RAM with asynchronous read architecture syn of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type := (others => (others => '0')); begin process (clk) begin if rising_edge(clk) then if (we = '1') then RAM(to_integer(unsigned(a))) <= di; end if; end if; end process; spo <= RAM(to_integer(unsigned(a))); dpo <= RAM(to_integer(unsigned(dpra))); end syn; 47
48 Block RAM Waveforms READ_FIRST mode 48
49 Block RAM with synchronous read LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 9); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; en : in std_logic; addr : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr; 49
50 Block RAM with synchronous read Read-First Mode - cont'd architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type := (others => (others => '0')); begin process (clk) begin if rising_edge(clk) then if (en = '1') then do <= RAM(to_integer(unsigned(addr))); if (we = '1') then RAM(to_integer(unsigned(addr))) <= di; end if; end if; end if; end process; end behavioral; 50
51 Block RAM Waveforms WRITE_FIRST mode 51
52 Block RAM with synchronous read Write-First Mode - cont'd architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type := (others => (others => '0')); begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(to_integer(unsigned(addr))) <= di; do <= di; else do <= RAM(to_integer(unsigned(addr))); end if; end if; end if; end process; end behavioral; 52
53 Block RAM Waveforms NO_CHANGE mode 53
54 Block RAM with synchronous read No-Change Mode - cont'd architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type := (others => (others => '0')); begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(to_integer(unsigned(addr))) <= di; else do <= RAM(to_integer(unsigned(addr))); end if; end if; end if; end process; end behavioral; 54
55 Criteria for Implementing Inferred RAM in BRAMs 55
56 FIFOs 56
57 FIFO Interface clk rst clk rst FIFO 8 din full dout empty 8 write read ECE 448 FPGA and ASIC Design with VHDL 57
58 Operation of the Standard FIFO A B C D ECE 448 FPGA and ASIC Design with VHDL 58
59 Operation of the First-Word Fall-Through FIFO ECE 448 FPGA and ASIC Design with VHDL 59
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