Field Program mable Gate Arrays

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1 Field Program mable Gate Arrays M andakini Patil E H E P g r o u p D H E P T I F R SERC school NISER, Bhubaneshwar Nov

2 Outline Digital electronics Short history of programmable logic devices The internals of an FPGA Programming techniques Example Applications Design flow

3 What is a Field Programmable Gate Array? A quick answer for the impatient An FPGA is an integrated circuit Mostly digital electronics An FPGA is programmable in the field (=outside the factory), hence the name field programmable Design is specified by schematics or with a language Tools compute a programming file for the FPGA The FPGA is configured with the design Your electronic circuit is ready to use With an FPGA you can build electronic circuits without using a soldering iron without plugging together existing modules without having a chip produced at a factory hardware description

4 Introduction to digital electronics The building AND gate blocks: logic gates Truth table Exclusive OR gate XOR gate C equivalent q = a && b; OR gate q = a b;

5 q = a!= b; Combinatorial logic (asynchronous) Outputs are determined by Inputs, only Example: Full adder with carry-in, carry-out Combinatorial logic may be implemented using Look-Up Tables (LUTs)

6 (Synchronous) sequential logic Outputs are determined by Inputs and their History (Sequence) The logic has an internal state 2-bit binary counter set D Flip-flop: samples the data at the rising (or falling) edge of the clock data clock Output Inverted output

7 Synchronous sequential logic + = Using Look-Up-Tables and Flip-Flops any kind of digital electronics may be implemented

8 Of course there are some details to be learnt about electronics design Programmable digital electronics Long long time ago

9 Ever-decreasing feature size Higher capacity Higher speed Lower power consumption 130 nm Xilinx Virtex-2 28 nm Xilinx Virtex-7 / Altera Stratix V 16 nm Xilinx UltraScale 14 nm Altera Stratix 10 Slowing down 5.5 million logic cells 4 million logic cells

10 Programmable Logic Devices Simple PLDs (splds): PROMs Programmable Read-Only Memory Unprogrammed PROM (Fixed AND Array, Programmable OR Array)

11 Simple PLDs (splds): PLAs Programmable Logic Arrays Programmable AND array Unprogrammed PLA (Programmable AND and OR Arrays) Most flexible

12 but slower Simple PLDs (splds): PALs Programmable Array Logic 1975

13 Unprogrammed PAL (Programmable AND Array, Fixed OR Array) Complex PLDs (CPLDs) Coarse grained 100 s of blocks, restrictive structure and flip-flops

14 FPGAs

15 ASIC You can get started with a $200 development board and free software Rapid development cycle (minutes / hours) May be reprogrammed in the field (firmware upgrade) New features Bug fixes Lower cost per device in a large volume production FPGA Extremely high development cost ASICs are produced at a semiconductor fabrication facility ( fab ) according to your design Long development cycle (weeks / months) Design cannot be changed once it is produced Better radiation hardness Analog designs possible

16 Components in a modern FPGA

17 LUT-based Fabrics Typical LUT-based Logic Cel l

18 Embedded RAM blocks

19 Inside a FPGA Xilinx: logic cell, Altera: logic element Flip-Flop registers the LUT output May use only the LUT or only the Flip-flop LUT may alternatively be configured as a shift register Additional elements (not shown): fast carry logic

20 Digital Signal Processor (DSP) DSP block (Xilinx 7-series) Up to several 1000 per chip

21 Today: Up to several MB of RAM Embedded Multipliers

22 Soft and Hard Processor Cores Clock Trees

23 Clock Managers

24 System-On-a-Chip (SoC) FPGAs Xlinix Zynq Altera Stratix 10 CPU(s) + Peripherals + FPGA in one package

25 Trends Increased capacity and speed (> 1 M logic cells) Look-up-tables with more inputs

26 DIFFERENT FEATURES of FPGA Hard macro cores (Ethernet MAC, Memory interfaces ) Embedded CPUs Sophisticated interfaces (PCI Express, ) Domain-specific devices Ultra-low-power FPGAs Mixed-signal FPGAs

27 ... How FPGA Technology evolved.

28 Design Considerations (SRAM Config.) Used in most FPGAs

29 Fusible Links (not used in FPGAs) Antifuse Technology

30 SRAM-Based Devices

31 EEPROM Technology Erasable Programmable Read Only Memory Intel,1971

32 Major Manufacturers Xilinx First company to produce FPGAs in 1985 About 50% market share, today SRAM based CMOS devices Altera About 30% market share SRAM based CMOS devices Actel Anti-fuse FPGAs Flash based FPGAs Mixed Signal Lattice Semiconductor

33 Hardware Description Language Looks similar to a programming language BUT be aware of the difference Programming Language => translated into machine instructions that are executed by a CPU HDL => translated into gateware (logic gates & flip-flops) Common HDLs VHDL Verilog AHDL ( Altera specific ) Newer trends C-like languages (handle-c, System C) Labview

34 Development Tools

35 Different Steps in Implementation

36 entity DelayLine is! generic (! n_halfcycles : integer := 2);! port (! x : in std_logic_vector;! x_delayed : out std_logic_vector;! clk : in std_logic);! end entity DelayLine; Graphical overview Can draw entire design Can Can generate blocks using loops Can synthesize algorithms also include blocks in hardware Independent of design tool description language. May use tools used in SW development (CVS, ) Mostly a personal choice depending on previous experience Design flow

37 Hardware Description Language

38

39 Configuration at power-up Flash PROM stores single or multiple designs FPGA ( SRAM based ) Serial bit-stream (may be encrypted) Typical FPGA configuration time: milliseconds

40 Programming from a host PC Flash PROM FPGA PCI, VME FPGA ( SRAM based ) JTAG bus... The JTAG bus may be driven by an FPGA which contains an interface to a host PC via PCI or VME Firmware can then be updated from the PC

41 FPGA APPLICATIONS in HEP and Other Domain

42 Why are FPGAs ideal for First-Level Triggers? They are fast Much faster than discrete electronics (shorter connections) Low latency Many parallel inputs Data from many parts of the detector has to be combined Can send parallel data rather than serial All operations are performed in parallel High performance Can build pipelined logic

43 FPGAs in Data Acquisition Frontend Electronics Pedestal subtraction Zero suppression Compression Custom data links E.g. SLINK-64 Several serial LVDS links in parallel Up to 400 MB/s Interface from custom hardware to commercial electronics PCI bus, VME bus, Myrinet, etc. Example 3: CMS Front-end Readout Link

44 Peak finding Pattern Finding Track Finding Energy summing Sorting Topological Algorithms Trigger Control system Fast signal merging Many more Trigger algorithms implemented in FPGAs

45 Example: CMS Global Muon Trigger Input: ~ and 80 MHz Output: ~50 80MHz Processing time: 250 ns Pipelined logic one new result every 25 ns 10 Xilinx Virtex-II FPGAs up to 500 user I/Os per chip Up to LUTs per chip used Up to 96 x 18kbit RAM used The CMS Global Muon trigger receives 16 muon candidates from the three muon systems of CMS It merges different measurements for the same muon and finds the best 4 over-all muon candidates

46 CMS Global Muon Trigger main FPGA

47 Example 4: CMS Readout Link for Run-2 in use 10 Gb/s TCP/IP since 2015 Myrinet NIC replaced by custom-built card ( FEROL ) SLINK-64 input LVDS / copper Cost effective solution (need many boards) Rather inexpensive FPGA + commercial chip to combine 3 Gb/s links to 10 Gb/s FEROL (Front End Readout Optical Link) Input: 1x or 2x SLINK (copper) Output: 10 Gb/s Ethernet optical 1x or 2x 5Gb/s optical TCP/IP sender in FPGA 1x 10Gb/s optical

48 CMS Global Muon Trigger main FPGA

49 bi-color LEDs Example 2: CMS Fast Merging Modules These modules merge the status of all detector front-ends in CMS in order to throttle the trigger when buffers fill up. Additionally these modules monitor all status changes of detector frontends. 1 FPGA (Altera) : PCI interface 1 FPGA (Xilinx) : Merging logic (1 µs latency) Monitoring logic Interface to SRAM

50 SLINK Sender Mezzanine Card: 400 M B / s 1 FPGA (Altera) CRC check Automatic link test Commercial Myrinet Network Interface Card on internal PCI bus Front-end Readout Link Card 1 main FPGA (Altera) 1 FPGA as PCI interface Custom Compact PCI card Receives 1 or 2 SLINK64 2nd CRC check Monitoring, Histogramming Event spy

51 Example 2: New µtca board for CMS trigger upgrade based on Virtex Gb/s 36 x 10 Gb/s Tx Rx Tx Rx MP7, Imperial College Virtex 7 with 690k logic cells 80 x 10 Gb/s transceivers bi-directional 72 of them as optical links on front panel Tb/s Being used in the CMS trigger since 2015 Input/output: up to 14k bits per 40 MHz clock Same board used for different functions (different gateware) Separation of framework + algorithm fw

52 FPGAs in Server Processors and the Cloud New in 2016: Intel Xeon Server Processor with FPGA in socket Intel acquired Altera in 2015 FPGAs in the cloud Amazon Elastic Cloud F1 instances 8 CPUs / 1 Xlinix UltraScale FPGA 64 CPUs / 8 Xlinix UltraScale FPGA

53 FPGAs in other domains Set-top boxes Digital Signal Processing Medical imaging ASIC Prototyping Computer vision Speech recognition Computations performed Cryptography High performance computing by FPGA: FFT, Convolution Bioinformatics Reconfigurable computing Software-Defined Radio Aerospace Defense

54 FPGAs in other domains Medical imaging Advanced Driver Assistance Systems (Image Processing) Speech recognition ASIC Prototyping High performance computing Accelerator cards Cryptography Bioinformatics Aerospace / Defense Bitcoin mining 3 TFlop Server processors w. FPGA

55 You are going to design the digital electronics using this FPGA board!

56 THANK YOU

57 VHDL has roots in the Ada programming language in both concept and syntax, while Verilog's roots can be tracked back to an early HDL called Hilo and the C programming language.

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