Fujitsu Microelectronics Europe Application Note MCU-AN E-V11 FR FAMILY 32-BIT MICROCONTROLLER MB91460 RESET APPLICATION NOTE

Transcription

1 Fujitsu Micrelectrnics Eurpe Applicatin Nte MCU-AN E-V11 FR FAMILY 32-BIT MICROCONTROLLER MB91460 RESET APPLICATION NOTE

2 Revisin Histry Revisin Histry Date V1.0 RSchum First draft V1.1 HPi, Crrected frmatting Issue This dcument cntains 15 pages. MCU-AN E-V Fujitsu Micrelectrnics Eurpe GmbH

3 Warranty and Disclaimer Warranty and Disclaimer T the maximum extent permitted by applicable law, Fujitsu Micrelectrnics Eurpe GmbH restricts its warranties and its liability fr all prducts delivered free f charge (eg. sftware include r header files, applicatin examples, target bards, evaluatin bards, engineering samples f IC s etc.), its perfrmance and any cnsequential damages, n the use f the Prduct in accrdance with (i) the terms f the License Agreement and the Sale and Purchase Agreement under which agreements the Prduct has been delivered, (ii) the technical descriptins and (iii) all accmpanying written materials. In additin, t the maximum extent permitted by applicable law, Fujitsu Micrelectrnics Eurpe GmbH disclaims all warranties and liabilities fr the perfrmance f the Prduct and any cnsequential damages in cases f unauthrised decmpiling and/r reverse engineering and/r disassembling. Nte, all these prducts are intended and must nly be used in an evaluatin labratry envirnment. 1. Fujitsu Micrelectrnics Eurpe GmbH warrants that the Prduct will perfrm substantially in accrdance with the accmpanying written materials fr a perid f 90 days frm the date f receipt by the custmer. Cncerning the hardware cmpnents f the Prduct, Fujitsu Micrelectrnics Eurpe GmbH warrants that the Prduct will be free frm defects in material and wrkmanship under use and service as specified in the accmpanying written materials fr a duratin f 1 year frm the date f receipt by the custmer. 2. Shuld a Prduct turn ut t be defect, Fujitsu Micrelectrnics Eurpe GmbH s entire liability and the custmer s exclusive remedy shall be, at Fujitsu Micrelectrnics Eurpe GmbH s sle discretin, either return f the purchase price and the license fee, r replacement f the Prduct r parts theref, if the Prduct is returned t Fujitsu Micrelectrnics Eurpe GmbH in riginal packing and withut further defects resulting frm the custmer s use r the transprt. Hwever, this warranty is excluded if the defect has resulted frm an accident nt attributable t Fujitsu Micrelectrnics Eurpe GmbH, r abuse r misapplicatin attributable t the custmer r any ther third party nt relating t Fujitsu Micrelectrnics Eurpe GmbH. 3. T the maximum extent permitted by applicable law Fujitsu Micrelectrnics Eurpe GmbH disclaims all ther warranties, whether expressed r implied, in particular, but nt limited t, warranties f merchantability and fitness fr a particular purpse fr which the Prduct is nt designated. 4. T the maximum extent permitted by applicable law, Fujitsu Micrelectrnics Eurpe GmbH s and its suppliers liability is restricted t intentin and grss negligence. NO LIABILITY FOR CONSEQUENTIAL DAMAGES T the maximum extent permitted by applicable law, in n event shall Fujitsu Micrelectrnics Eurpe GmbH and its suppliers be liable fr any damages whatsever (including but withut limitatin, cnsequential and/r indirect damages fr persnal injury, assets f substantial value, lss f prfits, interruptin f business peratin, lss f infrmatin, r any ther mnetary r pecuniary lss) arising frm the use f the Prduct. Shuld ne f the abve stipulatins be r becme invalid and/r unenfrceable, the remaining stipulatins shall stay in full effect Fujitsu Micrelectrnics Eurpe GmbH MCU-AN E-V-11

4 Cntents Cntents REVISION HISTORY... 2 WARRANTY AND DISCLAIMER... 3 CONTENTS INTRODUCTION RESET FLOW AND RESET CAUSES Reset Flw INIT RESET STATE Hw t enter INIT Reset State Releasing the INIT Reset State request Operatins perfrmed in INIT Reset State (INIT reset cancellatin sequence) RST RESET STATE Hw t enter RST Reset State Releasing the RST Reset State request Operatins perfrmed in RST Reset State (RST reset cancellatin sequence) RST Reset Operatin Mdes Nrmal (Asynchrnus) RST Reset Operatin Synchrnus RST Reset Operatin EVALUATION OF THE RESET CAUSE Reset Cause Register RSRR Hardware Watchdg Cntrl Register HWWD HARDWARE STANDBY INPUT HSTX Influence f HSTX/INITX n Oscillatin Stabilizatin Wait Time ADDITIONAL INFORMATION LIST OF FIGURES LIST OF TABLES MCU-AN E-V Fujitsu Micrelectrnics Eurpe GmbH

5 Chapter 1 Intrductin 1 Intrductin This applicatin nte describes the reset flw n MB Depending n reset cause (Pwer ON, external reset pin input, Watchdg reset r sftware reset) the MCUs f MB91460 Series run thrugh tw different reset states: INIT reset state (Settings Initializatin Reset) and RST reset state (Operatin Initializatin Reset). In the fllwing the peratins perfrmed in the tw abve mentined reset states are described and the flw thrugh these states is explained. In additin infrmatin abut hw t determine the reset cause will be given. Fujitsu Micrelectrnics Eurpe GmbH MCU-AN E-V-11

6 Chapter 2 Reset Flw and Reset Causes 2 Reset Flw and Reset Causes This Chapter gives an verview abut the flw thrugh the different reset states and hw these states can be invked. 2.1 Reset Flw Pwer ON 4) INITX pin input (pssible frm any state) INIT Reset State Settings Initializatin HSTX pin input 3) Watchdg Timeut 1) Lw Vlatage Reset RST Reset State Operatin Initializatin Sftware Reset (STCR_SRST) RSTX pin input 2) Nrmal RUN Mde Figure 2-1 Reset Flw 1) When INIT Reset State was entered due t Watchdg Timeut the setting f the scillatin stabilizatin time (STCR_OS[1:0]) are nt changed 2) External RSTX pin is nt supprted by sme f the MB91460 devices 3) External Hardware Standby input pin HSTX is nt supprted by sme f the MB91460 devices. On devices supprting HSTX the setting f the scillatin stabilizatin wait time (STCR_OS[1:0]) depends n the rder f releasing HSTX and INITX pin (fr details please see f this dcument). 4) After pwer n the INITX input pin has t be kept lw until the scillatin f the external scillatr has stabilized. MCU-AN E-V Fujitsu Micrelectrnics Eurpe GmbH

7 Chapter 3 INIT Reset State 3 INIT Reset State INIT Reset is used t initialize settings f the cntrller. In the fllwing a descriptin f the initializatin steps is given. 3.1 Hw t enter INIT Reset State The INIT Reset state is entered by: Pulling INTIX t lw level a) Pulling HSTX t lw level (when supprted by the specific MB91460 Series MCU) Lw Vltage Reset (fr details abut the setup f the Lw Vltage Reset/Interrupt please refer t the Hardware Manual f MB91460 Series) Watchdg Reset generated by Hardware Watchdg (RC scillatr driven) r by Sftware Watchdg (Timebase Timer driven) (fr details abut the tw Watchdg types please refer the Hardware Manual f MB91460 Series) a) At Pwer n the INITX pin must be kept at lw level until the external scillatr is started cmpletely. The scillatr start up time depends n the used scillatr, the circuit (e.g. the lad capacities) and the PCB layut. The start up time has t be evaluated by the custmer and the custmer has t guarantee that the lw level is supplied t the INITX input pin during this scillatr start up time. 3.2 Releasing the INIT Reset State request The INIT Reset state request is released: Supply high level t INITX input pin c) Supply high level t HSTX input pin (when supprted by the specific MB91460 Series MCU) c) In case f Pwer On please keep the scillatr start up time in mind when releasing the INITX input pin t high level (please refer t the abve remark added fr the signal supplied t INITX while scillatr start up at Pwer On). 3.3 Operatins perfrmed in INIT Reset State (INIT reset cancellatin sequence) Cnfiguratin f clck settings t default settings (clck surce is Main Clck, PLL disabled) Oscillatin Stabilizatin time is set t default value (STCR_OS[1:0] = b 00) d) Wait fr scillatin stabilizatin wait time as specified by STCR_OS[1:0] Initialize Reset Cause Register RSRR e) Enter RST Reset State d) Cnfiguratin f the scillatin stabilizatin wait time (STCR_OS[1:0]) t default settings is nt dne when INIT Reset State was entered due t Watchdg reset e) A Watchdg Timeut will nt initialize the Reset Cause Register. Fujitsu Micrelectrnics Eurpe GmbH MCU-AN E-V-11

8 Chapter 4 RST Reset State 4 RST Reset State RST Reset is used t initialize the peratin f the cntrller. In the fllwing a descriptin f the initializatin steps is given. 4.1 Hw t enter RST Reset State Entered frm previus INIT Reset State Apply lw level t RSTX input pin Invking a Sftware Reset by writing 0 t the SRST flag in the STCR register (fr details abut the Standby Cntrl Register STCR please refer t the Hardware Manual f MB91460 Series) 4.2 Releasing the RST Reset State request The RST Reset State request is released when the RST Reset state is entered. 4.3 Operatins perfrmed in RST Reset State (RST reset cancellatin sequence) All MCU peripheral registers will be initialized t default values as described in the Hardware Manual f MB91460 Series. The clck setting registers will nt be changed. Cnfiguratin f IO Prts t default values like all IO prts set t input, glbal prt enable flag is cleared, (fr details refer t the Hardware Manual f MB91460) Evaluatin f the setting f the Mde Pins MD[2:0] and setting up the device perating mde (bus mde and external bus width) crrespndingly. Please find an verview f the device peratin mdes in the Hardware Manual f MB91460 Series. Set up f the CS0 Area t 0x xFFFFFFFF (entire address range) Change t nrmal peratin (RUN) Read Mde Vectr frm address 0x000FFFF8 (depending n the Mde Pin setting and the used MB91460 Series MCU the Mde Vectr address might be in the internal ROM area r in the external ROM area) Write Mde Vectr t Mde Register (MODR) Read Reset Vectr frm address 0x000FFFFC (depending n the Mde Pin setting and the used MB91460 Series MCU the Mde Vectr address might be in the internal ROM area r in the external ROM area). The bus width which is used fr the access t the Reset Vectr is defined by the previusly read Mde Vectr. Write Reset Vectr t PC (Prgram Cunter) and start prgram executin MCU-AN E-V Fujitsu Micrelectrnics Eurpe GmbH

9 Chapter 4 RST Reset State 4.4 RST Reset Operatin Mdes Fr the RST Reset peratin tw mdes are pssible: Nrmal (asynchrnus) Reset Operatin r Synchrnus Reset Operatin. The RST Reset Operatin mde is selected by the SYNCR-flag in the Timebase Timer Cntrl Register TBCR. Figure 4-1 Register TBCR Fr details n the Timebase Timer Cntrl Register TBCR please refer t the Hardware manual f the MB91460 Series Nrmal (Asynchrnus) RST Reset Operatin Nrmal reset peratin refers t the mde when the device ges t the peratin reset (RST) state immediately after an peratin reset (RST) request ccurs. Fr a nrmal reset, the device changes t the reset (RST) state immediately after a reset (RST) request is received regardless f the current state f internal bus access. In nrmal reset mde, the result n any bus peratin that is in prgress at the time the device changes state is nt guaranteed. Hwever, acceptance f the peratin reset (RST) request is guaranteed Synchrnus RST Reset Operatin Synchrnus RST reset peratin refers t the mde when the device des nt g t the peratin reset (RST) state after an peratin reset (RST) request until all bus access has halted. In synchrnus RST reset mde, the device des nt g t the RST reset state when a RST reset request is received if internal bus access is still in prgress. When such a RST reset request is received, a sleep request is issued t the internal bus. The device des nt change t the peratin reset RST state until all buses have shutdwn peratin and changed t SLEEP state. In synchrnus reset mde, the results f bus peratins are guaranteed because the device des nt change state until all bus access has halted. Hwever, if bus access shuld nt halt fr sme reasn, n requests can be received while bus peratin cntinues. In such case, the settings initializatin reset (INIT) remains available at any time. The fllwing lists cases in which bus access may nt stp: - If bus wait is enabled due t cntinuus input f RDY (ready request) t the external expansin bus interface. Fujitsu Micrelectrnics Eurpe GmbH MCU-AN E-V-11

10 Chapter 5 Evaluatin f the Reset Cause 5 Evaluatin f the Reset Cause The Reset Cause Register can be used by an applicatin t keep track f the cause f last reset. 5.1 Reset Cause Register RSRR Figure 5-1 Register RSRR INIT: INIT Reset ccurred due t INITX pin input r Hardware Watchdg Timeut A). HSTB: INIT Reset ccurred due t HSTX pin input. WDOG: INIT Reset ccurred due t Sftware Watchdg Timeut. ERST: RST Reset ccurred due t RSTX pin input. SRST: RST Reset ccurred due t Sftware Reset (STCR_SRST). LINIT: INIT Reset ccurred due t Lw Vltage Reset. A) When the INIT-flag in the RSRR register is set it is necessary t check the Hardware Watchdg cntrl register HWWD als t distinguish between INITX pin input reset and Hardware Watchdg Timeut. Fr details n HWWD please refer t pint 5.2 f this dcument and t the hardware manual f MB91460 Series. The RSRR register is cleared after the first read. Since the RSRR is already evaluated by the BtROM when the MB91460 MCU is started in Single Chip Mde (pins MD[2:0]=b 000) the BtROM will prvide the riginal cntent f RSRR in the CPU register R4 at applicatin start and a cpy f the riginal RSRR cntent can be fund at a device specific RAM address. Fr the RAM address at which the RSRR cntent is stred please refer t the datasheet f the used MB91460 device. Fr details n the Reset Cause Register RSRR please refer t the Hardware manual f the MB91460 Series. MCU-AN E-V Fujitsu Micrelectrnics Eurpe GmbH

11 Chapter 5 Evaluatin f the Reset Cause 5.2 Hardware Watchdg Cntrl Register HWWD Figure 5-2 Register RSRR CPUF: When the last reset ccurred due t a Hardware Watchdg Timeut the CPUFflag in the Hardware Watchdg cntrl register is set while in the RSRR register (please refer t pint 5.1) nly the INIT-flag is set. The CPUF-flag has t be cleared by the applicatin. Fr details n the Hardware Watchdg cntrl register HWWD please refer t the Hardware manual f the MB91460 Series. Fujitsu Micrelectrnics Eurpe GmbH MCU-AN E-V-11

12 Chapter 6 Hardware Standby input HSTX 6 Hardware Standby input HSTX This chapter describes the functin f the Hardware Standby input pin HSTX. Hardware Standby is intended t halt the cmplete MCU including als the external scillatrs. 6.1 Influence f HSTX/INITX n Oscillatin Stabilizatin Wait Time Releasing the Hardware Standby Mde als the signal input t the scillatin stabilizatin wait time STCR_OS[1:0] is cnfigured depending n the state f the INTX input pin: - OS[1:0]=b 00 when INITX input pin is at lw level while releasing HSTX frm lw t high - OS[1:0]=b 11 when INITX input pin is at high level while releasing HSTX frm lw t high Please see the belw table fr the resulting scillatin stabilizatin wait times depending n the setting f STCR_OS[1:0] Table 6-1 STCR: OS bits The Hardware Standby input pin HSTX is nt supprted by sme f the MB91460 devices. MCU-AN E-V Fujitsu Micrelectrnics Eurpe GmbH

13 Chapter 7 Additinal Infrmatin 7 Additinal Infrmatin Infrmatin abut FUJITSU Micrcntrllers can be fund n the fllwing Internet page: Fujitsu Micrelectrnics Eurpe GmbH MCU-AN E-V-11

14 List f Figures List f Figures Figure 2-1 Reset Flw... 6 Figure 4-1 Register TBCR... 9 Figure 5-1 Register RSRR Figure 5-2 Register RSRR MCU-AN E-V Fujitsu Micrelectrnics Eurpe GmbH

15 List f Tables List f Tables Table 6-1 STCR: OS bits Fujitsu Micrelectrnics Eurpe GmbH MCU-AN E-V-11