ECE484 VLSI Digital Circuits Fall Lecture 01: Introduction

Transcription

1 ECE484 VLSI Digital Circuits Fall 2017 Lecture 01: Introduction Adapted from slides provided by Mary Jane Irwin. [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] CSE477 L01 Introduction.1 Irwin&Vijay, PSU, 2002

2 Course Contents Introduction to digital integrated circuits CMOS devices and manufacturing technology. CMOS logic gates and their layout. Propagation delay, noise margins, and power dissipation. Combinational (e.g., arithmetic) and sequential circuit design. Course goals Ability to design and implement CMOS digital circuits and optimize them with respect to different constraints: size (cost), speed, power dissipation, and reliability Course prerequisites ECE 326. Electronic Circuit Design ECE 282. Logic Design of Digital Systems CSE477 L01 Introduction.2 Irwin&Vijay, PSU, 2002

3 Course Administration Instructor: George L. Engel TA: Sri Kandula Labs: Need university account. CSE477 L01 Introduction.3 Irwin&Vijay, PSU, 2002

4 Background from ECE282 and ECE326 Basic circuit theory resistance, capacitance, inductance MOS gate characteristics Hardware description language VHDL or verilog Logic design logical minimization, FSMs, component design CSE477 L01 Introduction.4 Irwin&Vijay, PSU, 2002

5 Transistor Revolution Transistor Bardeen (Bell Labs) in 1947 Bipolar transistor Schockley in 1949 First bipolar digital logic gate Harris in 1956 First monolithic IC Jack Kilby in 1959 First commercial IC logic gates Fairchild 1960 TTL 1962 into the 1990 s ECL 1974 into the 1980 s CSE477 L01 Introduction.5 Irwin&Vijay, PSU, 2002

6 MOSFET Technology MOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935 CMOS 1960 s, but plagued with manufacturing problems PMOS in 1960 s (calculators) NMOS in 1970 s (4004, 8080) for speed CMOS in 1980 s preferred MOSFET technology because of power benefits BiCMOS, Gallium-Arsenide, Silicon-Germanium SOI, Copper-Low K, CSE477 L01 Introduction.6 Irwin&Vijay, PSU, 2002

7 Moore s Law In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 14 months (i.e., grow exponentially with time). Amazingly visionary million transistor/chip barrier was crossed in the 1980 s transistors, 1 MHz clock (Intel 4004) Million transistors (Ultra Sparc III) 42 Million, 2 GHz clock (Intel P4) Million transistor (HP PA-8500) CSE477 L01 Introduction.7 Irwin&Vijay, PSU, 2002

8 Intel 4004 Microprocessor CSE477 L01 Introduction.8 Irwin&Vijay, PSU, 2002

9 Intel Pentium (IV) Microprocessor CSE477 L01 Introduction.9 Irwin&Vijay, PSU, 2002

10 State-of-the Art: Lead Microprocessors CSE477 L01 Introduction.10 Irwin&Vijay, PSU, 2002

11 Transistors (MT) Moore s Law in Microprocessors Transistors on lead microprocessors double every 2 years X growth in 1.96 years! CSE477 L01 Introduction.11 Irwin&Vijay, PSU, P6 Pentium proc Year Courtesy, Intel

12 Kbit capacity/chip Evolution in DRAM Chip Capacity ,000 4, m human memory human DNA 4X growth every 3 years! book 16, m page 64, m 256, m 1,000,000 4,000,000 16,000,000 64,000, Year m m 0.13 m 0.1 m 0.07 m encyclopedia 2 hrs CD audio 30 sec HDTV CSE477 L01 Introduction.12 Irwin&Vijay, PSU, 2002

13 Die size (mm) Die Size Growth 100 Die size grows by 14% to satisfy Moore s Law P6 Pentium proc ~7% growth per year ~2X growth in 10 years Year Courtesy, Intel CSE477 L01 Introduction.13 Irwin&Vijay, PSU, 2002

14 Frequency (Mhz) Clock Frequency Lead microprocessors frequency doubles every 2 years X every 2 years P6 Pentium proc Year Courtesy, Intel CSE477 L01 Introduction.14 Irwin&Vijay, PSU, 2002

15 Power (Watts) Power Dissipation Lead Microprocessors power continues to increase 100 P6 Pentium proc Year Power delivery and dissipation will be prohibitive Courtesy, Intel CSE477 L01 Introduction.15 Irwin&Vijay, PSU, 2002

16 Power Density (W/cm2) Power Density Rocket Nozzle 100 Nuclear Reactor Hot Plate P6 Pentium proc Year Power density too high to keep junctions at low temp Courtesy, Intel CSE477 L01 Introduction.16 Irwin&Vijay, PSU, 2002

17 Design Productivity Trends Logic Transistor per Chip (M) Complexity Productivity (K) Trans./Staff - Mo. 10, ,000 1, Logic Tr./Chip Tr./Staff Month. 10,000 1, %/Yr. compounded Complexity growth rate x x x x x x x x 21%/Yr. compound Productivity growth rate Complexity outpaces design productivity Courtesy, ITRS Roadmap CSE477 L01 Introduction.17 Irwin&Vijay, PSU, 2002

18 Technology Directions: SIA Roadmap Year Feature size (nm) Mtrans/cm Chip size (mm 2 ) Signal pins/chip Clock rate (MHz) Wiring levels Power supply (V) High-perf power (W) Battery power (W) For Cost-Performance MPU (L1 on-chip SRAM cache; 32KB/1999 doubling every two years) CSE477 L01 Introduction.18 Irwin&Vijay, PSU, 2002

19 Why Scaling? Technology shrinks by ~0.7 per generation With every generation can integrate 2x more functions on a chip; chip cost does not increase significantly Cost of a function decreases by 2x But How to design chips with more and more functions? Design engineering population does not double every two years Hence, a need for more efficient design methods Exploit different levels of abstraction CSE477 L01 Introduction.19 Irwin&Vijay, PSU, 2002

20 Design Abstraction Levels SYSTEM + MODULE GATE CIRCUIT V in V out S n+ G DEVICE D n+ CSE477 L01 Introduction.20 Irwin&Vijay, PSU, 2002

21 Major Design Challenges Microscopic issues ultra-high speeds power dissipation and supply rail drop growing importance of interconnect noise, crosstalk reliability, manufacturability clock distribution Macroscopic issues time-to-market design complexity (millions of gates) high levels of abstractions reuse and IP, portability systems on a chip (SoC) tool interoperability Year Tech. Complexity Frequency 3 Yr. Design Staff Size Staff Costs M Tr. 400 MHz 210 $90 M M Tr. 500 MHz 270 $120 M M Tr. 600 MHz 360 $160 M M Tr. 800 MHz 800 $360 M CSE477 L01 Introduction.21 Irwin&Vijay, PSU, 2002