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1 October 2013

2 During this session you will learn about: Kinetis L series portfolio overview Migrating between Kinetis K and L series Low power philosophy Reducing the area under the energy curve The four pillars of low power Ultra efficient Cortex M0+ processor Energy saving architecture Energy saving peripherals Ultra low power modes (including hands on demo) Using the PEx USB stack (hands on lab) ADC Topics Review 2

3 After completing this session you will have: Knowledge of the feature set of the Kinetis L series The ability to describe the migration with the Kinetis K series An understanding of the power saving features of the Kinetis L series MCUs, including, The M0+ core The energy saving architecture Low power modes, including entry and exit strategies The energy saving peripherals The ability to demonstrate low power software showing various low power operating scenarios. Knowledge the USB PEx stack and be able to demonstrate using it. An understanding of ADC parameters and how to achieve them in an application 3

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5 Common Features System ARM Cortex-M0+ Core, 48MHz Multiple low-power modes, Clock Gating, 1.71V - 3.6V Operating Temp: -40 to 105 C [1] Memory 90nm TFS Flash, SRAM Internal Memory Security/Protection Family Flash SRAM Optional Features USB OTG Seg. LCD DMA Cross- Bar Key Features ADC DAC I2S TSI KL KB 16-32KB 16-bit 12-bit KL KB 8-32KB 16-bit 12-bit KL34 64KB 8KB 12-bit Analog Peripherals 12/16-Bit ADC High-Speed Comparators Serial Interfaces KL KB 16-32KB 16-bit 12-bit KL KB 4-16KB 16-bit 12-bit KL KB 4-8KB 12-bit UART (Including 1 LPUART) SPI, IIC Timers Real Time Clock [2] KL KB 4-32KB 16-bit 12-bit KL KB 4-16KB 16-bit 12-bit KL KB 4-8KB 12-bit 16bit Low Power TPMs (GP Timer/PWM) Low Power Timers 32bit Periodic Interrupt Timer KL KB 1-4KB 12-bit 12-bit KL KB 1-4KB 12-bit KL KB 1-4KB 12-bit [1] Feature to be determined on CSP packages [2] For KL02, use software to support 5

6 Flash Memory Flash Memory 256KB USB + Seg. LCD Segment LCD USB General Purpose Entry Level KL4x KL3x KL2x KL1x KL2x KL1x KL4x KL3x KL2x KL4x KL4x 128KB KL2x KL2x KL2x KL3x KL2x KL2x KL3x KL2x KL1x KL1x KL1x KL1x KL1x KL3x KL3x 64KB KL2x KL2x KL2x KL2x KL2x KL1x KL1x KL1x KL1x KL1x 32KB KL2x KL1x KL2x KL1x KL2x KL1x KL2x KL1x KL2x KL1x KL0x KL0x KL0x KL0x 16KB KL0x KL0x KL0x KL0x 8KB KL0x KL0x KL0x <24 pin 24 QFN 32 LQFP/ QFN 35 WLCSP 48 LQFP/QFN 6 Package 64 LQFP / MBGA 80 LQFP 100 LQFP/ 121 MBGA

7 KL02 Block Diagram System Unique ID Clock Management Energy Management ARM Cortex-M0+ Core Ultra-low-power 48MHz bus freq. Debug (SWD) COP RST LPO (1KHz) Crystal Oscillator (low range) LS Osc (32KHz) Voltage Regulator Flash 8-32K RAM 1-4K FLL ULP Osc (4MHz) Power On Reset Low Voltage Detector Peripheral Bus Analog Interfaces Timers Communication I/O Ports ADC (SAR) 12-bit, up to 12ch HSCMP 16b LPTPM 2ch x 2 LPR SPI x 1 I2C x 2 LPUART x 1 Up to 27 GPIO (4High Dive) w/ 12 interrupt RST/ Input Operation in: Run Wait Stop/ VLPS VLLS 3 VLLS 1 VLLS 0 Packages: 16QFN, 20WLCSP, 24QFN, 32QFN 7

8 KL04/05 Family Block Diagram System Unique ID Clock Management Energy Management ARM Cortex-M0+ Core Ultra-low-power 48MHz bus freq. Debug (SWD) COP RST LPO (1KHz) Crystal Oscillator (low & high range) LS Osc (32KHz) Voltage Regulator Flash 8-32K RAM 1-4K DMA 4-ch FLL ULP Osc (4MHz) Power On Reset Low Voltage Detector Peripheral Bus Analog Interfaces Timers Communication I/O Ports ADC (SAR w/ DMA) 12-bit, up to 14ch 12-bit DAC HSCMP PIT 2ch, 32bit RTC 16b LPTPM 6ch x1, 2ch x 1 LPR SPI x 1 I2C x 1 LPUART x 1 TSI x 12ch Up to 41 GPIO (4 High Dive) w/ 18 interrupt RST/ Input Operation in: Run Wait Stop/ VLPS VLLS 3 VLLS 1 VLLS 0 Packages: 24QFN, 32LQFP, 32QFN, 48LQFP 8

9 KL14/15/16 Family Block Diagram System Unique ID Clock Management Energy Management ARM Cortex-M0+ Core Ultra-low-power 48MHz bus freq. Debug (SWD) COP RST LPO (1KHz) Crystal Oscillator (low & high range) LS Osc (32KHz) Voltage Regulator Flash K RAM 4-32K DMA 4-ch FLL PLL ULP Osc (4MHz) Power On Reset Low Voltage Detector Peripheral Bus Analog Interfaces Timers Communication I/O Ports ADC (SAR w/ DMA) 12/16-bit, up to 16ch 12-bit DAC HSCMP PIT 2ch, 32bit RTC 16b LPTPM 6ch x1, 2ch x 2 LPR UART x2 LPUA RTx1 SPI x 2 I2C x 2 IIS x1 TSI x 16ch Up to 70 GPIO (4 High Dive) w/ 23 interrupt RST/ Input Operation in: Run Wait Stop/ VLPS VLLS 3 VLLS 1 VLLS 0 Packages: 32QFN, *35WLCSP, 48QFN, 64LQFP, *64MBGA, 80LQFP * Under Proposal 9

10 KL24/5/6 Family Block Diagram System Unique ID Clock Management Energy Management ARM Cortex-M0+ Core Ultra-low-power 48MHz bus freq. Debug (SWD) COP RST LPO (1KHz) Crystal Oscillator (low & high range) LS Osc (32KHz) Voltage Regulator Flash K RAM 4-32K DMA 4-ch FLL PLL ULP Osc (4MHz) Power On Reset Low Voltage Detector Peripheral Bus Analog Interfaces Timers Communication Connectivity I/O Ports ADC (SAR w/ DMA) 12/16-bit, up to 16ch 12-bit DAC HSCMP PIT 2ch, 32bit RTC 16b LPTPM 6ch x1, 2ch x 2 LPR UART x2 LPUA RTx1 SPI x 2 I2C x 2 IIS x1 USB FS/LS Transceiver USB Controller V Regulator TSI x 16ch Up to 80 GPIO (4 High Dive) w/ 25 interrupt RST/ Input Operation in: Run Wait Stop/ VLPS VLLS 3 VLLS 1 VLLS 0 Packages: 32QFN, 48QFN, 64LQFP, 80LQFP, 100LQFP, 121MBGA 10

11 KL34/36 Family Block Diagram System Unique ID Clock Management Energy Management ARM Cortex-M0+ Core Ultra-low-power 48MHz bus freq. Debug (SWD) COP RST LPO (1KHz) Crystal Oscillator (low & high range) LS Osc (32KHz) Voltage Regulator Flash K RAM 8-32K DMA 4-ch FLL PLL ULP Osc (4MHz) Power On Reset Low Voltage Detector Peripheral Bus Analog Interfaces Timers Communication HMI I/O Ports ADC (SAR w/ DMA) 12/16-bit, up to 16ch 12-bit DAC HSCMP PIT 2ch, 32bit RTC 16b LPTPM 6ch x1, 2ch x 2 LPR UART x2 LPUA RTx1 SPI x 2 I2C x 2 IIS x1 Segment LCD 51x8/55x4 TSI x 16ch Up to 80 GPIO (4 High Dive) w/ 25 interrupt RST/ Input Operation in: Run Wait Stop/ VLPS VLLS 3 VLLS 1 VLLS 0 Packages: 64LQFP, *64MBGA, 100LQFP, 121MBGA * Under Proposal 11

12 KL46 Family Block Diagram System Unique ID Clock Management Energy Management ARM Cortex-M0+ Core Ultra-low-power 48MHz bus freq. Debug (SWD) COP RST LPO (1KHz) Crystal Oscillator (low & high range) LS Osc (32KHz) Voltage Regulator Flash K RAM 16-32K DMA 4-ch FLL PLL ULP Osc (4MHz) Power On Reset Low Voltage Detector Peripheral Bus Analog Interfaces Timers Communication Connectivity I/O Ports ADC (SAR w/ DMA) 12/16-bit, up to 16ch 12-bit DAC HSCMP PIT 2ch, 32bit RTC 16b LPTPM 6ch x1, 2ch x 2 LPR UART x2 LPUA RTx1 SPI x 2 I2C x 2 IIS x1 USB FS/LS Transceiver USB Controller V Regulator TSI x 16ch Up to 80 GPIO (4 High Dive) w/ 25 interrupt RST/ Input Operation in: Run Wait Stop/ VLPS VLLS 3 VLLS 1 VLLS 0 HMI Segment LCD 51x8/55x4 Packages: 64LQFP, *64MBGA, 100LQFP, 121MBGA * Under Proposal 12

13 HSCMP ADC DAC/ADC HSCMP GPIO etc. SWD TSI GPIO etc Digital Power HSCMP ADC VREFOUT Clock (32K) Vbat SWD JTAG TSI GPIO etc Digital Power ADC GPIO etc LLWU GPIO ADC GPIO etc LLWU GPIO Digital Power USB ADC DP Ch GPIO etc. Analog Power 48 KL25 48-pin ADC/TSI GPIO etc. Reset GPIO Clock GPIO etc Fully Hardware Compatible Follow Same Pin Assignment Rule Same Peripheral Register Setting for common features Digital Power USB ADC DP Ch Analog Power MHz K20 48-pin ADC/TSI GPIO etc. Reset GPIO Clock (3~32M) GPIO etc Software Compatible, C-Code Reusable Take 3 Steps for easy Migration: Step 1 Check Hardware difference Power Pin (Vbat) External Clock Input (32KHz/3~32MHz) Analog interface (DAC, Vref_Out) Debug Interface (JTAG) GPIO pinmux Step 2 Check Software difference DMA configuration Watchdog Service Routine Low Power usecase (New features added on L series) BME (new on L series) MTB (new on L series) GPIO Map (More on L series) Flexmemory (K series only) Step 3 Optimize the Design Adopt new header file and reuse the C code by modifying the difference Add new features support in design that specific to L series or K series 13

14 Feature 50 MHz K20 KL25Z Hardware Characteristics Package 32-pin QFN (5x5mm) 32-pin QFN (5x5mm not pinto-pin compatible to K20) 48-pin QFN (7x7mm) 48-pin QFN (7x7mm) 48-pin LQFP (7x7mm) 64-pin LQFN (9x9mm) 64-LQFP (10x10mm) 64-LQFP (10x10mm) 80-LQFP (12x12mm) System Central processing unit (CPU) ARM Cortex M4 ARM Cortex M0+ Max. CPU frequency 50 MHz 48 MHz Max. Bus frequency 50 MHz 24 MHz Digital signal processor (DSP) Yes No Nested vectored interrupt controller (NVIC) 45 channels 32 channels (interrupt assignments are different between K20D and KL25Z) Wake-up interrupt controller (WIC) FSL WIC & LLWU FSL WIC is the same. LLWU lite (reduces LLWU external wakeup sources to 8 maintaining pin-to-pin compatible location) 14

15 Feature 50 MHz K20 KL25Z System Direct memory access (DMA) 4 channels (Kinetis DMA2) 4 channels (ColdFire+ DMA) DMA request multiplex Yes Same (maintains compatible multiplex assignments) Bit manipulation engine (BME) No Yes Single-cycle IOPORT No Yes Software watchdog (WDOG) Yes ColdFire+ COP Hardware watchdog (EWM) Yes No Low-leakage wake-up unit (LLWU) Power Modes 16 external wake-up pins with digital filter 8 external wake-up pins with digital and 6 internal wake-up sources filter and 5 internal wake-up sources RUN RUN (adds Compute Only clock option) WAIT WAIT VLPR VLPR (adds Compute Only clock option) VLPW VLPW STOP STOP (adds Partial STOP 1 & 2 w/ Asynchronous DMA Wakeup support) VLPS VLPS LLS LLS VLLS3,2,1,0 VLLS3,1,0 (no VLLS2) 15

16 Feature 50 MHz K20 KL25Z System Debug 2-pin serial wire debug (SWD) 2-pin serial wire debug (SWD) IEEE Joint Test Access Group (JTAG) IEEE compact JTAG (cjtag) Trace Trace Port Interface Unit (TPIU) Data Watchpoint and Trace (DWT) Flash Patch and Breakpoint (FPB) Breakpoint and Patch Unit (BPU) reduced to 2 BKPTs and 2 WPTs Data Watchpoint and Trace (DWT) Micro Trace Buffer (MTB) with additional trigger event logic allows trace capabilities from trigger events captured into user selected system RAM Instrumentation Trace Macrocell (I) Boundary scan Yes No Unique Identification (ID) Number 128-bit wide 80-bit wide Reset pin Dedicated Programmable using FOPT 16

17 Feature 50 MHz K20 KL25Z Memory Flash memory Up to 128 KB P-Flash, up to 32KB D-Flash (32- bit wide) Up to 128 KB P-Flash, no D-Flash (32- bit wide) Flash cache 32 bytes 64 bytes Random-access memory (RAM) Up to 16KB (2x 8KB cuts) straddled at 0x2000_0000 with ½ on SRAML and ½ on SRAMU Up to 16KB (1x 16KB cuts) straddled at 0x2000_0000 with 12KB as SRAM_U and 4KB as SRAML. FlexMemory Yes No Low-leakage standby memory up to 8 KB in VLLS2 mode VLLS2 not supported 32 Register File Bytes in VLLS1 mode Register File not supported Cyclic redundancy check (CRC) 32-bit CRC with programmable generator polyn No Serial factory programming interface (EzPort) Yes No Clocks External square wave input clock DC to 50 MHz DC to 48 MHz Phase-locked loop (PLL) Up to 100 MHz VCO Up to 96 MHz VCO Frequency-locked loop (FLL) Range 1: MHz Range 1: MHz Range 2: MHz Range 2: MHz Range 3: MHz Range 3: Not supported Range 4: MHz Range 4: Not supported 17

18 Feature 50 MHz K20 KL25Z General-purpose input/output (GPIO) Human-Machine Interface (HMI) Up to 44 GPIO pins (64-pin) Up to 54 GPIO pins (64-pin); up to 70 GPIO pins (80-pin) Pin interrupt & DMA request capability Pin interrupt & DMA request on all pins capability on Port A and D only Digital glitch filter on Port D only Digital glitch filter on RESET_b and select LLWU wakeup pins Hysteresis and configurable pull up device on all input pins Configurable slew rate and drive strength on all output pins Hysteresis and fixed pull up on all i/p pins (except SWD_CLK) Fixed slew rate and drive strength on all o/p pins (select SPI pins have slew rate off for faster timing) 4 pins with 18 ma high current drive Single cycle IOPORT Touch sensor inputs (TSI) (but is more SW intensive) Analog 16-bit analog-to-digital converter 0 (ADC0) 11 single-ended channels 10 single-ended channels 2 differential pairs (dedicated pins) 2 differential pairs (muxed) Includes dedicated analog domain No dedicated analog domain. High-speed comparator (HSCMP) with internal (new low power sample mode) 12-bit DAC No 1 (2x16-bit FIFO, no swing mode, no watermark) Voltage reference (VREF) 1.2 V No 18

19 Feature 50 MHz K20 KL25Z Programmable delay block (PDB) 16-bit Flexible timer 0 16-bit Flexible timer 1 16-bit Flexible timer 2 Timers channel0 for ADC0, channel1 for F0 sync1, individual pulse-outputs to HSCMPs 8 channels, F32 fully motor control features Timer clock selections Bus clock, MCGFFCLK, F_CLKINx 2 channels, F32 with Quadrature decoder feature Timer clock selections Bus clock, MCGFFCLK, F_CLKINx No No (new trigger sources from LPR and TPM) 6 ch, LPTPM with basic TPM features, functional in STOP/VLPS Timer clock selections - PLL/2, FLL, IRCLK or ERCLK 2 ch, LPTPM with basic TPM features, functional in STOP/VLPS Timer clocked selections - PLL/2, FLL, IRCLK or ERCLK 2 ch, LPTPM with basic TPM features, functional in STOP/VLPS Timer clock selections - PLL/2, FLL, IRCLK or ERCLK 32-bit Programmable interrupt timer (PIT) 4 channels 2 channels Carrier modulator timer (CMT) Yes No Real-time clock (RTC) Auxiliary VBAT supply Uses MCU VDD supply 32 khz independent external oscillator Uses 32kHz system oscillator or external RTC_CLKIN path 32 Byte register file No 32 Byte register file System Tick (Systick) 24-bit timer (Core clock) 24-bit timer (Core clock / 16) 19

20 Feature 50 MHz K20 KL25Z Communication Interfaces USB device charger detect Yes No Serial peripheral interface (SPI) 1 DSPI w/ 4 TX and 4 RX FIFOs (bus clock) 2 S08 SPI w/o FIFO (SPI0 on bus clock and SPI1 on core clock) Serial audio interface (SAI) 1 No Inter-Integrated Circuit (I2C) 1 2 Universal asynchronous receiver/transmitter 0 (UART0) 1 FlexSCI with standard features plus ISO7816, FIFO, IrDA, and LON (clocked by Core clock) UART FlexSCI with standard features plus IrDA (UART1 clocked by Core clock and UART2 clocked by Bus clock) 1 LPSCI w/o FIFO and standard S08 SCI features, functional in STOP/VLPS TX/RX baud rate can be asynchronous to Bus clock Supports x4 to x32 receiver baud rate oversampling ratio UART0 clock selections - PLL/2, FLL, IRC or ERCLK 2 S08 SCI w/o FIFO and standard features (clocked by Bus clock) 20

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23 Ultra-efficient Cortex-M0+ processor Most energy-efficient 32-bit processor on the market with industry leading throughput/ma Energy-saving architecture Optimized for low power with 90nm TFS technology, clock and power gating techniques, and highly efficient platform featuring a low power boot option, bit manipulation engine, peripheral bridge crossbar and zero wait state flash memory controller Ultra-low-power modes Several, flexible power modes fit for different application use cases designed to maximize battery life Energy-saving peripherals Smart peripherals with functionality in deep sleep modes can make intelligent decisions and process data without waking up the core 23

24 Power ENERGY SAVINGS Very Low Active and Standby Power Consumption Energy Saving Peripherals Reduced Processing Time Initialization Control Compute Ultra-low Active Current CPO offers lower compute Current Ultra-low Standby Current Deep Sleep Mode Time 48 MHz 6 ma VLLS0 Deep 200 na CoreMark/MHz MHz 300 ua LLS Deep 1.9 ua LLS Wake-up Time 4.0 us 24

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26 Most energy-efficient 32-bit processor on the market Processor power consumption as low as 9uA/MHz 30% power reduction from Cortex-M0 56% increased energy efficiency from Cortex-M0 Outstanding performance results of 2.40 CoreMark/MHz 2 to 40 times higher performance compared to 8/16-bit architectures including TI MSP430, Microchip PIC18 & PIC24, and Atmel ATXmega 9% increased performance from Cortex-M0 Single-cycle fast I/O access port facilitates bit-banging and software protocol emulation, keeping an 8-bit look and feel Up to 50% faster than normal I/O Single-cycle 32b x 32b multiply instruction Interrupt latency decreased by 1 cycle compared to the Cortex-M0 26

27 MTB Micro Trace Buffer Provides a low cost trace solution without using additional I/O pins Information is read back over serial wire interface Stores change of flow information is a user defined area of system RAM Address branched from Address branched to Encodes cause of the branch (exception/instruction) Debugger can read back the trace packets and recreate an instruction by instruction trace. Can be configured either by application code or by the debugger Tracing can be halted when the buffer is full or can be allowed to wrap Kinetis L added Watchpoints offer trace start/stop based on address or data value 27

28 Previous Kinetis K series devices offered a single bit LPBOOT option. The benefits of this option were very limited. The SIM_CLKDIV was not written until the flash was fully initialized. In the L series the LPBOOT has been re-architected to offer more choices of BOOT time vs dynamic IDD. System clock dividers (SIM_CLKDIV) now loaded at the start of the boot process Clock source during flash initialization is selectable The FOPT register now contains 2 bits (0 and 4) to control the default system divider setting. Values of divide by 1, 2, 4, and 8 FOPT register also contains the FAST_INIT bit to select either the system clock (frequency defined by the SIM_CLKDIV) or the internal flash clock. 34

29 Normal boot Fast clock, Core clock divide by 1 ~6mA peak ~4mA nominal Time to first toggle = 98.3us 35

30 LPBOOT boot Slow clock, Core clock divide by 8 ~4mA peak ~2 2.5mA nominal Time to first toggle = 848.5us 36

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32 Intelligent peripherals increasing time in deep sleep modes with no CPU intervention for increased battery life Peripheral DMA UART SPI I2C USB LPTPM (Timer/PWM) LPR (Timer/Pulse Counter) RTC Low Power Functionality Allows energy-saving peripherals (ex. ADC, UART and Timer/PWM) to trigger asynchronous DMA request in STOP/VLPS modes to perform DMA transfer and return to current power mode with no CPU intervention Supports asynchronous transmit and receive operations to the bus clock supporting communication down to STOP/VLPS modes. Configurable receiver baud rate oversampling ratio from 4x to 32x allowing higher baud rates with lower clock sources Supports slave mode address match wake-up function and first message capture down to STOP/VLPS modes Supports multiple address match wake-up function down to STOP/VLPS modes Supports asynchronous wakeup on resume signaling down to STOP/VLPS Supports 16-bit timer input capture, output compare and PWM functions down to STOP/VLPS modes Supports 16-bit timer and pulse counter functions in all power modes Supports 32-bit seconds counter with seconds interrupt and programmable alarm in all power modes with include temperature and voltage compensation 38

33 Intelligent peripherals increasing time in deep sleep modes with no CPU intervention for increased battery life Peripheral ADC CMP (Analog Comparator) DAC Segment LCD TSI (Capacitive Touch Sense Interface) LLWU (Low- Leakage Wakeup Unit) Low Power Functionality Supports single conversions in multiple result registers down to STOP/VLPS modes with hardware averaging and automatic compare modes Supports threshold crossing detection in all power modes along with a triggered compare mode for lower average power compares Supports static reference in all power modes Supports alternate displays and blink capability in all power modes Supports wake-on capacitive touch on single channel in all power modes Supports 8 wake-up pins, RESET and NMI wakeup pins, and some energy-saving peripherals in LLS and VLLSx modes 39

34 2 UART designs are provided with similar functionality however one provides additional low power mode features UART0 features: Baud rate clock is independent of the bus clock Sources are IRCLK, ERCLK, FLLCLK or PLLCLK/2 Need to be careful when exiting low power modes in PEE mode Configurable baud rate oversampling of 4x to 32x Allows higher baud rates with lower uart clock Allows for operation in STOP/VLPS with DMA transfers independent of the MCU Guaranteed to receive the first byte in STOP/VLPS Supports address match capability 40

35 Potential use case Multiple devices on a common bus (single wire) MCU can be placed in VLPS mode and if the MCG is configured appropriately, the UART0 baud clock can remain active Using address match mode, messages that are not for this particular device can be ignored without waking the MCU When a matching address is received, subsequent frames can be stored to memory via asynch DMA. The system and bus clocks would be automatically enabled to allow the transfer but the core clock would be gated off. Once the DMA transfers are complete, the MCU can be woken to process the whole set of data without having to wait for each frame to be received individually. 41

36 Based on the TPM used in the S08 family Has extended functionality to use an asynchronous clock allowing the TPM to remain functional in STOP and VLPS modes. Supports input capture, output compare and PWM functions Clock sources are: OSCERCLK MCGIRCLK MCGPLLCLK/2 MCGFLLCLK EXT Clock in Has the ability to initiate DMA transfers even in VLPS mode via the asynchronous DMA. 43

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38 DEEP SLEEP SLEEP RUN Expands beyond typical run, sleep and deep sleep modes with power options designed to maximize battery life in varying applications Mode Run VLP Run (VLPR) Wait VLP Wait (VLPW) Stop VLP Stop (VLPS) LL Stop (LLS) VLL Stop 3 (VLLS3) VLL Stop 1 (VLLS1) VLL Stop 0 (VLLS0) Definition MCU can be run at full speed. Supports Compute Operation clocking option where bus and system clock are disabled for lowest power core processing and energy-saving peripherals with an alternate asynchronous clock source are operational. MCU maximum frequency is restricted to 4MHz core/platform and 1 MHz bus/flash clock. Supports Compute Operation clocking option. LVD protection is off and flash programming is disallowed. Allows all peripherals to function, while CPU goes to sleep reducing power consumption. No Compute Operation clocking option. Similar to VLP Run, with CPU in sleep to further reduce power. No Compute Operation clocking option. MCU is in static state with LVD protection on. Energy-saving peripherals are operational with Asynchronous DMA (ADMA) feature that can wake-up DMA to perform transfer and return to current mode when complete. AWIC detects wake-up source for CPU. Lowest power mode with option to keep PLL active. MCU is in static state with LVD protection off. Energy-saving peripherals are operational with ADMA feature. AWIC detects wake-up source for CPU. MCU is in low leakage state retention power mode. LLWU detects wake-up source for CPU including LPR, RTC, TSI, CMP, and select pin interrupts. Fast <4.3us wake-up. MCU is placed in a low leakage mode powering down most internal logic. All system RAM contents are retained and I/O states held. LLWU controls wake-up source for CPU similar to LLS mode. Similar to VLLS3 with no RAM or register file retention. Pin wakeup supported. LPR, RTC, TSI and CMP wake-up supported with external clock. No RAM or register file retention. Optional POR brown-out detection circuitry. 49

39 *Compute Operation enabled: 48MHz core / 24MHz bus) ** Compute Operation enabled: 4MHz core / 800kHz bus) *** Running Coremark algorithm, KEIL 4.54 optimized for speed 50 Kinetis Power Modes RUN Recovery Time KL25 Typical 3V and 25C Leading Dynamic Power ma*/ 6.4 ma*** VLPR Innovative low power process technology (C90TFS) ua**/ 980 ua*** WAIT Low Power focused Platform Design 1.6us 48MHz VLPW Next Generation Cortex M0+ core 1.6us 4MHz STOP Asynchronous DMA Wake-up (ADMA) 4.0us 345uA Energy-saving peripherals are operational with ADMA feature that can wake-up DMA to perform transfer and return to current mode when complete 4.0us 4.4uA LLS Low Leakage Wake-up Unit 4.0us 1.9uA VLLS3 Enables complete shut-down of core logic, including AWIC, further reducing leakage currents in all low power modes 42us 1.4uA Supports 8 external input pins and up to 8 internal modules as wakeup sources; extends the low power wake-up capability of some internal peripherals to all power modes. VLPS VLLS1 93us 700nA VLLS0 Wake-up inputs are activated in LLS or VLLS modes 95us 176nA / 381nA

40 Partial STOP modes Two new clock options in STOP mode allow the PMC, MCG and Flash to remain fully powered PSTOP2 Only System clocks are shut off. Bus clock remains active Peripherals running from the bus clock can remain fully functional in this mode PSTOP1 Both System and bus clocks are gated off but the system clock source remains active Reduces power consumption over PSTOP2 but prevents use of bus clocked peripherals. Energy saving peripherals that use clock sources directly from the MCG/OSC can remain active in this mode 51

41 Compute Operation mode Keeps CPU enabled with full access to RAM and Flash Available in both RUN and VLPR modes Generation of asynch interrupts and DMA requests are possible Writes to GPIO outputs are possible by means of the IOPORT Exit from CPO can be by means of software or an interrupt (exit from CPO by interrupt is optional) Must exit CPO before accessing peripheral registers 52

42 When should you use each of these modes? Each mode has it s own advantages and disadvantages and the application drives which mode should be selected. Consideration needs to be given to the requirements of the application Is a fast wake up time required? Does the RUN current need to be kept below a minimum value? Is flash programming required in the application? What is the active/sleep duty cycle? Are there computational intensive requirements? What peripherals are required to be active? Is accurate timing required in low power modes? What type of wake up event is required (ext/int)? To achieve lowest power, the best mode may not be the one with the absolute lowest Idd. 53

43 Switching between modes 55

44 Low Power Mode checklist The SMC_PMPROT must be set to allow the mode you wish to enter (write once) Clock monitor must be disabled before entering any low power mode except WAIT A wake up source must be enabled before entering a low power mode, just an interrupt for VLPS or greater and also LLWU for LLS or lower Select the desired low power mode in the SMC_PMCTRL and SMC_STOPCTRL registers Set/Clear ARM SLEEPDEEP bit for STOP/WAIT. Read the SMC_STOPCTRL register before executing WFI instruction To enter VLPR you must Be in BLPI (using fast IRC) or BLPE clock mode Set the core frequency to 4MHz or less and flash clock to 1MHz or less Not have the slow IRC enabled Disable the clock monitor Write the SMC_PMCTRL RUNM bits to enter VLPR 56

45 Exiting Low Power Modes Exiting VLPR Software write of the RUNM bits in the SMC Exiting WAIT/STOP/VLPS By an interrupt Code re-starts from where the low power mode was entered after exiting ISR Exiting LLS By a low leakage wake up (LLWU) event LLWU interrupt is pending after wake up and takes priority Internal module flags must be cleared in the LLWU ISR Code re-starts from where the low power mode was entered after exiting ISR 57

46 Exiting Low Power Modes Exiting VLLSx VLLSx recovery is via the reset flow After exiting any of the VLLSx modes, the IO remain latched until they are released by writing 1 to the ACKISO bit in the PMC The GPIO must be re-configured before ACKISO is written If there is no requirement to make use of any external IO, there is no need to re-configure it before re-entering VLLSx If the oscillator has been kept running in VLLS1 or VLLS3, it must be re-configured before ACKISO is written (unless it was configured in RTC) RAM contents need to be re-initialized if using VLLS1 or VLLS0 58

47 Exiting Low Power Modes (Exiting VLLSx continued) The LLWU interrupt will be pending If the wake up was by a module then the associated Module interrupt will also be pending The interrupt taken will be the first one enabled in the reset flow If the LLWU interrupt is the first enabled then the module interrupt flag must be cleared in the LLWU ISR If the Module interrupt is the first enabled then the module ISR will clear the interrupt flag and the LLWU ISR will no longer be pending Pin wake up flags must be cleared in the LLWU VLLS wakeup will be reported in the RCM 59

48 Power mode differences within the Kinetis L series KL02 has no LLS mode KL02 has no LLWU, limited wake up sources LPR, CMP, NMI pin and RESET pin KL02 has no RTC 60

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50 Power Modes RUN Normal fully active mode WAIT CPU is halted, all other circuits active VLPR Very Low Power RUN, reduced frequency, low power RUN mode VLPW VLPR equivalent of WAIT STOP System is clock gated, some peripherals still active VLPS Very Low Power STOP, lower power version of STOP, using back bias with fewer clocks available LLS Low Leakage STOP VLLSx Very Low Leakage STOP, power is turned off to areas of the device Clock Modes IRC Internal Reference Clock, slow (32kHz) and fast (4 MHz) are available FEI FLL Engaged Internal, FLL is system clock using the slow IRC as the reference FEE FLL Engaged External, FLL is system clock using an external reference clock FBI FLL Bypassed Internal, IRC is used as the system clock but the FLL is still running with the IRC as the reference FBE FLL Bypassed External, Ext. clock is used as the system clock but the FLL is running with the external clock as the reference BLPI Bypassed Low Power Internal, IRC is used as the system clock but the FLL is disabled BLPE Bypassed Low Power External, external clock is used as the system clock but the FLL is disabled PBE PLL Bypassed External, Ext. clock is used as the system clock but the PLL is running with the external clock as the reference PEE PLL Engaged External, PLL is used as the system clock with the external clock as the reference 62

51 Power Management App Note - Asynchronous DMA App Note - TSS Main Page TSS Library - MCU&fpsp=1&nodeId= USB Main Page - USB Stack download - EDICALUSB&location=null&fpsp=1&Parent_nodeId= &Parent_pa getype=product ADC Measurement App Note (not Kinetis specific but applies to Kinetis) - FRDM-KL25Z Main Page - KL25Z&parentCode=KL2x&fpsp=1 63

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