Embedded Operating Systems. Unit I and Unit II

Transcription

1 Embedded Operating Systems Unit I and Unit II

2 Syllabus Unit I Operating System Concepts Real-Time Tasks and Types Types of Real-Time Systems Real-Time Operating Systems

3 UNIT I

4 Operating System Manager: CPU, I/O, memory Abstraction: Hides details of h/w from the user Layers of protection: Users supervisor Support: Applications run above Bit length and OS: 32-bit 64-bit 32-bit Windows 7 or 64-bit Windows 7 No. of apps don t run on 64-bit ver! Many cross compilers, IDEs don t run on 64-bit ver!

5 What s an embedded system? Wiki: An embedded system is a special-purpose system in which the computer is completely encapsulated by or dedicated to the device or system it controls.

6 Embedded Operating Systems Why Embedded Systems need OS? They are complex, run multiple tasks, have many I/Os and networks to manage

7 Embedded Operating Systems ecos Embedded Linux RTLinux FreeDOS FreeRTOS LynxOS RTOS MicroSuse NetBSD OpenBSD Inferno (operating system) ITROM OSE OS-9 QNX RTEMS RTXC Quadros VxWorks Windows CE Windows XP Embedded SymbianOS T2 SDE

8 Network OS (NOS) Specialized in managing networked systems alone E.g.: Windows NT, Microsoft server, Novell Netware

9 Layers of OS

10 History of OS MSDOS: Unix: 1970, Ken Thomson and Dennis Ritchie Windows: 1990s Windows 3.0 Linux: 1991, Linus Torvalds

11 Functions - OS Process management Memory management I/O Management File Management Support to Multiprogramming Protection Security Network management

12 Kernel Functions Interrupt handling Task creation and scheduling Inter Process communication Support for I/O devices Memory allocation and deallocation File system management Network management

13 Facts - kernel While loading OS, specific kernel options have to be configured. This is w.r.t. h/w Changing Mother Board, Processor, memory require kernel updates For E.S. boards, it is important to know type of board so that kernel can be selected and configured

14 Types of Kernel Monolithic Kernel Microkernel

15 Monolithic Kernel It has simple design and is a large single process Runs entirely in single address space i.e.: kernel space and in supervisory mode Kernel is bulky and is difficult to extend and maintain E.g.: Unix, Linux, MSDOS

16 Monolithic Kernel

17 Microkernel It is minimum amount of software to provide the mechanisms needed to implement an OS mechanisms => low-level address, space management, thread management, and IPC Kernel is broken down into separate processes (servers) Some of the processes (servers) run in kernel space and some run in user-space E.g.: MINIX by A. Tanenbaum, QNX (RTOS), Mach kernel 3.0 by CMU

18 Microkernel

19 Tasks/Processes A program in execution is a process Task or a job can also be used to denote process Process can be in any one of 5 states broadly 1. New 2. Ready 3. Running 4. Blocked 5. Exit For each task there is Task Control Block (TCB)

20 State transition diagram of a process

21 Task (Process) Control Block

22 Multitasking Time multiplexing Context Context switch Overhead

23 Task scheduling Techniques, methods.. Time, priority, order?? Scheduling policy of OS decides CPU bound tasks and I/O bound tasks CPU bound tasks are computation intensive I/O bound tasks need more I/O time

24 Quality points that rate Scheduling algorithms CPU utilization: % of time CPU working Response time: task waiting for CPU to respond Turnaround time (TAT): time interval from which the task is presented to the system to the instance at which task exits after completion Throughput rate: No. of tasks processed in unit time

25 Scheduling Algorithms 1. Non-preemptive scheduling Co-operative scheduling Shortest job next Priority based scheduling 2. Preemptive scheduling Round robin scheduling Pre-emptive priority Pre-emptive SJN/ Shortest remaining time (SRT)

26 Threads

27 Interrupt Handling In OS interrupts are used either with h/w support or by pure software ISR Interrupt latency Sequence of actions following an interrupt: Saving current context Determine ID of the interrupt Switch to new context Starting the execution of interrupt handler (ISR)

28 Interrupts and Task Switching Task switching is accomplished by the mechanism of interrupts The total switching latency = interrupt latency + dispatch latency

29 Inter Process (Task) Communications (IPC) Where is communication needed? Processes in the same machine, and processes in different machines might need to communicate to share data, or to send queries and receive responses Two of the task communication methods are i) Shared memory ii) Message passing e.g.: Semaphores, Pipes, Mailbox, RPC

30 Shared Memory

31 Message Passing

32 Producer Consumer Paradigm Sender receiver communication is a Producer Consumer Paradigm Consumer consumes if producer produces Producer needs to produce as long as consumer consumes it Bounded buffer problem: sender side receiver side

33 Task Synchronization There are three aspects to it. First, how different tasks with conflicting actions can cause havoc. Second, how to avoid such situations and third, if such a situation occurs, how to get out of it.

34 Task Synchronization Race Condition Critical Section Solution to Race Condition Automicity Disable interrupts Locks - mutex

35 Deadlocks What is Deadlock? What are the Necessary conditions? Mutual exclusion Hold & wait Non-Preemption Circular Wait How to deal with them? Ignore, avoid, prevent, detect and recover

36 Tasks and their Conflicts Priority Inversion? Solution to this : Priority Inheritance and Priority Ceiling

37 Device Drivers in OS What are they? What are the types? What are the design issues?

38 Layers Associated with Device Driver I/O Service I/O Request

39 Real-Time Systems & Real-time Tasks It consists of many tasks with at least one time constrained task Real-Time tasks Hard real-time and Soft real-time Can be pre-emptive or non-preemptive Periodic, Aperiodic, Sporadic

40 What does an RTOS do?

41 Kernel Services of an RTOS

42 Real-time Scheduling Algorithms

43 UNIT II

44 Syllabus Unit II Processor basics Integrated Processors: SOC History of ARM Processors Hardware Platforms ARM Architecture Interrupt Vector Table ARM Programming Assembly Language Instruction Set Read only and Read-Write Memory ARM9 ARM-Cortex-M3 Case Study of BeagleBone Black Board

45 SYSTEM-ON-CHIP (SOC) Embedding: Multiple processors, memories, multiple standard source solutions (IP Cores), analog units

46 A SOC Embedded System -with two internal ASICs, two internal processor and peripheral interfaces ASIPs IPs Data Address generator Program Address generator Multiprocessor DSP RISC processor Program data and memory Port Other Digital circuits- Timer,MUXs Port Interfaces DMAC Interrupt Controller Analog circuits, A /D EEPROM

47 History of the ARM Processor Acorn Computers Ltd. (UK) developed ARM1, ARM2 ARM5 Acorn Computers Ltd. + Apple Computers + VLSI Tech. Group Advanced RISC Machines Ltd. ARM6, ARM 7 most popular and still widely used ARM9, ARM10,ARM11 CORTEX 90% of embedded 32-bit RISC processors used are ARM processors

48 The ARM Core What is meant by the core? The core is the processing unit or the computing engine It has all the computing power, and this aspect is decided by the architecture, which represents the basic design of the processor The ARM Microcontroller is ARM core with peripherals added to it

49 ARM SOC Core with Peripherals

50 The RISC Architecture These apply to most of the instructions of ARM 1) Instructions are of the same size, that is, 32 bits 2) Instructions are executed in one cycle 3) Only the load and store instructions access memory

51 Advanced Features of ARM Thumb MMU and MPU Cache Debug interface Embedded ICE macrocell Fast multiplier Enhanced instructions Jazelle DBX (Direct Bytecode execution) Vector floating point unit Synthesizable

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55 Features of ARM which make it special Data bus width Computational capability Low Power Pipelining Multiple Register instructions DSP Enhancements

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57 Operating Modes Of ARM

58 Register Set

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61 CPSR

62 Interrupt Vector Table

63 Programming the ARM processor Can be done in Assembly as well as in high level languages Assembly Language Programming: Instruction set features: 1) Instructions are of the same size, that is, 32 bits 2) Only the load and store instructions access memory 3) Barrel shifter..more than I bit of shift/rotation 4) Conditions can be appended to the instructions Data Types and Data Alignment: 32-bit 2 words each 16-bits byte Both Little Endian and Big Endian supported 4 banks of memory

64 Instruction Set

65 Data Processing Instructions Move Shift Move and Shift together

66 Conditional Execution

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68 Data Processing Instructions Arithmetic

69 Data Processing Instructions Logical Compare

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71 Load-Store Instructions

72 Branch Instructions

73 Loading constants-immediate mode ARM has the limitation that its instruction size should nor exceed 32 bits This means that the constant should fit in the word length of 32 bits along with the opcode, condition code, register code and other information So, we can t have a 32-bit constant embedded in the instruction! ARM uses an ingenious technique the use of rotation of a small number to generate a large number

74 Constants

75 Multiple Load and Store

76 Readonly and Read/Write Memory The two memory areas defined by the compiler are Readonly for code and Read/write memory for data This corresponds to ROM and RAM RAM is used for intermediate results, for temporary storage, etc., as this is volatile memory In the readonly memory, data is written using directives like DCD, DCW, etc.

77 ARM 9

78 ARM 9 32-bit Harvard Architecture 5-stage pipeline DSP instructions E.g.: LPC29XX (2917, 2919, 2927, 2927) 125 MHz core, 2.0 USB host-device, CAN, LIN, 56KB SRAM, 768KB Flash, three10-bit ADC, multiple serial & parallel interfaces

79 ARM Cortex-M3

80 ARM Cortex-M3 Up to 100 MHz CPU frequency 3-stage pipeline Harvard architecture Separate instruction, data and peripheral bus 64 KB SRAM, 512KB Flash Ethernet MAC, USB host-device 8-channel DMA controller 4 UARTs, 2 CAN ports, 2-SSP controllers, SPI interface 3 I2C interfaces, 8-channel 12-bit ADC, 10-bit DAC, PWM 4 timers, RTC, 70 general purpose I/O pins

81 BeagleBone Black low-cost, open source, community-supported development platform for ARM Cortex -A8 processor developers and hobbyists Shipped with the Debian GNU/Linux in onboard FLASH Other Linux distributions and operating systems are also supported on BeagleBone Black including: Ubuntu, Android, Fedora to get all h/w details Blogs

82 BeagleBone Black

83 BeagleBone Black Features Processor : 1GHz AM3359 Sitara ARM Cortex-A8 512 DDR Memory On-chip 10/100 Ethernet 512MB DDR3 RAM 4GB 8-bit emmc on-board flash storage with Debian GNU/Linux 3D graphics accelerator NEON floating-point accelerator 2x PRU 32-bit microcontrollers USB client for power & communications USB host Ethernet HDMI 2x 46 pin headers

84 BeagleBone Black Programming BoneScript JavaScript C++ programming with Eclipse IDE with CDT

85 Thank you