NXP Cortex-M0 LPC1100L Design with a Cortex-M0 in a DIP package ASEE Tech Session. Sergio Scaglia (NXP Semiconductors) August 2012

Transcription

1 NXP Cortex-M0 LPC1100L Design with a Cortex-M0 in a DIP package ASEE Tech Session Sergio Scaglia (NXP Semiconductors) August 2012

2 Agenda NXP Microcontroller Portfolio Cortex M0 LPC1100L Family Support/Resources Hands-On Lab Questions 2

3 NXP is a leader in ARM Flash MCUs Clear strategy: 100% focus on ARM Top performance through leading technology & architecture Design flexibility through pin- and software-compatible solutions Scalable memory sizes Widest range of peripherals Unlimited choice through complete families for multiple cores 3 3

4 NXP MCU the only complete ARM range of Cortex-M0, Cortex-M3 and Cortex-M4 processors cost performance 8-bit 16-bit 32-bit DSP Entry level Cortex-M0 NXP ARM Cortex-M Continuum Cortex-M0 Cortex-M3 Cortex-M4 Fully featured Cortex-M4 True 8/16-bit replacement - low power, low cost, more performance High performance for communication and control - USB, Ethernet, CAN, and much more Advanced Digital Signal control - Floating point unit - Dual-core options Over 250 different ARM based microcontrollers available!! (* Recommended price at 10kpcs) 4 4

5 Rapidly growing family of ARM Cortex-M MCUs Check pin- and software compatible options: Cortex-M4 Up to 204 MHz LPC4300 LPC4000 High Performance Dual Core Cortex-M4/M0 FPU and DSP extensions Cortex-M3 Up to 180MHz LPC1800 LPC1700 LPC1300 Memory options up to 1MB flash, 200k SRAM High-performance with USB, Ethernet, LCD, and more USB solution, incl. on-chip USB drivers 5 5

6 NXP s Cortex -M0 True 8/16-bit replacement Cortex-M0 was designed to replace 8/16-bit architectures ARM s smallest, lowest-power, and most energy-efficient 32-bit MCU core to date Simplicity! Small instruction set keeps silicon area and gate count similar to traditional 8/16-bit MCUs 6 6

7 Widest Selection of Cortex-M0 Packages Package CSP16 QFN33 QFN33 BGA48 QFP48 QFP64 QFP100 SO20 TSSOP20 TSSOP28 DIP28 Width (mm) Length (mm) Height (mm) Sample Picture NXP offers the widest selection of packages for Cortex-M0 devices World s first low-pin-count 32-bit ARM packages World s smallest 32-bit ARM MCU 2 x 2 mm 2 7

8 USB Solutions for Cortex-M0 LPC11U1x Pin-to-Pin Compatible LPC11U2x 32K Flash, 6K SRAM LPC11U3x 32K Flash, up to 10K SRAM, up to 4K EEPROM LQFP64 package offering LPC134x K Flash, up to 10K SRAM, up to 4K EEPROM Small sector size (256 bytes) LQFP64 package offering Up to 64K Flash, up to 10K SRAM, up to 4K EEPROM Small sector size (256 bytes) LQFP64 package offering Low cost USB Platform for mbed Platform for LPCXpreso 8 8

9 ARM Cortex-M0 Re-defining 32-bit migration 2-10x higher performance than 8/16-bit MCUs 40-50% smaller code size than 8/16-bit MCUs 2-3x power saving compared to 8/16-bit MCUs Pin compatible options from M0 to M3 ARM s smallest, lowest-power, and most energy-efficient efficient 32- bit-processor core to date 9

10 CoreMark Benchmarks Performance CoreMark Performance CoreMark Score Power ARM Cortex-M ENERGY EFFICIENT Power 8-bit or 16-bit ENERGY COST LPC1100L 16-bit MSP430 8-bit ATMega Time Time x higher performance than 8/16-bit MCUs 10 10

11 8- vs. 16-bit vs. Cortex-M0 Current Comparison 11

12 Cortex-M0 Has Lower Power Consumption Cortex-M0 runs at a much slower clock frequency for the same required performance Cortex-M0 can sleep most of the time, or spare the resource for handling additional tasks 12

13 Superior Code Density (e.g. 16-bit Multiply) MOV A, XL ; 2 bytes MOV B, YL ; 3 bytes MUL AB; 1 byte MOV R0, A; 1 byte MOV R1, B; 3 bytes MOV A, XL ; 2 bytes MOV B, YH ; 3 bytes MUL AB; 1 byte ADD A, R1; 1 byte MOV R1, A; 1 byte MOV A, B ; 2 bytes ADDC A, #0 ; 2 bytes MOV R2, A; 1 byte MOV A, XH ; 2 bytes MOV B, YL ; 3 bytes ; 1 byte ADD A, R1; 1 byte MOV R1, A; 1 byte MOV A, B ; 2 bytes ADDC A, R2 ; 1 bytes MOV R2, A; 1 byte MOV A, XH ; 2 bytes MOV B, YH ; 3 bytes MUL AB; 1 byte ADD A, R2; 1 byte MOV R2, A; 1 byte MOV A, B ; 2 bytes ADDC A, #0 ; 2 bytes MOV R3, A; 1 byte 8-bit (8051) 16-bit (MSP430) 28 Instructions MOV R4,&0130h MOV R5,&0138h MOV SumLo,R6 MOV SumHi,R7 (Operands are moved to and from a memory mapped hardware multiply unit) 4 Instructions MULS r0,r1,r0 ARM Cortex-M0 1 Instruction Time: 48 clock cycles Code size: 48 bytes Time: 8 clock cycles Code size: 8 bytes Time: 1 clock cycle Code size: 2 bytes 13

14 CoreMark Benchmarks Code Size Code Size Comparison Bytes LPC1100L 16-bit MSP430 8-bit ATMega % smaller code size than 8-/16-bit 14

15 Superior Code Density Instruction Size for Various Processors Leading to superior code density: In Cortex-M0 all instructions (except BL) are 16-bit wide instructions Over 64K of address space, 8- and 16- processors have to introduce paging leading to extra overhead in code Efficiency of the Cortex-M0 instruction set (next slide) 8051 PIC18 PIC24 MSP430/ MSP430X Cortex-M0 15

16 LPC1100L in Low-Pin-Count Packages Cortex-M0 Core up to 50 MHz Lowest Active Current 130 ua/mhz (LPC1100XL 110 ua/mhz) Memory: Up to 32 KB on-chip flash Up to 4 KB SRAM Peripherals U(S)art (1), SPI/SSP (1), I2C (1) 4x general purpose Timers with PWM 10-bit 5-channel ADC Programmable WDT and WD Oscillator +/- 1 % accuracy, 12 MHz IRC Oscillator Single power supply (1.8 V to 3.6 V) SO, TSSOP, DIP package options 16

17 Important Features for 8/16-bit MCU Customers Timers with PWM Generation For each timer, up to four match registers can be configured as PWM, each timer supports up to three match outputs as single edge controlled PWM outputs; Dynamic System Clock Switching Change frequency on the fly depending on processing demand. The LPC1100 current consumption at 50 MHz is specified at 7mA. This can be reduced to a little over 130uA when running at 1 MHz on the low-power internal oscillator; Clock Output Clock output with divider can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock. Output can source downstream devices such as other microcontrollers, CPLD or FPGA; Interrupt via Any GPIO Any GPIO pins can be used as Edge and Level Sensitive interrupt sources; Programmable Pull Up/Down/Open Drain Internal pull-up/pull-down resistor, pseudo open drain or bus keeper function; Enhanced GPIO Pin Manipulation Capable of simultaneously reading Bit/Byte/Word or toggling up to 22 I/Os per instruction 17

18 Low-Pin-Count Package Options SO20 TSSOP20 (2 Options) TSSOP28 DIP28 Final Part Number SRAM Flash Package Pin Count I2C SPI UART 16b Timer 32b Timer ADC GPIO LPC1110FD SO b, 5ch 16 LPC1111FDH20 / TSSOP b, 5ch 16 LPC1112FD20 / SO b, 5ch 16 LPC1112FDH20 / TSSOP b, 5ch 14 LPC1112FDH28 / TSSOP b, 6ch 22 LPC1114FDH28 / TSSOP b, 6ch 22 LPC1114FN28 / DIP b, 6ch 22 18

19 Why Choose LPC Package Devices from NXP Manufacturing Efficiency and Supply Guarantee NXP ships over three billion Low-Pin-Count packages per year, no backend capacity constraints High manufacturing efficiency and cost leverage for these MCU devices Clear Migration Path Firmware compatible with other NXP Cortex-M0 devices Firmware re-usable when upgrade to NXP Cortex-M3 devices $0.49 Today Low-Pin-Count devices starts at $0.49 for 10Kpc via distribution 19

20 Targeted Applications Consumer Electronics Human Input Devices (e.g. mouse) Simple motor control (e.g. fan control) Toys Small appliances Industrial Control Thermostat Lighting / Home Security Medical Portable health care products More 20

21 Where to get started? MCU homepage Product updates and training Low-cost development Engineering community

22 Objective Using the LPCXpresso Development Platform, and familiarity with the LPC1114 device Integrating the LPC1114 device (DIP package) onto a breadboard Build an application where the LPC1114 drives a 10 LED bar graph controlled by a Potentiometer 22

23 NXP s Low Cost Development Tool Platform Eclipse-based IDE Development Board Evaluation Product Development 23 23

24 LPCXpresso Board LPC-Link Target 24 24

25 LPC-Link LPC-Link is an integrated JTAG/SWD debug interface based on LPC3154 (ARM9) LPC-Link can be used as a standalone JTAG debugger with other LPC target boards. So, no need for a separate debug probe! LPC-Link makes it possible for users to experience the same user interface all the way to final code development and testing 25 25

26 Evaluate LPCXpresso Development Stages Explore Develop 26 26

27 LPCXpresso Web Support Main page NXP examples page, schematics and FAQ Live training modules Support forum for LPCXpresso supported by NXP and Code Red (main support destination) LPCXpresso IDE downloads and Code Red knowledgebase Base board schematics and even more example projects 27

28 Components Software LPCXpresso Development Tool ( DIP demo-bargraphled.zip file (software project) Hardware LPC1114 DIP part (qty 1) LPC1200 LPCXpresso Board (LPC-LINK debugging module + LPC1227) (qty 1) USB cable (qty 1) Breadboard (qty 1) Potentiometer (10K) ( (qty 1) 10 Segment LED Bar Graph ( (qty 1) Resistors (qty 3) Wires 28

29 LPC1114FN28/102 Pinout 29

30 Application Block Diagram 30

31 Application Board 31 31

32 Schematics Note: Please connect ONLY PIO0_1 (pin 24), PIO0_2 (pin 25), PIO0_3 (pin 26) to the LED bar graph 32

33 10 Segment LED Bar Graph LPCXpresso Board 10K Potentiometer Note: On the LPCXpresso board, on the J4 connector, remove the headers 33

34 LPCXpresso IDE Once the hardware is completed, connect the USB from the PC to the LPC-Link. Choose install the software automatically (USB Device with DFU capabilities) Open LPCXpresso now 34 34

35 LPCXpresso IDE Import Project Select the Quickstart Pan tab In the Start here tab Select Import project(s) 35 35

36 LPCXpresso IDE Import Project Browse to the ASEE folder on the desktop and select: DIP demo-bargraphled.zip Select All & Finish 36 36

37 LPCXpresso IDE Navigating Your Project Navigate to the src folder under DIP demo in the Project Explorer view Open (double-click) main.c 37 37

38 LPCXpresso IDE LPCXpresso Interface Project Explorer Editor Quick Start Console 38 38

39 LPCXpresso IDE Build Project Build the project 39 39

40 LPCXpresso IDE Debug Start the debugger Choose install the software automatically (LPC-Link Debug Probe v1.1) The debugger will: Activate the Debug View Break once inside main() 40 40

41 Running the Application Resume After hitting resume, the application should be running.rotate the pot Suspend, Terminate 41 41

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