Philippe Thierry Sr Staff Engineer Intel Corp.

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1 Philippe Thierry Sr Staff Engineer Intel Corp. IBM, April 8,

2 Agenda CPU update: roadmap, micro-μ and performance Solid State Disk Impact What s next Q & A

3 Tick Tock Model Perenity market Perenity and Time to Intel Core Nehalem microarchitecture Future uarch Merom Penryn Nehalem Westmere Sandy Bridge NEW Microarchitecture 65nm NEW Process 45nm NEW Microarchitecture 45nm NEW Process 32nm NEW Microarchitecture 32nm TOCK TICK TOCK TICK TOCK

4 Intel HPC Roadmap H 2H 1H 2H 1H 2H EXpandable Tigerton (4C) Dunnington (6C) Nehalem-EX ENtry Efficient Performance Harpertown (4C) Wolfdale-DP (2C) Harpertown (4C) Wolfdale-DP (2C) Nehalem-EP (4C/8T) Nehalem-EP WSM-EP Westmere- EP

5 Intel Xeon 5500 Platform New Memory Subsystem Intel 5520 Chipset Intel Quick-Path Interconnect PCI Express* 2.0 Intel Intelligent Power Technology Intel X25-E SSDs ICH 9/10 Intel GbE Controller New I/O Subsystem Platform Ready for Future 32nm Products

6 Nehalem-EP 4 cores - 3-level cache hierarchy 32k I-Cache + 32k D-cache Integrated Memory Controller 3 Ch DDR3 New 256k L2 cache per core Inclusive Cache Policy 8M on-chip L3 Shared Cache Cor e Cor e Cor e Cor e Simultaneous Multi-Threading capability (SMT) QuickPath interconnect Point-to-Point 2 links per CPU socket 1 for connection to other socket Q P I Shared L3 Cache 1 for connection to chipset Up to 6.4 GT/sec (12.8 GB/sec) in each direction per link ( Full duplex) Integrated QuickPath Memory Controller (DDR3) 3 DDR3 channels Two QuickPath Interconnects Up to 18 DIMMs 800/1066/1333MHz DDR3 Power: 130W, 95W, 80W, 60W

7 Intel Smart Cache Core Caches 1 st level caches 32kB Instruction cache 32kB Data Cache Support more L1 misses in parallel than Core 2 2 nd level Cache New cache introduced in Nehalem Unified (holds code and data) 256 kb per core Performance: Very low latency Scalability: As core count increases, reduce pressure on shared cache Core 32kB L1 32kB L1 Data Cache Inst. Cache 256kB L2 Cache

8 Intel Smart Cache -- 3 rd Level Cache 3 rd level cache Shared across all cores Core L1 Caches Core L1 Caches Core L1 Caches Size depends on # of cores Quad-core: Up to 8MB Scalability: L2 Cache L2 Cache L2 Cache Built to vary size with varied core counts L3 Cache Built to easily increase L3 size in future parts Inclusive cache policy for best performance Address residing in L1/L2 must be present in 3 rd level cache

9 Designed For Modularity C O R E C O R E C O R E Core Differentiatio n in the Uncore DRAM IMC L3 Cache QPI QPI Power & Clock Uncore QPI # cores # mem channels #QPI Links Size of cache Type of Memory Power Manage- ment

10 Nehalem-EP Processor N N Frequency (Ghz)Memory (MHz)QPI (GT/s) Cache (MB)

11 Memory Population Scenarios Maximum B/W: DDR across 3 channels 1 DPC (6 DIMMs) Max capacity: 48 GB 10.6 GB/s CPU CPU CPUs X5550 and above Balanced Performance: DDR across 3 channels Up to 2 DPC (12 DIMMs) Max capacity: 96GB 8.5 GB/s CPU CPU E5520 and above Maximum capacity: DDR3 800 across 3 channels Up to 3 DPC (18 DIMMs total) Max capacity: 144GB 6.4 GB/s CPU CPU All NHM-EP SKUs

12 Intel QuickPath Architecture Intel QuickPath interconnect plus integrated Intel QuickPath memory controllers Higher is better +357% +394%

13 Memory Latency Comparison Intel QuickPath interconnect plus integrated Intel QuickPath memory controllers Low memory latency critical to high performance Design integrated memory controller for low latency Need to optimize both local and remote memory latency Effective memory latency depends per application/os

14 Apps classification and performance analysis CPU bound. HPL Real world applications Memory bound. Stream Part of the code doing ops Part of the code doing memory access CPU.ops% * (cycle / trans) + Mem.ops cycle/trans) ] Mem.ops% * [ ( [ ( Lxx_success% % * cycle / trans) + (Lxx_misses( Lxx_misses% % * 1 / IPC_max Higher frequency New SSE4 Cache Size Mem BW 1 cpu no i/o No comms nb cycle to access memory

15 Peak performance % , 5365 Higher is better % of the NHM peak 43 % of the 5472 peak 25 % of the 5365 peak SSE implementation,, DP

16 Performance Enhancements Intel Turbo Boost Technology Increases performance by increasing processor frequency and enabling faster speeds when conditions allow Frequency Core 0 Normal Core 1 Core 2 Core 3 4C Turbo Core 0 Core 1 Core 2 Core 3 <4C Turbo Core 0 Core 1 Performance On-Demand Intel Nehalem Microarchitecture Intel Turbo Boost Technology Intel Hyper-Threading Technology Intel Intelligent Power Technology Integrated Power Gates Automated Low-Power States Intel Node Manager Technology All cores operate at rated frequency All cores operate at higher frequency Fewer cores may operate at even higher frequencies

17 Intel QuickPath Architecture Intel QuickPath interconnect plus integrated Intel QuickPath memory controllers Higher is better +357% +394%

18 Memory Latency Comparison Intel QuickPath interconnect plus integrated Intel QuickPath memory controllers Low memory latency critical to high performance Design integrated memory controller for low latency Need to optimize both local and remote memory latency Effective memory latency depends per application/os

19 Apps classification and performance analysis CPU bound. HPL Real world applications Memory bound. Stream Part of the code doing ops Part of the code doing memory access CPU.ops% * (cycle / trans) + Mem.ops cycle/trans) ] Mem.ops% * [ ( [ ( Lxx_success% % * cycle / trans) + (Lxx_misses( Lxx_misses% % * 1 / IPC_max Higher frequency New SSE4 Cache Size Mem BW 1 cpu no i/o No comms nb cycle to access memory

20 Peak performance % , 5365 Higher is better % of the NHM peak 43 % of the 5472 peak 25 % of the 5365 peak SSE implementation,, DP

21 Performance Enhancements Intel Turbo Boost Technology Increases performance by increasing processor frequency and enabling faster speeds when conditions allow Frequency Core 0 Normal Core 1 Core 2 Core 3 4C Turbo Core 0 Core 1 Core 2 Core 3 <4C Turbo Core 0 Core 1 Performance On-Demand Intel Nehalem Microarchitecture Intel Turbo Boost Technology Intel Hyper-Threading Technology Intel Intelligent Power Technology Integrated Power Gates Automated Low-Power States Intel Node Manager Technology All cores operate at rated frequency All cores operate at higher frequency Fewer cores may operate at even higher frequencies

22 SMT 35% 30% 25% 20% 15% 10% 5% 4% 5% 5% 11% 14% 15% 16% 17% 20% 22% 24% 25% 31% 31% 31% 0% -5% -10% -15% -10% -8% -7% -6% -5% -3% -2% -1% Data source: Intel Internal measurements Sept 2008; Configuration details same as performance summary slide. HT ON and OFF run on the same platform

23 Turbo on / off : HPL efficiency

24 Next bottleneck Memory size, BW & latency? I / O Intra / Inter socket communications CPU L 1 L 2 L 3 Memory CPU Memory L 1 L 2 L 3 Core count, size & perf? Cache Size, BW & latency Interconnect. Inter nodes Comms. Inter nodes Comms.?

25 Intel Technology is Changing HPC TCO, Performance, Reliability Solid State Disk 10GbE Optimize Performance for I/O Intensive Apps and Boot Drive Replacement Bridging the Gap Between 1GbE and Infiniband Intel IT evaluation results.

26 HD comparison : SATA Solid State Drives - The new trend 2.5 SAS 15K rpm 3.5 SATA 7.2K rpm Intel X25-E SLC SSD Capacity 300 GB 1500 GB 32 / 64 GB Bandwidth 100~170 80~130 MB/s 170~250 (W/R) Read Access 4.0ms MB/s 13.6ms 0.1 MB/s ms Time Power (Watts) 12 ~ 17 7 ~ ~ 1.8 Price $600 $130 $400 Power: Active 2.0W / 0.1W Standby Weight: 2.5 SSD 87g / 1.8 SSD 40g X25-E E has a huge advantage on random I/O

27 Finite Difference example: Xeon CPU Comparison MPI Loop over Shot Intel / Paris School of Mines MPI loop (for DD if needed ) Loop over time samples (+ OMP in FD kernel) 8 cores running : Total output : 12GB

28 Finite difference example: HD Comparison MPI Loop over Shot Intel / Paris School of Mines x 5.35 MPI loop (for DD if needed ) Loop over time samples (+ OMP in FD kernel) x 4.65

29 Non i/o optimized application : 2 x HD CGGV / Intel presentation at HPC workshop, Rice Univ, Houston, 2009 INIT SRC RCV IMG SRC RCV IMG Intel Core i7 3.2 GHz 4 cores; 6 GB, kernel 2 x Seagate 1.5TB SATA + 4 x Intel X25-E E SLC SSD (Raid 0 + ext3 filesystem)

30 Non i/o optimized application : 2 x HD CGGV / Intel presentation at HPC workshop, Rice Univ, Houston, 2009 INIT SRC RCV IMG SRC RCV IMG E5462@ 2.8 GHz i7@ 8 cores 3.2 Ghz 4 cores 2 x HD 106m n38s 122mn 7s SSD 4 x SSD Speedu p mn 31s 1.6 x Intel Core i7 3.2 GHz 4 cores; 6 GB, kernel 2 x Seagate 1.5TB SATA + 4 x Intel X25-E E SLC SSD (Raid 0 + ext3 filesystem)

31 Trace Sort : 4 sorts, 2 x HD CGGV / Intel presentation at HPC workshop, Rice Univ, Houston, 2009

32 Trace Sort : 4 sorts, 4 x X25-E E SLC CGGV / Intel presentation at HPC workshop, Rice Univ, Houston, 2009 SSD 2 x HD 4 x SSD Speedup 4 sorts 3685 s 346 s 10.6x 8 sorts 8675 s 1426 s 6.0x

33 Next bottleneck Memory size, BW & latency? I / O Intra / Inter socket communications CPU L 1 L 2 L 3 Memoire CPU Memoire L 1 L 2 L 3 Core count, size & perf? Cache Size, BW & latency Interconnect. Inter nodes Comms. Inter nodes Comms.?

34 Moore s s law nm 300mm nm 300mm Dual Core nm 300mm 130nm 200mm

35 Intel HPC Roadmap Frequency bigger Die more cores more cache lower frequency Die size ~ same TDP more transistor more cores same cache same frequency TDP Nanometers & physic s limits Transistors Cache ~ same Die ~ same TDP more transistor more cores same cache same frequency same cores count more cache higher frequency

36 Next big step Evolution of Instruction Set Architecture (ISA) : 2 YEARS Shrink/Derivative Intel Xeon, Pentium D, Intel Core Duo 65nm SSSE3 Intel Core Microarchitecture x87 Numeric data extensions MMX - 64b SIMD ISA extension SSEx - 128b SIMD ISA extensions 2 YEARS Shrink/Derivative Penryn Family New Microarchitecture Nehalem SSE4 45nm Starting 2010 Intel AVX 256b SIMD ISA extensions Benefits of Intel s s ISA Available across a wide range of platforms and integrated into the platforms 2 YEARS Shrink/Derivative Westmere New Microarchitecture Sandy Bridge 32nm Intel AVX

37 Low power for the ExaFlops? peak perf. 1 TF *1000 <= > 1 PF * 1000 <=> 1 Exa Flops power. 100 W (including cooling) 0.1 MW <=> (including cooling) <=> 100 MW (including cooling) nb. cores 1 CPU => 1 K CPU => => => 1M CPU Then - how to use 10 6 «CPU»? - is that the only problem?

38 Memory solutions Heat-sink If we have many tera-ops processors CPU We ll need many TB/s Memory systems DRAM Package Actual Tera - Gain values value Performa 20 1 Tflops ~50 x nce Gflops / / c BW 12 GB/s ~1.2 ~100 x c Latency TB/s cycles ~20 x cycles

39 Parallel computing & Amdhal law Elapsed time Speedup Super linear Linear (theory) Ideal Saturated «try again» 1 c 4 c Nb cores More important than the number of transistor?

40 Serial and // Optimization using Hardware counters

41 Parallel computing & Amdhal law 0 - Serial Optimization Elapsed time Elapsed time 1 - Work on the ovehead 1 c Elapsed time 1 c 4 c 2 - Take advantage of parallelism to run N x bigger workloads?

42 Intel point of view : Emerging application research Workload requirements drive design decisions Cores Cache memory On-die fabric I/o, network, storage Platform firmware Execution Environments Programming Environments Workloads used to validate designs Workloads

43 Questions?

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