C.P.U Organization. Memory Unit. Central Processing Unit (C.P.U) Input-Output Processor (IOP) Figure (1) Digital Computer Block Diagram

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1 C.P.U Organization 1.1 Introduction A computer system is sometimes subdivided into two functional entities "Hardware" and "Software". The H/W of the computer consists of all the electronic components and the electromechanical devices that comprise the physical entity of the device. Computer S/W consists of the instructions and data that the computer manipulates to perform various data processing tasks. Memory Unit Central Processing Unit (C.P.U) Control Unit A.L.U Registers Processor Unit Input Devices Input-Output Processor (IOP) Output Devices Figure (1) Digital Computer Block Diagram 1.2 Some Definitions When dealing with H/W it is customary to distinguish between what is referred to as: Computer Organization: Which is concerned with the way the H/W components operate and the way they are connected to form the computer system. Computer Design: Which is concerned with the determination of what H/W should be used and how these parts should be connected. Computer Architecture: Which is concerned with the structure and behavior of the computer as seen by the user; it includes instruction format, instruction set and techniques or addressing memory. 1

2 1.3 Design of a simple computer The minimum requirements to design a simple computer are the following: 1- Computer Memory. 2- Computer Registers. 3- Arithmetic Logic Shift Unit (ALSU). 4- Common Bus System. 5- Control Unit. 1. Computer Memory: A RAM (random access memory) of size 4096 word of 16-bit, 4K x u, was chosen to the design of a simple computer. This memory was used to store the computer programs. 4KL X 16 Memory Read Write Figure (2) Computer Memory 2. Computer Registers: A simple computer has six registers, the list of registers and it operations are given in table (1) below. A register with parallel load capability was used to construct the simple computer. Table (1) computer register Register Size Description AR 12 Address Register, hold memory address. PC 12 Program Counter, hold instruction address. DR 16 Data Register, hold memory operand. AC 16 Accumulator, it is a processor register. IR 16 Instruction Register, hold instruction code. TR 16 Temporary Register, hold temporary data. 2

3 3. Arithmetic Logic Shift Unit (ALSU): The simple computer also has an ALSU to perform data processing instruction (arithmetic logic and shifting instructions) on the data stored on the Accumulator and data registers. 4. Common Bus System: A common bus was used to ensure the connections between the simple computer memory and registers as shown in figure bellow. The common bus system was constructed with 16Mux of size 8x1 of three selection variables (C2 C1 C0) to determine the output to the bus as shown in table (2). The register whose load (LD) input is enabled receives the data from the bus. Figure (3) Simple Computer Configuration 5. Control Unit: The simple computer has also a hardwired control unit that generate the control signals for the computer register, memory, ALSU, and the common bus system 3

4 Table (2) Bus Control C2 C1 C0 Bus Nothing AR PC DR AC IR TR Memory 4

5 1.2 Instruction of a simple computer Some definitions Computer instruction: is a binary code that specifies a sequence of microoperations for the computer. Instruction code: is a group of bits that instruct the computer to perform a specific operation. Operation: is part of an instruction stored in computer memory. Operation code: is a group of bits that define such operations as add, subtract, multiply, shift, and complement. Instruction word of the simple computer consists of 16-bits; 12-bits are needed to specify the address of the operand in a 4K word memory. This leaves 4-bit for the Opcode field of the instruction as shown in figure bellow Opcode Address Figure (4) Simple Computer Instruction Format The 4-bit Opcode means only 16-instructions can be specified. The simple computer contain ten instructions only which listed in table (3). Although this is not efficient, but by using limited number of instructions, it is possible to show the detailed logic design of the computer without much complexity. Table (3) The Simple Computer Instructions Instruction Code Description Example INC 0000 H Increment AC ACAC+1 CMA 1000 H Complement AC AC- AC Shr 2000 H Shift right AC AC Shr[AC] Shl 3000 H Shift left AC AC Shl[AC] IDA 4000 H Load Memory word to AC AC M[AR] STA 5xxx H Store Content of AC in memory M[AR]AC ADD 6xxx H Add memory word to AC ACAC+DR AND 7xxx H AND Memory word to AC ACAC ^ DR OR 8xxx H OR Memory word to AC ACAC V DR BUN 9xxx H Branch Unconditionally PCDR 5

6 1.2.2 Instruction Cycle A program residing in memory of a computer consists of a sequence of instructions. The program is executed in the computer by going through a cycle for each instruction. Each instruction cycle in turn is subdivided into a sequence of sub cycles or phases. In the simple computer each instruction cycle consist of the phases shown in figure (5) which continue until HALT instruction is occur. Fetch Decode Execute Figure (5) Instruction Cycle 1- The Fetch Phase: the sequence counter (SC) is cleared to 0, provided coming signal T 0. The Program Counter (PC) is loaded with the access of the fast instruction in the program. The fetch phase required two timing signal to complete. T 0 : AR PC T 1 : IR M [AR], PC PC+1 2- The Decode Phase: After fetching the instruction, it must be decoded to determine the type, this performed in the next timing signal T 2. T 2 : D 0,.., D 15 IR (12-15) AR IR (0-11) 3- The Execute Phase: This the last phase during it the instruction is executed and perform its required operation. It start with the timing signal T 3 and when finished clear the Sequence Counter (SC 0) to return to the fetch phase T 0, as shown in figure(4) 6

7 SC 0 AR PC IR M[AR] PC PC+1 Fetch Phase D 0,.., D 15 IR (12-15) AR IR (0-11) Decode Phase Execute the Instruction SC 0 Execute Phase Figure (6) Instruction Cycle Flowchart in a Simple Computer Example: The content of PC in the simple computer is 3AF H. The content of AC is 6EC3 H. The content of memory at address 3AF H is 632E H. The content of memory at address 32E H is 849F H. a. What is the instruction that will be fetched and execute. b. Show the binary operation that will be performed in AC when the instruction is executed. c. Give the contents of registers PC, AR, DR, AC, and IR at the end of instruction cycle. 7

8 Solution T 0 : AR PC T 1 :IR M[AR] PC PC+1 T 2 : D 0,.., D 15 IR (12-15) AR IR (0-11) D 6 T 3 : DR M[AR] D 6 T 4 : ACAC+DR AR=3AF H IR= 632E H D 6 ADD instruction AR= 32E H DR= M[32E H ] = 849F H AC= 6EC3 H + 849F H = F362 H 8