AM57x Sitara Processors Technical Deep Dive

Transcription

1 AM57x Sitara Processors Technical Deep Dive ARM Cortex-A15 Solutions for automation, HMI, vision, imaging, and other industrial and high-performance applications

2 Agenda AM57x Silicon Overview AM57x Processors AM57x Peripherals AM57x System Architecture AM57x EVMs & Tools

3 AM57x Silicon Overview AM57x Sitara Processors Technical Deep Dive

4 AM57x Product Family ARM Cortex-A15 (MHz) C66x DSP (MHz) ARM Cortex-M4 (MHz) Graphics Video Acceleration Display Subsystem PRU-ICSS AM GHz 1.5GHz 750 MHz 750 MHz 213 MHz 213 MHz 3D 3D 2D 1080p Yes PRU-ICSS* (Quad Core) Pin Compatible AM GHz 1.5GHz 750 MHz 750 MHz MHz 213 MHz AM GHz 3D 2D 1080p MHz MHz MHz AM GHz 750 MHz 213 MHz 213 MHz Yes PRU-ICSS* (Quad Core) PRU-ICSS* (Quad Core) PRU-ICSSU* (Quad Core) Software Compatible AM MHz 500 MHz 213 MHz 213 MHz PRU-ICSS* (Quad Core) PRU-ICSS can be used for industrial communication protocols such as Profibus, Profinet RT/IRT, EtherCAT, POWERLINK, Ethernet/IP, and more.** *PRU-ICSS is configured into two dual-core subsystems. **Support for premium protocols such as EtherCAT or POWERLINK requires ordering a specific part.

5 AM572x Cortex -A15-based Processors High-Speed Interconnect 28 nm ARM Cortex-A15 ARM Cortex-A15 32K/32K L1 32K/32K L1 2MB 1MB L2 w/ecc ARM M4 ARM M4 32KB L1 64KB RAM + - * C66x DSP + - * 32K/32K L1 288KB L2 512KB L3 Shared RAM w/ecc 32b DDR3/3L w/ ECC 32b DDR3/3L = = C66x DSP 32K/32K L1 288KB L2 Video Acceleration IVA HD 1080p Video, VPE Graphics Acceleration 3D GPU 2x SGX544 2x24b, 2x8b BB2D GC320 Display Subsystem 3 LCD HDMI 1.4a 1080p Blend/Scale/ Convert Video Input Ports 2x24b, 2x8b 2x16b PRU (Quad Core) Industrial Communication Subsystem (ICSS) EtherCAT,PROFINET, EtherNET/IP, PROFIBUS, POWERLINK, SERCOS 3 Security Acceleration 2 AES, 2 SHA2MD5, DES3DES, RNG System Services EDMA 13 Mailbox RTC SDMA Secure WDT WDT Spinlock 16 Timer KBD 2 DCAN QSPI 10 UART Serial IO 8 McASP 5 I2C 4 McSPI Industrial and Programmable IO 2 PCIe USB3/2 GPIO 3 PWM/CAP/QEP USB2 GbE 2-port switch w/1588 G/MII, RMII, RGMII SATA NAND/ NOR Storage IO 3 SD/SDIO 1 emmc/ SD/SDIO Pin muxing may limit peripheral availability. Bandwidth may limit simultaneous use of peripherals. Not available in AM5726, except VPE

6 AM571x Cortex -A15-based Processors High-Speed Interconnect 28 nm ARM Cortex-A15 32K/32K L1 1MB L2 w/ w/ecc ARM M4 ARM M4 32KB L1 64KB RAM 512KB L3 L3 Shared RAM w/ecc ECC 32b DDR3/3L w/ ECC + - * = C66x DSP 32K/32K L1 288KB L2 Video Acceleration IVA HD 1080p Video, VPE Graphics Acceleration 3D GPU SGX544 BB2D GC320 Display Subsystem 3 LCD HDMI 1.4a 1080p Blend/Scale/ Convert Camera Port 2 x CSI2 Video Input Ports 2x24b, 2x8b PRU (Quad Core) Industrial Communication Subsystem (ICSS) EtherCAT,PROFINET, EtherNET/IP, PROFIBUS, POWERLINK, SERCOS 3 Security Acceleration 2 AES, 2 SHA2MD5, DES3DES, RNG System Services EDMA 13 Mailbox RTC SDMA Secure WDT WDT Spinlock 16 Timer KBD 2 DCAN QSPI 10 UART Serial IO 8 McASP 5 I2C 4 McSPI Industrial and Programmable IO 2 PCIe 3 PWM/CAP/QEP USB3/2 GPIO USB2 GbE 2-port switch w/1588 G/MII, RMII, RGMII SATA NAND/ NOR Storage IO 3 SD/SDIO 1 emmc/ SD/SDIO Pin muxing may limit peripheral availability. Bandwidth may limit simultaneous use of peripherals. Not available in AM5716, except VPE

7 AM57x Package ABC Package: 23 x 23mm, 0.8 pitch, 760-pin BGA package

8 AM57x Processors AM57x Sitara Processors Technical Deep Dive

9 Processors and Memory: ARM Dual (AM572x) / Single (AM571x) ARM Cortex-A15 Up to 1.5 GHz, r2p2 revision core(s), ARMv7-A instructions set Out-of-order instruction dispatch and completion Backward-compatible with code for previous ARM processors Integrated NEON processing engine and VFPv4-compatible hardware Five execution units handle simple instructions, branch instructions, NEON and floating point instructions, multiply instructions, & load and store instructions AM572x has 2MB L2 memory (no ECC), while AM571x has 1MB L2 with ECC

10 Cortex-A15 (AM57x) vs Cortex-A9 (AM437x) Enhancements 128-bit (vs 64) data path 3-inst (vs 2) instruction decode 8-micro-ops (vs 4) issue 64-byte (vs 32) cache line Dual load/store (vs one or other) Improved branch prediction: Higher capacity Support for indirect branches More out-of-order instructions Physically-indexed/tagged L1 cache Tighter integration with NEON/VFP: Faster interworking with ARM code Dual-issue (vs single) Improved memory performance: Tightly-coupled L2 cache to reduce latency 23 to 14 clocks Enhanced auto-prefetch More requests buffering New Features Extended physical addressing Virtualization support: Virtual interrupt controller 2 nd stage MMU for Hypervisor control of guest OS memory CP15 trapping Debug/trace support: Integrated trace Virtualization support AMBA4 bus supports: System coherency MMU coherency Key Benefits Higher single-thread performance: 3.5 vs 2.5 DMIPS/MHz 1.4x higher instructions per cycle (IPC) from enhancements 1.4x faster floating point 10-15% higher clock in same process due to design x faster fully-pipelined cache maintenance support Improved system-level support to support new architecture needs: Larger memory, virtualization, system coherency Cortex-A15 offers substantial enhancements and new features to dramatically increase performance and system-level support.

11 Processors and Memory: M4, DSP, & L3 Dual (AM572x) / Single (AM571x) ARM Cortex-A15 Up to 1.5 GHz, r2p2 revision core(s), ARMv7-A instructions set Out-of-order instruction dispatch and completion Backward-compatible with code for previous ARM processors Integrated NEON processing engine and VFPv4 compatible hardware Five execution units handle simple instructions, branch instructions, NEON and floating point instructions, multiply instructions, & load and store instructions AM572x has 2MB L2 memory (no ECC), while AM571x has 1MB L2 with ECC Dual-ARM Cortex M4s Up to 213 MHz, ARMv7-M and Thumb -2 ISAs w/ ARMv6 SIMD & DSP extensions Dual (AM572x) / Single (AM571x) C66x DSPs Up to 750MHz, fixed- and floating-point ISA Object code compatible with C64x+ and C674x DSPs Advanced VLIW architecture w/ two multiplier units and six arithmetic logic units operating in parallel L3 Memory with ECC AM572x has 2.5MB of L3 memory with ECC AM571x has 512 KB of L3 memory with ECC AM5728 diagram shown

12 Processors and Memory: PRU-ICSS Programmable Real-Time Unit Industrial Communication Subsystem (PRU-ICSS) (2) Dual 32-bit RISC cores 12KB program RAM, 8 KB data RAM per CPU 32KB shared RAM Interrupt controller Fast IO interface Programming Tools PRU C-compiler for PRU firmware ARM Linux remoteproc + rpmsg driver PRU debugger in CCS Peripherals: One Ethernet MII_RT module with two MII ports * One MDIO port * One Industrial Ethernet peripheral * and Industrial Ethernet timer 1 x compatible UART 1 x ecap Capable of supporting master and/or slave modes of protocols such as: Profinet, Ethernet IP, Profibus, Ethercat, Powerlink, and Sercos 3 * Use of these ports is only supported via TI Processor SDK RTOS.

13 PRU-ICSS Feature Comparison AM18x/ Features OMAPL138 AM335x AM437x AM571x AM572x (SR1.1) PRUSS PRU-ICSS1 PRU-ICSS1 PRU-ICSS0 2 x PRU-ICSS 2 x PRU-ICSS PRU core version Number of PRU cores Max frequency CPU freq / MHz 200 MHz 200 MHz 200 MHz 200 MHz IRAM size (per PRU core) 4 KB 8 KB 12 KB 4 KB 12 KB 12 KB DRAM size (per PRU core) 512 B 8 KB 8 KB 4 KB 8 KB 8 KB Shared DRAM size KB 32 KB -- 32KB 32KB General purpose input (per PRU core) Direct Direct; or 16-bit parallel capture; or 28-bit shift Direct; or 16-bit parallel capture; or 28-bit shift; or 3ch EnDat 2.2; or 9ch Sigma Delta Direct; or 16-bit parallel capture; or 28-bit shift; or 3ch EnDat 2.2; or 9ch Sigma Delta Direct; or 16-bit parallel capture; or 28-bit shift; or 3ch EnDat 2.2; or 9ch Sigma Delta Direct; or 16-bit parallel capture; or 28-bit shift; General purpose output (per PRU core) Direct Direct; or Shift out Direct; or Shift out Direct; or Shift out Direct; or Shift out Direct; or Shift out GPI Pins (PRU0, PRU1) 30, 30 17, 17 13, 0 20, 20 21*, 21 21, 21 GPO Pins (PRU0, PRU1) 32, 32 16, 16 12, 0 20, 20 21*, 21 21, 21 MPY/MAC N Y Y Y Y Y Scratchpad N Y (3 banks) Y (3 banks) N Y (3 banks) Y (3 banks) CRC16/ INTC Peripherals n/a Y Y Y Y Y UART ecap not pinned out 1 1 IEP not pinned out 1 1 MII_RT not pinned out 2 2 MDIO not pinned out 1 1 Simultaneous protocols 1 1 2** 2 * PRU-ICSS2 only. PRU-ICSS1 does not pin out the PRU0 core GPIs/GPOs. ** 2 nd protocol limited to EnDAT/Profibus/BISS/HIperphase DSL or serial based protocol

14 AM57x Peripherals AM57x Sitara Processors Technical Deep Dive

15 Video and Graphics Video Acceleration IVA HD 1080p Video, VPE Graphics Acceleration 3D GPU 2x SGX544 BB2D GC320 AM5728 diagram shown. Not available in AM57x6, except VPE. Video Acceleration (same for AM572x and AM571x) IVA (image and video accelerator) HD-based video processing solution. Sometimes this is called HDVICP. Up to 1080p60 decode and 1080p30 encode support for MPEG4 and H.264 Single-channel encode support (1080p30, D1, and QVGA) Graphics Acceleration Dual (AM572x) / Single (AM571x) Imagination SGX544 3D graphics engine Up to 532 MHz API support for OpenGL ES1.1 & 2.0 Tile-based architecture reduces access to external memory Vivante Corporation GC320 2D graphics accelerator API support for OpenWF, DirectFB, and GDI/DirectDraw Also supports BitBlt, StretchBlt, blending, and transparency

16 Display Subsystem 2x24b, 2x8b Display Subsystem 3 LCD HDMI 1.4a 1080p Blend/Scale/ Convert Video Input Ports 2x24b, 2x8b 2x16b Display Subsystem Three LCD outs supporting MIPI DPI 2.0, BT-656, or BT-1120, each with dedicated overlay manager HDMI output supporting up to 1080p with a dedicated overlay manager One graphics, three video, and one write-back pipelines Maximum display resolution up to 1920x1200 NOTE: Simultaneous use of multiple displays will reduce maximum resolution subject to DDR bandwidth and graphics layers. AM5728 diagram shown. Not available in AM57x6.

17 Dual Camera Serial Interface 2 (CSI2) Display Subsystem 3 LCD HDMI 1.4a 1080p Blend/Scale/ Convert Camera Port 2 x CSI2 Video Input Ports 2x24b, 2x8b AM5718 diagram shown. Not available in AM57x6. Display Subsystem Three LCD outs supporting MIPI DPI 2.0, BT-656, or BT-1120, each with dedicated overlay manager HDMI output supporting up to 1080p with a dedicated overlay manager One graphics, three video, and one write-back pipelines Maximum display resolution up to 1920x1200 NOTE: Simultaneous use of multiple displays will reduce maximum resolution subject to DDR bandwidth and graphics layers Dual-Camera Serial Interface 2 (CSI2) (AM571x) Two ports compliant with MIPI CSI-2 1.0, MIPI D-PHY RX 1.0 Port A: Four data lanes Port B: Two data lanes

18 Video Input Ports (VIP) Display Subsystem 3 LCD HDMI 1.4a 1080p Blend/Scale/ Convert Video Input Ports (VIP) Each VIP supports 2-input independent stream parser slices VIP1 and VIP2 slice can handle two streams - Port-A: 8/16/24-bit options - Port-B: 8-bit only VIP3 slice can handle one stream - Port-A: 8/16-bit options NOTE: AM571x only supports VIP1 2x24b, 2x8b Video Input Ports 2x24b, 2x8b 2x16b AM5728 diagram shown. Not available in AM57x6.

19 AM57x Serial Peripherals DCAN (2) Support bit rates up to 1Mbit/s and are compliant to CAN2.0B protocol specification Multichannel Audio Serial Port Interface (McASP) (8) Two instances support 16 channels w/ independent TX/RX clock sync domains Six instances support 4 channels w/ shared TX/RX clock sync domains QSPI Master-only interface primarily intended for fast booting from quad-spi flash memories Supports single, dual or quad reads. Only single writes are supported. 2 DCAN Serial IO 8 McASP I2C (5) Slave or master configurable Two I2C ports support Fast mode (up to 400 Kbps) Three I2C ports support HS mode (up to 3.4 Mbps) Universal Asynchronous Receiver Transmitters (UART) (10) Baud rates up to Mbps One with extended modem control signals (DCD, RI, DTR, DSR) One with IrDA Multichannel Serial Port Interface (McSPI) (4) Function as master or slave Each supports up to four external device (four chip selects) or one external master QSPI 10 UART 5 I2C 4 McSPI

20 Industrial Programmable I/Os: PWMSS & GPIO Three PWMSS (Pulse-Width Modulation Subsystems) ehrpwm: High Resolution PWM 2x PWM outputs with single-/dual-edge symmetric/asymmetric operation Only ehrpwm[x]a supports the High-Resolution PWM feature 1x Trip Zone Input for reacting to external fault conditions ehrpwm1 has Time Base Synchronization I/Os (internally daisy-chained to other modules) Industrial and Programmable IO ecap: Capture 1x Capture Input with 4-event time-stamp registers Used for measuring audio sample rate, rotating machinery speed, position sensor pulses Can optionally be configured as a single channel PWM output eqep: Quadrature Encoded Pulse Used to measure the angular position or motion of a shaft or axle (for example, volume knob) 2x Quadrature Inputs, 1x Index Input, 1x Strobe Input GPIOs AM572x up to 247 GPIOs; AM571x up to 215 GPIOs Divided amongst 8x GPIO modules (muxed on most LVCMOS device pins) 2 PCIe USB3/2 GPIO 3 PWM/CAP/QEP USB2 GbE 2-port switch w/1588 G/MII, RMII, RGMII

21 Industrial Programmable I/Os: PCI Express (PCIe) PCI Express (PCIe) (2) Supports Gen I (2.5GT/s) and Gen II (5GT/s) modes AM57x has 2x PCIe lanes* supporting two configurations: 1) One Controller with 2 lanes 2) Two Controllers with 1 lane each * On AM571x, use of Lane 1 is mutually exclusive with USB SuperSpeed mode Supported features: Root Complex and Endpoint modes Single Function in Endpoint mode Optional traffic mapping through dedicated MMU2 Single Virtual Channel (VC) and Traffic Class (TC) Unsupported features: Power states L2 (w/beacon) and D3 cold Built-in hot plug Addressing modes other than incremental for bursts Outbound transactions involving less than 4 bytes Supports the following maximum payload sizes 128-byte outbound payload size (limited by EDMA) 256-byte inbound payload size USB SS * PCIE_SS1 PCIE_SS2 Control Module Lane 0 Lane 1

22 Industrial Programmable I/Os: USB USB (2) (USB 3.0/2.0 x1; USB 2.0 x1) Two xhci USB Controllers with different configurations: Standard Line Rate PHY USB Port 1 (USB1) USB 3.0 5Gbps Internal SS (USB3.0) PHY and Internal HS/FS (USB2.0) PHY USB Port 2 (USB2) USB Mbps Internal HS/FS PHY On AM571x, use of USB SuperSpeed mode is mutually exclusive with lane of second PCIe. All xhci Controllers support: Host or Peripheral mode (Dual-Role-Device (DRD)) DRVVBUS (Drive-VBUS) output signal to External Charge Pump for VBUS 5V generation No support for the following: Full OTG (Software-based Role Switching still possible) Attached Detection Protocol (ADP), ACA ID pin (if desired, must be implemented by an external GPIO)

23 Industrial Programmable I/Os: Ethernet Ethernet Internal Gb Ethernet Switch with 3 ports: 2 External Ethernet Ports 1 Internal Local Host Port External Interface support: RMII/MII (10/100Mbps) at 3.3V RGMII (10/100/1000*Mbps) at 1.8V/3.3V Single MDIO interface for PHY Control Clocking: MII/RMII: Supports both internal and external 50MHz reference clock RGMII: Internal clock reference only No support for: GMII interface 2.5V Signaling * AM572x errata Ethernet RGMII2 limited to 10/100 Mbps. Refer to device errata for impacted silicon revisions.

24 Storage I/Os: SATA SATA Single Port SATA host controller supporting 1.5-Gbps and 3-Gbps speeds (SATA-1 and SATA-2) Supports multiple drives with a port multiplier: command-based switching only (Issuing commands to only one drive at a time) Dedicated sata1_led pin for Activity LED generation Storage IO No support for the following: ATA legacy mode of operation Cold presence detection for hot-plug operation Message signaled interrupts Far-end Analog Loopback Port Multiplier FIS-based switching SATA NAND/NOR 3 SD/SDIO 1 emmc/ SD/SDIO

25 Storage I/Os: emcc/sd/sdio emmc / SD / SDIO (4) Four controllers with different configurations: Data Bus Primary Support Max Frequency* IO Buffer Type DMA MMC1 4-bit SD 192 MHz (via DLL) UHS1 Master & Slave MMC2 8-bit emmc 192 MHz (via DLL) LVCMOS Master & Slave MMC3 8-bit SDIO / SD 96 MHz LVCMOS Slave MMC4 4-bit SDIO / SD 48 MHz LVCMOS Slave Full compliance with standards: JC64 MMC/eMMC standard specification, v4.5 SD Physical Layer specification v3.01 SD part E1 specification v3.00 (SDIO) SD card specification Part A2 v3.00 No support for: * AM572x errata MMC1/2/3 write speed limited. Refer to device errata for impacted silicon revisions. MMC POW output pin: Must utilize chip level GPIO for this function, if desired.

26 Storage I/Os: GPMC & ELM General Purpose Memory Controller (GPMC) Used for accessing SRAM, NOR, NAND, etc. 8/16-bit data at up to 88MHz Non-muxed, Address-Data muxed, and Address-Address-Data muxed modes Async mode with read page access Sync mode with burst access and wrap capability 8 chip-selects covering 512MB of address space GPMC Error Locator Module (ELM) Used when interfacing GPMC to a NAND device Provides 4-, 8- or 16-bit error location over a 512-Byte block based on BCH algorithms Allows detected errors and their locations in the NAND block to be retrieved by the processor when the PAGE_VALID interrupt is generated

27 Storage I/Os: EMIF & DMM External Memory Interface (EMIF) Number EMIF Controllers ECC Addressable SDRAM size Chip Selects AM572x Dual EMIF1 only Up to 2GB per controller 1 per controller AM571x Single Yes Up to 4 GB * 2 16-/32-bit DDR3/ DDR3L support Speeds up to 533MHz (DDR-1066) Hardware-leveling support Class of Service and burst priority counter MPU MA has 128-bit direct path with optimized latency to each of EMIF0/1 * if using stacked die package Dynamic Memory Management (DMM) Performs global address translation and address rotation (tiling) between L3_MAIN Interconnect and EMIFs Performs access interleaving between EMIFs

28 System Peripherals Enhanced DMA (EDMA) Supports two simultaneous read and two simultaneous write physical channels Up to 64 programmable logical channels Mailbox (13) 13 for the MPU, DSP, IPU, and PRU; 1 for IVA Number of users, number of messages in the queue Real-Time Clock (RTC): RTC-only low power mode not supported System DMA (SDMA): Up to 128 hardware requests, 32 prioritizable logical channels, and bit FIFO dynamically allocable between active channels Watchdog Timer: Free-running 32-bit upward counter (runs off of 32kHz system clock) Spinlock: 256 hardware semaphores between the MPU, DSP, and IPU Timer (16): Free-running 32-bit upward counter. Runs off 32KHz or system clock Keyboard Controller (KBD): Supports up to 9x9 Keypads System Services EDMA 13 Mailbox RTC SDMA Secure WDT WDT Spinlock 16 Timer KBD

29 AM57x System Architecture AM57x Sitara Processors Technical Deep Dive

30 Pad Configuration Requirements In order to guarantee the IO Timings in the AM57x Data Manual over the lifetime of the device, AM57x software shall implement the proper pad configuration requirements. Pad configuration settings that impact IO timings include: Slew Control Settings Virtual IO Timing Modes Manual IO Timing Modes (default values must be used) Proper pad configuration procedure includes: IO Isolation: Required to guarantee IO state when changing IO settings IO Delay Recalibration: Required to guarantee timings after AVS changes The AM57x Data Manual lists the pad configuration requirements to achieve the various timing modes of operation. The TRM Pad Configuration Section provides the details on implementing the pad configuration requirements.

31 Virtual IO Timing Modes Virtual IO Timing Modes are pre-defined IO timing settings that are coded in the Device ROM. Selection of Virtual Modes is done via the Pad Configuration Registers. This is described in AM57x TRM section Virtual IO Timing Modes. Below is an example of how Virtual IO Timing Modes are defined in the AM57x Data Manual:

32 Manual IO Timing Modes Manual IO Timing Modes are IO timing settings that must be calculated and programmed by system software based on seed values in the datasheet. Application of Manual IO Timing Modes is done via the CFG_x_IN, CFG_x_OEN, and CFG_x_OUT registers in the IODELAYCONFIG Module. This is described in the AM57x TRM section Manual IO Timing Modes. Below is an example of how Manual IO Timing Modes seed values are defined in the AM57x Data Manual:

33 IO Isolation Mode Any changes to the Pad Configuration Registers or IODELAYCONFIG registers can potentially result in an undesirable state (i.e., output state changes or output enable changes) on the associated IOs. To guarantee IO state, device pins should be placed in Isolation Mode when making any changes to the Pad Configuration Registers or IODELAYCONFIG Module Registers. Run-time (non-isolated) changes are only supported for MMC. See TRM section Isolation Requirements for details.

34 Customer Software Implications All I/O timing modes and pinmuxing shall be set by software At boot-time While under protection of isolation While executing code from OCMCRAM (since DDR cannot be accessed while IOs are in isolation) The Secondary Boot Loaders (just after ROM bootloader) execute from OCMC RAM. The MLO in the Linux eco-system operates from the OCMC RAM. Therefore the MLO/ SBL is the ideal place for pad configurations. Run-time changes are needed for MMC where dynamic configurations can not be avoided. TI has validated this use case. IO Delay support is included in the AM57xx Pin Mux Tool (PMT). NOTE: In order to guarantee the IO timings in the AM57x Data Manual over the lifetime of the device, AM57x software shall implement the proper pad configuration requirements.

35 AM57x Boot Booting devices include: NOR flash memory or other XIP device NAND flash memories (non-xip) Removable SD card device emmc memory device 1-bit SPI flash memories (QSPI_1) 4-bit (Quad) SPI flash memories (QSPI_4) SATA-compatible devices Solid state drives (SSDs) Hard-disk drives (HDDs) USB: HS USB 2.0 interface UART: UART interface Initial boot order comes from sysboot pins.

36 Interrupt & Event Controller Crossbar Each core or DMA can only supports a static number of interrupt/event inputs. Each core interrupt controller and each DMA event handler is preceded by an Interrupt Controller or DMA Crossbar mux. Crossbar allows any peripheral interrupt/event to be mapped to a core or DMA. Mapping of peripheral interrupt/event selections is the same for each crossbar instance to allow software consistency. All peripherals Repeated for each IRQ of each CPU core (similar for events/dma)

37 AM57x EVMs & Tools AM57x Sitara Processors Technical Deep Dive

38 AM57x Development Tools AM572x Evaluation Module (EVM) BeagleBoard-X15 AM57x Industrial Development Kit (IDK) COMING SOON General Availability Oct 15 Late 4Q15 1Q16 Sold and Supported by TI BeagleBoard.org TI Processor Memory AM5728 2GB DDR3L 4GB emmc micro SD AM5728 2GB DDR3L 4GB emmc micro SD AM5728 AM571x 1Q16 1GB DDR3L 32MB QSPI / 16 GB emmc micro SD Display Yes, Capacitive Touch Size: 7, 800 x 480 None Yes, Capacitive Touch Size: 10, 1080p Key Features USB 3.0/2.0, e/msata, HDMI, 2x Gb Ethernet, Audio in/out, WiLink8 connector, Camera, PCIe & Peripheral Expansion USB 3.0/2.0, esata, HDMI, 2x Gb Ethernet, Audio in/out, & Peripheral Expansion Full ICSS access (x4), ADC, ECC DDR support, HDMI, Camera Software Linux, Android*, TI-RTOS** Linux, TI-RTOS** TI-RTOS, RT Linux*** *Supplied via third party: would not ship with kit **Available via download: target 4Q15 *** Available via download: target 1Q16

39 AM572x Evaluation Module (EVM) Processor board based on BeagleBoard-X15 Sitara AM5728 processor TPS power management 2GB DDR3L 4GB emmc Micro SD card 3x USB 3.0 HUB USB 2.0 (micro) Full size HDMI connector esata connector 2Gb Ethernet ports Audio input/output 20-pin ARM JTAG Included accessories Quick Start Guide HDMI cable USB-to-Serial debug cable Micro SD card with Processor SDK Power LED Camera board 3Mp sensor 7 LCD Display (WVGA - 800x480) Capacitive touch screen Bottom side of LCD board minipcie connector msata connector WiLink 8 connector User buttons Processor board Plugs in via expansion connectors in the back *Power supply not included

40 AM572x Power Solutions TPS is the Power Management IC (PMIC) that shall be used for the Device designs. TI requires use of this PMIC for the following reasons: TI has validated its use with the device. Board level margins including transient response and output accuracy are analyzed and optimized for the entire system. Support for power sequencing requirements (refer to Section 5.8 Power Supply Sequences in the AM57x datasheet) Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software TPS Power Supply TPS configured for the AM572x EVM TPS configured for the AM572x IDK SMPS1/2 vdd_mpu vdd_mpu SMPS3 DDR Memory DDR Memory SMPS4/5 vdd_dspeve, vdd_gpu, vdd_iva vdd_dspeve SMPS6 vdd vdd_gpu SMPS7 SW configuration after boot vdd SMPS8 vdds18v vdd_iva SMPS9 SW configuration after boot 3.3V vddshvx

41 AM571x Power Solutions TPS65916 or TPS is the Power Management IC (PMIC) that shall be used for the Device designs. TPS Power Supply TPS configured for the AM571x IDK TPS65916 Power Supply Generic TPS65916 configuration for AM571x SMPS1/2 vdd_mpu SMPS1 vdd_mpu SMPS3 DDR Memory SMPS2 vdd SMPS4/5 vdd_dsp SMPS3 vdd_dsp, vdd_gpu, vdd_iva SMPS6 vdd_gpu SMPS4 vdds18v SMPS7 vdd SMPS5 DDR Memory SMPS8 vdd_iva SMPS9 3.3V

42 Thermal Considerations Thermal management ensures that every silicon device on the board works within its allowable operating junction temperature. Failure to maintain a junction temperature within the range specified reduces operating lifetime, reliability, and performance. The product design cycle should include thermal analysis to verify the operating junction temperature of the device is within functional limits. If the temperature is too high, componentor system-level thermal enhancements are required to dissipate the heat from the system.

43 AM572/1x Layout Compatibility AM572x & AM571x are designed as layout compatible solutions. AM572/1x Compatibility Guide application note walks through differences: Feature differences Hardware considerations Pin compatibility Software impact PMIC compatibility Example differences: Same multiplexings for all common features Features/signals removed or added in AM571x New added pin muxings in AM571x IVA/DSP must run at same OPP when AM571x populated (unless special population hooks) Some special powers swap, must treat them the same (same filtering/handling)

44 For More Information For information about AM57x: For more training related to Sitara and AM57x: For questions about this training, refer to the E2E Sitara Processors Forum: