VELAMMAL COLLEGE OF ENGINEERING & TECHNOLOGY DEPARTMENT OF INFORMATION TECHNOLOGY QUESTION BANK

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1 VELAMMAL COLLEGE OF ENGINEERING & TECHNOLOGY Viraganoor, Madurai. DEPARTMENT OF INFORMATION TECHNOLOGY QUESTION BANK IV SEMESTER EC6504-MICROPROCESSOR AND MICROCONTROLLER Regulation 2013 Academic Year Prepared by Ms.B.Saravanya, APIII/IT

2 VELAMMAL COLLEGE OF ENGINEERING & TECHNOLOGY, MADURAI. DEPARTMENT OF INFORMATION TECHNOLOGY QUESTION BANK SUBJECT : Microprocessor and Microcontroller YEAR/SEM : II/IV UNIT I - THE 8086 MICROPROCESSOR Introduction to 8086 Microprocessor architecture Addressing modes - Instruction set and assembler directives Assembly language programming Modular Programming - Linking and Relocation - Stacks - Procedures Macros Interrupts and interrupt service routines Byte and String Manipulation. Course Course Outcome statement Blooms Outcome Level CO1 Explain and implement programs on 8086 microprocessor K2 PART A S.No Questions K-Level Competence 1 List down the functional parts of 8086 CPU K1 Remember 2 What are the primary objective of 16 bit microprocessor? K1 Remember 3 Explain the functionality of BIU? 4 Explain the functionality of Execution unit? 5 What is the purpose of AX register? K1 Remember 6 What is the purpose of BX register? K1 Remember 7 What is the purpose of CX register? K1 Remember 8 What is the purpose of DX register? K1 Remember 9 Explain about code segment register? 10 Explain stack segment register 11 Explain about Data segment register 12 What is the purpose of extra segment register K1 Remember 13 List down the pointers and index registers of 8086 micro K1 Remember 14 List the flags of 8086 microprocessor K1 Remember 15 Illustrate the flag register format 16 Explain about CY and AC in 8086 flag register 17 Explain about PF, ZF and SF in 8086 flag register 18 What is control flag? Explain about Trap Flag in 8086 K1 Remember microprocessor. 19 Compare Interrupt flag and Direction flag in 8086 microprocessor 20 List the types of addressing modes in 8086 microprocessor K1 Remember 21 Explain Immediate addressing mode with an example 22 Explain Register addressing mode with an example 23 What is direct addressing mode? Give an example K1 Remember Prepared by B.Saravanya, APIII/IT Page 1

3 24 What is Register indirect addressing mode? Give an K1 Remember example 25 Explain string addressing mode with an example 26 What is implied addressing mode? Give an example K1 Remember 27 What are the types of instruction set available in 8086 K1 Remember microprocessor 28 What is data copy/transfer instructions? Give an example K1 Remember 29 Explain the following instruction with an example : (i) PUSH (ii) POP 30 How MOV and XCHG instruction is used in 8086 K1 Remember microprocessor? Give an example 31 Compare IN and OUT instruction of 8086 microprocessor 32 Define stack. K1 Remember 33 What are the advantages of memory segmentation? K1 Remember 34 Explain LEA instruction with an example 35 Compare LDS and LES instruction with an example 36 List down the flag transfer instructions with an example K1 Remember 37 List down the arithmetic instructions of 8086 K1 Remember microprocessor 38 Compare ADD and ADC mnemonic with an example 39 Explain the functionality of INC and DEC instruction with an example 40 What is the function of NEG instruction? Explain with K1 Remember example 41 Which mnemonic is used to compare the source operand K1 Remember with destination operand? Explain it with an example 42 Explain the following instruction with an example: (i) MUL (ii) IMUL 43 Explain the difference between CBW and CWD instructions with an example 44 What is the function of DIV instruction of 8086 K1 Remember microprocessor? 45 How ASCII coded operands are processed in 8086 K1 Remember microprocessor? Explain with example 46 Compare DAA and DAS instruction of 8086 microprocessor with an example 47 List down the logical instructions of 8086 microprocessor K1 Remember 48 Explain the functionality of TEST instruction of 8086 microprocessor with an example 49 Summarize the shift instructions of 8086 microprocessor 50 Explain the function of SHR, SAR instruction with a suitable example 51 Write the syntax for SHL/SAL instruction with a brief explanation 52 List down the rotate instructions of 8086 microprocessor K1 Remember 53 Explain the syntax associated with rotating all bits in a specified byte or word of 8086 microprocessor 54 What is the purpose of RCL & RCR instruction of 8086 K1 Remember Prepared by B.Saravanya, APIII/IT Page 2

4 microprocessor 55 What is the difference between loop and branch instruction. K1 Remember Explain it with an example 56 Summarize the function of instruction involved in loop process 57 Explain the types of branch instructions of 8086 microprocessor 58 Compare RET and IRET instruction with an example 59 Compare INT and INTO instruction with an example 60 Explain the difference between CALL and JMP instruction with an example 61 Explain the function of following instruction (i) JO Label (ii) JNO Label (iii) JS label (iv) JNS Label 62 Explain the function of following instruction (i) JZ/JE Label (ii) JNZ/JNE Label (iii) JP label (iv) JNP Label 63 What is the difference between JB and JNB instruction of K1 Remember 8086 microprocessor? 64 Summarize the functions of string manipulation instruction of 8086 microprocessor 65 List down the string manipulation instruction of 8086 K1 Remember microprocessor 66 What is the purpose of REP string instruction of 8086 K1 Remember microprocessor 67 Explain MOVSB/MOVSW instruction with an example 68 Recall the function of CMPS instruction with an example K1 Remember 69 What is the function of SCAN instruction of 8086 K1 Remember microprocessor 70 Compare LODS and STOS instruction with an example 71 List down the functionality of each flag manipulation K1 Remember instruction used in 8086 microprocessor 72 Recall the machine control instruction set used in 8086 K1 Remember microprocessor 73 Define Assembler directive K1 Remember 74 Recall the importance of the following assembler directives: K1 Remember INCLUDE & END 75 What do you mean by Segment Override Prefix? K1 Remember 76 Recall the differences between an assembler directive and instruction. 77 Explain the use of the following assembler directives: DD, ASSUME, EQU. 78 What is the use of DB directive? Explain it with an K1 Remember example 79 Recall the purpose of DW directive with an example K1 Remember 80 Compare DQ and DT assembler directive with an example 81 Relate the following directive with an example (i) END (ii) ENDP (iii) ENDS 82 Define the directive used to align the memory address used K1 Remember Prepared by B.Saravanya, APIII/IT Page 3

5 in 8086 microprocessor with an example 83 When EXTRN directive is used in 8086 microprocessor? K1 Remember Explain it with an example 84 List down the function of GROUP assembler directive K1 Remember 85 Recall the function of LABEL assembler directive in 8086 K1 Remember microprocessor 86 Explain the function of following assembler directive: (i) LENGTH (ii) LOCAL 87 What are the functions of ORG assembler directive used in 8086 microprocessor 88 Explain PROC directive with an example 89 Explain the functions of PTR directive with an example 90 Recall the use of PUBLIC directive in 8086 microprocessor K1 Remember 91 Compare SEG and SEGMENT assembler directive used in 8086 microprocessor 92 List the use of SHORT assembler directive with an K1 Remember example 93 Explain the function of following assembler directive with an example (i) TYPE (ii) GLOBAL 94 Explain an 8086 ALP to convert BCD data to Binary data 95 Explain an 8086 ALP to add two 8 bit numbers 96 Explain an 8086 ALP to subtract two 8 bit numbers 97 Explain an 8086 ALP to multiply two 8 bit numbers 98 Explain an 8086 ALP to divide 16 bit number by 8 bit number 99 Explain an 8086 ALP to subtract two 16 bit numbers 100 Explain about loader and linker? 101 Recall the concept of relocation K1 Remember 102 How segments are combined? K1 Remember 103 Explain the different segment combination types used in 8086 microprocessor 104 Define the need for modular programming K1 Remember 105 Compare Procedure and Macro. 106 Define recursive procedures K1 Remember 107 Explain macro with its syntax 108 What is the need for local label K1 Remember 109 Recall the address in the interrupt vector table which is used K1 Remember for a Type-2 interrupt in What is interrupt? How it is classified? K1 Remember 111 What is the difference between software and hardware K1 Remember interrupt? 112 What are vectored and non-vectored interrupt? K1 Remember 113 What is masking? Why it is required? K1 Remember 114 What is vectoring? K1 Remember 115 What is exception? Give examples? K1 Remember 116 How many interrupts are available in 8086? How are they classified? K1 Remember Prepared by B.Saravanya, APIII/IT Page 4

6 117 How interrupts are initiated in 8086? K1 Remember 118 List the INTEL predefined interrupts? K1 Remember 119 What are the maskable and non maskable interrupts of 8086? K1 Remember 120 What is vector table? Where it is located? K1 Remember 121 How interrupt address is generated in 8086? K1 Remember 122 Find the physical address, when segment address is 1085H K1 Remember and effective address is 4537H. 123 How the 2 byte INT instruction can be applied for K1 Remember debugging. 124 Name the different types of interrupts supported in K1 Remember 125 Explain the sources of interrupts? 126 Illustrate the organization of interrupt vector table in What is type 1 interrupt? K1 Remember 128 List down the advantages of modular programming K1 Remember 129 List down the disadvantages of modular programming K1 Remember Relate physical address and offset address used in microprocessor Find the physical address when CS=5300 H and IP=0200H. K1 Remember 131 Write the starting and ending address of coding segment Find out the physical address when ES is 6500H and offset K1 Remember 132 address is 4767H What is the content of data segment DS to locate the K1 Remember 133 physical address 43657H? assume the content of IP = 2057H How 8086 instruction set is classified based on number of K1 Remember 134 bytes? 135 Define one byte instructions? Give examples K1 Remember 136 List down the examples of two byte instructions of 8086 K1 Remember 137 Explain about three byte and four byte instruction of Explain about five byte and six byte instruction of 8086 PART B & C S.No Questions K-Level Competence Explain the internal architecture of 8086 microprocessor 139 with a neat diagram Explain the various types of addressing modes used in microprocessor with an example Summarize the functions of various data transfer/copy 141 instructions of 8086 microprocessor Explain about arithmetic and logical instructions of microprocessor How shift and rotate operations is carried out in microprocessor? Explain it in detail Summarize about loop and branch instructions used in microprocessor with an example 145 Explain about string instructions in detail 146 Explain about processor control instructions used in 8086 Prepared by B.Saravanya, APIII/IT Page 5

7 microprocessor (i) What is assembler directive (ii) Explain various assembler directive used in 8086 K1 K2 Remember Understand 147 microprocessor Explain an ALP for decimal addition of two 16 bit number 148 with a clear algorithm and neat flowchart Explain an ALP to find out the largest number from a string 149 of bytes with a neat flowchart Explain an ALP to find out the largest number from a string 150 of words with a neat flowchart Explain an ALP to transfer a block of data from one section 151 of memory to other section of memory with a neat flow chart Explain an ALP to arrange a string of words in a descending 152 order with a neat flowchart Explain an ALP to arrange a string of words in a ascending 153 order with a neat flowchart Explain an ALP to find out the gray code equivalent of a 154 binary number with a neat flowchart Explain an ALP to convert a BCD number to equivalent 155 binary number with a neat flowchart Explain an ALP to find factorial of a BCD number with a 156 neat flowchart Explain an ALP to find out the number of positive numbers and negative numbers in a series of signed numbers with a 157 neat flow chart Explain an ALP to find out the number of even numbers and odd numbers in a series of signed numbers with a neat 158 flowchart Explain an ALP to convert binary number to equivalent 159 BCD number with a neat flowchart 160 (i) What is linker and loader? (ii) Explain the concept of Linking and relocation in detail K1 K2 Remember Understand 161 (i) What is the need for stack and illustrate it. (ii) Explain the functions of stack & its instructions in detail K1 K2 Remember Understand 162 (i) What is procedure? (ii) Explain the requirements of procedures in detail K1 K2 Remember Understand (i) Define Interrupt and mention its types (ii) Explain the sequence involved in Interrupt service K1 K2 Remember Understand 163 routine in detail 164 Explain about MACRO in detail 165 Explain about string instructions in detail 166 Summarize the use of REP prefix with a suitable example 167 Explain the hierarchy of text editor with a neat illustration 168 Explain the process involved in converting the table and number format in detail. Prepared by B.Saravanya, APIII/IT Page 6

8 APTITUDE S.No Question Answer 1 The first microprocessor was (d) 4004 (a) 4001 (b) 4002 (c) 4003 (d) The 64-bit processor is (d) Pentium 4 (a) Pentium (b) Pentium II (c) Pentium III (d) Pentium 4 3 The operating frequency of 8086 microprocessor is about (c) 5-10 MHz (a) 750 KHz (b) 3-6 MHz (c) 5-10 MHz (d) 3-6 GHz 4 A microcontroller has (se (a) ROM (b) RAM (c) I/O Ports (se 5 The 8086 has (a) 16 bit data bus and 20 bit address bus (b) 8 bit data bus and 20 bit address bus (a) 16 bit data bus and 20 bit address bus (c) 16 bit data bus and 16 bit address bus (d) 8 bit data bus and 16 bit address bus 6 The 16 bit register of 8086 microprocessor consist of (c) 9 flags (a) 16 flags (b) 8 flags (c) 9 flags (d) 7 flags 7 The instruction queue of 8086 consist of (a) 6 data (a) 6 data (b) 8 data (c) 4 data (d) 10 data 8 The 8086 has memory segments (c) 4 (a) 6 (b) 8 (c) 4 (d) 10 9 The physical memory of 8086 is (a) 1 MB (a) 1 MB (b) 64 KB (c) 2 MB (d) 4 MB 10 The segment memory capacity of 8086 is (b) 64 K (a) 1 MB (b) 64 K (c) 2 MB (d) 4 MB has the following units: (a) EU and BIU (a) EU and BIU (b) EU only (c) BIU only (d) CU and BIU 12 Physical address of 8086 is (c) 20-bit (a) 8-bit (b) 16-bit (c) 20-bit (d) 32-bit 13 The physical address when DS = 2345H and IP=1000H is (b) 24450H (a) 23450H (b) 24450H (c) 12345H (d) 2345H 14 What is the addressing mode of the instruction MOV AX, [BX]? (a) Register direct (b) Register indirect (c) immediate addressing (b) Register indirect (d) indirect addressing 15 What is the addressing mode of the instruction MOV AX, [BX+SI+06]? (a) Index addressing (b) Base addressing (c) Base index addressing (d) Base index displacement addressing 16 Which of the following instructions is immediate addressing? (a) MOV AX,[2000] (b) MOV BX, 2000 (c) MOV AX,[SI] (d)mov AX,BX 17 Which of the following instruction is base with 16 bit displacement addressing? (a) MOV AX,[BX+06] (b) MOV AX,[BP+2000] (c) MOV AX,[BP+06] (d) MOV AX,[BP] (d) Base index displacement addressing (b) MOV BX, 2000 (b) MOV AX,[BP+2000] 18 Which of the following instruction is a four byte instruction (d) ADD Prepared by B.Saravanya, APIII/IT Page 7

9 (a) MOV AX, 2345 (b) MUL BX (c) DIV CL (d) ADD AX,[BP+0200] 19 Which of the following is a six byte instruction (a) MOV [BX+DI+0200],2345 (b) MOV [SI],5665 (c) DIV CL (d) ADD BX, [BP+0200] 20 Which of the following instruction is a logical instruction? (a) DIV AB (b) TEST (c) CALL (d) AAM 21 Which of the following instruction affects carry flag? (a) RCR (b) MUL AB (c) JZ (d) INC AX 22 Which of the following instruction is an arithmetic instruction? (a) DIV AB (b) ROR (c) STI (d) WAIT 23 The example of string instruction is (a) MOV DX,[SI] (b) XLAT (c) MOVSB (d) AAD 24 Which of the following is not true? (a) MOV [2000],[4000] (b) MOV AX,[2000] (c) MOV [2000],AX (d) MOV AX,BX 25 2 s complement instruction is (a) NEG (b) NOT (c) CMP (d) CMC 26 Direction flag is used with which of the following instructions? (a) Data transfer (b) Branch control (c) String (d) Logical 27 Which of the following instruction does not allow the interrupt request signal to interrupt the instruction which follows NOP? (a) ESC (b) HALT (c) WAIT (d) LOCK 28 Which of the following instruction is used to read a string of bytes and send it to another memory location? (a) SCASB (b) MOVSB (c) LODSB (d) REP 29 A procedure can be called using the instruction (a) JMP (b) CALL (c) RET (d) INT n 30 Which of the following register combination is used with LODSB instruction? (a) ES:SI (b) ES:DI (c) DS:SI (d) DS:DI 31 When PUSH instruction is executed, initially (a) upper byte of data is stored on stack and SP=SP-1 (b) upper byte of data is stored on stack and SP=SP+1 (c) lower byte of data is stored on stack and SP=SP-1 (d) lower byte of data is stored on stack and SP=SP+1 32 Coprocessor control instructions are (a) WAIT, LOCK, ESC (b) HALT, STC, CLC (c) ROR, RCR, ROL (d) DAA 33 What is output of DL after execution of following instruction? MOV DL,36 AND DL,0F (a) 06H (b) 60H (c) 36H (d) 0FH 34 What is the content of AX and DX after execution of the following instructions? MOV BL,9 AX,[BP+0200] (a) MOV [BX+DI+0200],2345 (b) TEST (a) RCR (a) DIV AB (c) MOVSB (a) MOV [2000],[4000] (a) NEG (c) String (b) HALT (b) MOVSB (b) CALL (c) DS:SI (a) upper byte of data is stored on stack and SP=SP-1 (a) WAIT, LOCK, ESC (a) 06H (b) 0008H, 0009H Prepared by B.Saravanya, APIII/IT Page 8

10 MOV AX,0702 AAD DIV BL (a) 0080H, 0009H (b) 0008H, 0009H (c) 0008H, 0090H (d) 0800H, 0900H 35 What is the result after executing the following instruction? MOV AX,0037 ADD AX,0033 AAA OR AX,3030 (a) 3031 (b) 1303 (c) 3130 (d) After multiplication of two numbers, the result in AX will be MOV AL,05 MOV CL,05 MUL CL AAM (a) 0205 (b) 0250 (c) 0025 (d) Which one of the following program is correct for finding the complement of a number (a) MOV AX,2345 NEG AX (b) MOV AX,2345 CMP AX (c) MOV AX,2345 NOT AX (d) MOV AX,2345 CMC 38 The result of unsigned multiplication of two numbers is MOV CL,25 MOV AL,35 MUL CL (a) 7A90H (b) 907AH (c) A907H (d) 07A9H 39 The result of addition of two numbers is MOV AX,A233 MOV BX,A455 ADD AX,BX (a) 4688H (b) 4886H (c) 8846H (d) 6884H 40 Content of AL after executing the following instruction is MOV AH, 06H MOV AL,06H MOV BL,08H SUB AX,BX (a) 08 (b) FE (c) F8 (d) After execution of MOV AX,9535 and RCL AX,1 the content of AX is (a) 2A6A, carry=0 (b) 2A6A, carry =1 (c) A26A, carry = 1 (d) 2AA6, carry = 1 (c) 3130 (a) 0205 (c) MOV AX,2345 NOT AX (d) 07A9H (a) 4688H (b) FE (b) 2A6A, carry =1 42 If the following instructions are executed (a) 54D5, carry = 0 Prepared by B.Saravanya, APIII/IT Page 9

11 MOV CL,02 MOV AX,9535 RCL AX,CL Result of AX register will be (a) 54D5, carry = 0 (b) 54D5, carry = 1 (c) 45D5, carry = 0 (d) 45D5, carry=1 43 After execution of following instruction, the content of AX register is MOV AL,07 MOV BL,09 MUL BL (a) 0063 (b) 003F (c) 6300 (d) 3F00 44 If the following instruction are executed MOV CX,55 MOV AX,3545 DIV CX Then (a) Quotient AL=15, remainder AH =H0 (b) Quotient AL=0A, remainder AH =51 (c) Quotient AL=A0, remainder AH =15 (d) Quotient AL=A0, remainder AH =51 45 When MOV BX,2467 and ADD BX, 4 instruction are executed, the result will be (a) 2468 (b) 246A (c) 246D (d) 246B 46 2 s complement of AX is (a) NEG AX (b) NOT AX (c) CMP AX (d) XOR AX 47 The content of AX after execution of MOV AX,3957 and NOT AX is (a) C68A (b) 6CA8 (c) CA86 (d) C6A8 48 If a number of instructions are repeating through the main program, then to reduce the length of the program, is used. a) procedure b) subroutine c) macro d) none of the 49 The process of assigning a label or macroname to the string is called a) initialising macro b) initialising string macro c) defining a string macro d) defining a macro 50 A macro within a macro is called a) macro-within-macro b) nested macro c) macro-in-macro d) none of the 51 A macro can be defined at a) beginning of a program b) end of a program c) after initialisation of program d) anywhere in a program 52 A macro can be used as a) in data segment b) to represent directives c) to represent statements 53 The end of a macro can be represented by the directive. a) END b) ENDS c) ENDM d) ENDD (b) 003F (c) Quotient AL=A0, remainder AH =15 (d) 246B (a) NEG AX (d) C6A8 c) macro d) defining a macro b) nested macro d) anywhere in a program c) ENDM Prepared by B.Saravanya, APIII/IT Page 10

12 54 The time required for execution of a macro is that of procedure. a) greater than b) less than c) equal to d) none of the 55 Which of the following statements is incorrect? a) complete code of instruction string is inserted at each place, wherever the macroname appears b) macro requires less time of execution than that of procedure c) macro uses stack memory d) macroname can be anything except registers and mnemonics 56 The beginning of the macro can be represented as a) START b) BEGIN c) MACRO d) None of the 57 While programming for any type of interrupt, the interrupt vector table is set a) externally b) through a program c) either externally or through the program d) externally and through the program 58 Procedures are also known as a) macros b) segment c) subroutines d) none 59 The technique that is used to pass the data or parameter to procedures in assembly language program is by using a) global declared variable b) registers c) stack 60 If a procedure is interactive, then a) it accepts inputs directly from input devices b) it uses global declared variable technique c) it uses stack d) it uses memory locations 61 For passing the parameters to procedures using the PUBLIC & EXTRN directives, it must be declared PUBLIC in the a) subroutine b) procedure c) main routine d) main routine and subroutine 62 The technique to estimate the size of an executable program, before it is assembled and linked is a) memory location technique b) global variable technique c) stack d) none 63 The interrupt for which the processor has highest priority among all the external interrupts is a) keyboard interrupt b) TRAP c) NMI d) INT 64 The interrupt for which the processor has highest priority among all the internal interrupts is a) keyboard interrupt b) TRAP c) NMI d) INT 65 In case of string instructions, the NMI interrupt will be served only after a) initialisation of string b) execution of some part of the string c) complete string is manipulated d) the occurrence of the interrupt 66 The INTR signal can be masked by resetting the a) TRAP flag b) INTERRUPT flag c) MASK flag d) DIRECTION b) less than c) macro uses stack memory c) MACRO c) either externally or through the program c) subroutines a) it accepts inputs directly from input devices c) main routine d) none c) NMI b) TRAP c) complete string is manipulated b) INTERRUPT flag Prepared by B.Saravanya, APIII/IT Page 11

13 flag 67 The status of the pending interrupts is checked at a) the end of main program b) the end of all the interrupts executed c) the beginning of every interrupt d) the end of each instruction cycle 68 Once the processor responds to an INTR signal, the IF is automatically a) set b) reset c) high d) low 69 If an interrupt is generated from outside the processor then it is an a) internal interrupt b) external interrupt c) interrupt d) none of the 70 If the interrupt is generated by the execution of an interrupt instruction then it is a) internal interrupt b) external interrupt c) interrupt-in-interrupt d) none of the 71 Example of an external interrupt is a) divide by zero interrupt b) keyboard interrupt c) overflow interrupt d) type2 interrupt 72 Example of an internal interrupt is a) divide by zero interrupt b) overflow interrupt c) interrupt due to INT 73 The interrupt request that is independent of IF flag is a) NMI b) TRAP c) Divide by zero d) All of the 74 The type of the interrupt may be passed to the interrupt structure of CPU from a) interrupt service routine b) stack c) interrupt controller d) none of the 75 During the execution of an interrupt, the data pushed into the stack is the content of a) IP b) CS c) PSW d) All of the 76 After every response to the single step interrupt the flag that is cleared is a) IF (Interrupt Flag) b) TF (Trap Flag) c) OF (Overflow Flag) d) None of the 77 At the end of ISR, the instruction should be a) END b) ENDS c) IRET d) INTR 78 When the CPU executes IRET, a) contents of IP and CS are retrieved b) the control transfers from ISR to main program c) clears the trap flag d) the end of each instruction cycle b) reset b) external interrupt a) internal interrupt b) keyboard interrupt c) interrupt controller b) TF (Trap Flag) c) IRET a) contents of IP and CS are retrieved Prepared by B.Saravanya, APIII/IT Page 12

14 d) clears the interrupt flag 79 While CPU is executing a program, an interrupt exists then it a) follows the next instruction in the program b) jumps to instruction in other registers c) breaks the normal sequence of execution of instructions d) stops executing the program 80 NMI stands for a) non maskable interrupt b) non multiple interrupt c) non movable interrupt d) none of the 81 The INTR interrupt may be masked using the flag a) direction flag b) overflow flag c) interrupt flag d) sign flag 82 The stack pointer register contains a) address of the stack segment b) pointer address of the stack segment c) offset of address of stack segment d) data present in the stack segment 83 The stack segment register contains a) address of the stack segment b) base address of the stack segment c) pointer address of the stack segment d) data in the stack segment 84 PUSH operation a) decrements SP b) increments SP c) decrements SS d) increments SS 85 POP operation a) decrements SP b) increments SP c) decrements SS d) increments SS 86 In the instruction, ASSUME CS : CODE, DS : DATA, SS : STACK the ASSUME directive directs to the assembler the a) address of the stack segment b) pointer address of the stack segment c) name of the stack segment d) name of the stack, code and data segments 87 When a stack segment is initialised then a) SS and SP are initialised b) only SS is initialised c) only SP is initialised d) SS and SP need not be initialised 88 The number of PUSH instructions and POP instructions in a subroutine must be a) PUSH instructions must be greater than POP instructions b) POP instructions must be greater than PUSH instructions c) Both must be equal d) Instructions may be any kind c) breaks the normal sequence of execution of instructions a) non maskable interrupt c) interrupt flag c) offset of address of stack segment b) base address of the stack segment a) decrements SP b) increments SP d) name of the stack, code and data segments a) SS and SP are initialised c) Both must be equal 89 The Stack follows the sequence c) last-in-first-out Prepared by B.Saravanya, APIII/IT Page 13

15 a) first-in-first-out b) first-in-last-out c) last-in-first-out d) last-in-last-out 90 If the processor is executing a main program that calls a subroutine, then after executing the main program up to the CALL instruction, the control will be transferred to a) address of main program b) subroutine address c) address of CALL instruction d) none of the 91 The Stack is accessed using a) SP register b) SS register c) SP and SS register d) None of the 92 As the storing of data words onto the stack is increased, the stack pointer is a) incremented by 1 b) decremented by 1 c) incremented by 2 d) decremented by 2 93 While retrieving data from the stack, the stack pointer is a) incremented by 1 b) incremented by 2 c) decremented by 1 d) decremented by 2 94 The coded object modules of the program to be assembled are present in a).asm file b).obj file c).exe file d).object file 95 The advantages of assembly level programming is a) flexibility of programming is more b) chances of error are less c) debugging is easy 96 The extension that is essential for every assembly level program is a).asp b).alp c).asm d).pgm 97 The extension file that is must for a file to be accepted by the LINK as a valid object file is a).obj file b).exe file c).masm file d) DEBUG file 98 The directive that updates the location counter to the next even address while executing a series of instructions is a) EVN b) EVEN c) EVNE d) EQU 99 The directive that directs the assembler to start the memory allotment for a particular segment/block/code from the declared address is a) OFFSET b) LABEL c) ORG d) GROUP 100 The recurrence of the numerical values or constants in a program code is reduced by a) ASSUME b) LOCAL c) LABEL d) EQU b) subroutine address c) SP and SS register d) decremented by 2 b) incremented by 2 b).obj file c).asm a).obj file b) EVEN c) ORG d) EQU 101 The labels or constants that can be used by any module in the c) GLOBAL Prepared by B.Saravanya, APIII/IT Page 14

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17 UNIT II SYSTEM BUS STRUCTURE 8086 signals Basic configurations System bus timing System design using 8086 IO programming Introduction to Multiprogramming System Bus Structure - Multiprocessor configurations Coprocessor, Closely coupled and loosely Coupled configurations Introduction to advanced processors. Course Course Outcome statement Blooms Outcome Level CO2 Demonstrate the system bus structure K2 PART A S.No Questions K-Level Competence Compare and contrast maximum mode and minimum mode 1 configuration of 8086 microprocessor 2 Illustrate the pin diagram of 8086 microprocessor 3 What is the function of AD15-AD0 pins of 8086? K1 Remember 4 What is the function of A16/S3 and A17/S4 pins of 8086? K1 Remember 5 Recall the function of A18/S5 pin of 8086? K1 Remember 6 How A19/S6 pin of 8086 works? K1 Remember 7 Explain the function of BHE/S7 pin of What is the function of A19-A6 pins of 8086? K1 Remember 9 Recall the purpose of RD pin of 8086 K1 Remember 10 How READY pin f 8086 works? K1 Remember 11 What is the function of INTR pin of 8086? K1 Remember 12 Relate TEST pin and WAIT instruction K1 Remember 13 What is the use of NMI pin of 8086? K1 Remember 14 What is the purpose of MN/MX pin of 8086 K1 Remember 15 Why RESET pin is used in 8086? K1 Remember 16 What is the function of CLK pin in 8086? K1 Remember 17 List the pins used in minimum mode configuration of 8086 K1 Remember Explain the pin associated with interrupt acknowledge of What is purpose of ALE pin of 8086? K1 Remember 20 Recall the function of DEN pin of 8086? K1 Remember 21 Explain the function of DT/R pin of Recall the function of WR pin of 8086 pin K1 Remember 23 Relate the function of HOLD and HLDA pin of 8086? K1 Remember 24 List the pins used in maximum mode configuration of 8086 K1 Remember 25 What is the purpose of QS0 and QS1 pins of 8086 K1 Remember 26 List down the functions of S2, S1, S0 pins of 8086 K1 Remember 27 Explain the function of LOCK pin of What is the purpose of RQ/GT0 and RQ/GT1 pins of 8086 K1 Remember 29 Illustrate the memory read bus cycle timing diagram of 8086 for minimum mode configuration Prepared by B.Saravanya, APIII/IT Page 16

18 Illustrate the memory write bus cycle timing diagram of for minimum mode configuration Illustrate the memory read bus cycle timing diagram of for maximum mode configuration Illustrate the memory write bus cycle timing diagram of for maximum mode configuration Illustrate bus request and bus grant timing diagram in 33 minimum mode configuration of 8086 Illustrate the bus request and bus grant timing diagram in 34 maximum mode configuration of Explain the types of I/O programming 36 What is DMA? K1 Remember 37 What is polling? K1 Remember Illustrate the machine language code for IN and OUT 38 instruction 39 What is double buffering? K1 Remember Illustrate the I/O handling by operating system with a neat 40 diagram 41 What is Programmed I/O? K1 Remember Illustrate the interface for programmed I/O with a neat 42 diagram 43 Explain about Interrupt I/O Explain the sequence when interrupt request is recognized in microprocessor Explain the methods of prioritization of interrupt system in Illustrate the daisy chain arrangement with a neat diagram List down the sequence occurs when datum is sent from the K1 Remember 47 interface to the memory 48 List down the advantages of loosely coupled configuration K1 Remember 49 Illustrate the polling method with a neat diagram Illustrate the independent request method with a neat 50 diagram 51 Illustrate the sequence of closely coupled configuration 52 Explain how 8086 is synchronized with its coprocessor 53 Illustrate the machine language code for ESC instruction 54 List down the salient features of microprocessor K1 Remember 55 Explain the concept of virtual memory 56 How register is organized? K1 Remember Illustrate the flag register format of microprocessor 57 with a neat diagram 58 Define MSW K1 Remember 59 List down the functional blocks of microprocessor K1 Remember 60 How interrupts are classified? Explain it K1 Remember 61 What is single step interrupt in 80286? K1 Remember 62 How interrupts are prioritized in microprocessor K1 Remember 63 What is the function of PEREG and PEACK pin of K1 Remember Prepared by B.Saravanya, APIII/IT Page 17

19 64 Recall the function of BUSY and ERROR pin of K1 Remember 65 What is the function of CAP pin in microprocessor? K1 Remember 66 List down the salient feature of microprocessor K1 Remember 67 How functional units is divided? Explain it K1 Remember Illustrate the functional units of microprocessor with 68 a neat diagram 69 Illustrate the block diagram of microprocessor 70 Explain the various modes of How memory is organized and segmented in K1 Remember 72 Explain about register set of microprocessor 73 Illustrate the flag register format of microprocessor 74 List down the instruction set of microprocessor K1 Remember 75 Recall the salient features of Pentium processor K1 Remember 76 Define machine cycle K1 Remember 77 Define T-state K1 Remember 78 Define processor or machine cycle K1 Remember 79 What is instruction cycle? K1 Remember 80 What is fetch and execute cycle? K1 Remember 81 What is interrupt acknowledge cycle K1 Remember 82 What is bus? List down its types? K1 Remember 83 What is cycle stealing? K1 Remember 84 What are the advantages of independent bus request scheme? K1 Remember 85 What is multiprogramming K1 Remember What are the states of process in multiprogramming? 86 Illustrate the state transition diagram 87 Define semaphore K1 Remember 88 Compare closely and loosely coupled configuration 89 What are the advantages of multiprocessor configuration K1 Remember What is coprocessor? How does it identify the instruction K1 Remember 90 meant for it? 91 What is bus arbiter? List down its functions K1 Remember PART B & C S.No Questions K-Level Competence Explain the pin configuration of 8086 microprocessor in 92 detail Explain the functions performed by 8086 in minimum mode 93 configuration with a neat pin diagram Explain the functions performed by 8086 in maximum mode 94 configuration with a neat pin diagram Explain the system bus timing for minimum mode 95 configuration of 8086 Explain the system bus timing for maximum mode 96 configuration of Summarize the types of I/O data transfer in detail 98 Explain about Programmed I/O in detail Prepared by B.Saravanya, APIII/IT Page 18

20 How data is transferred using Interrupt I/O?Explain the 99 Interrupt Priority methods with a neat diagram 100 Explain the sequences involved in DMA process 101 Explain about multiprocessor configurations in detail 102 Summarize about coprocessor configuration in detail 103 Interpret about closely coupled configuration in detail What are the advantages of loosely coupled configuration? 104 Explain it in detail 105 Explain about multiprogramming in detail Explain the architecture and salient features of microprocessor Explain the internal architecture and pin diagram of microprocessor 108 Explain the salient features of Pentium with a neat block diagram APTITUDE S.No Question Answer 1 Which of the following is an incorporated function to resolve interprocessor communication problems? a) bus allotment and control b) bus arbitration c) priority resolving 2 The device that deals with the bus access control functions and bus handshake activities is a) bus allotment controller b) bus arbiter c) priority resolver d) none of b) bus arbiter the 3 The clock generator delays the READY signal until the signal goes low a) DEN (active high) b) DEN (active low) c) AEN (active low) d) AEN (active high) 4 The bus controller relinquishes the bus if a) READY (active low) b) LOCK (active high) c) CBRQ (active low) d) BPRO (active high) 5 The signals that are used by the bus arbitration in the independent request method is a) BREQ (active low) b) BPRN (active low) c) CBRQ (active low) d) All of the 6 The signal that is used to drive a priority resolving network that actually accepts the bus request inputs is a) BREQ (active low) b) BPRN (active low) c) CBRQ (active low) d) BPRO (active low) 7 Which of the following is the simplest and cheapest method of bus arbitration? a) daisy chaining b) independent request c) polling d) none of the 8 Which of the following is the fastest method of bus arbitration? a) daisy chaining b) independent request c) polling d) none of the c) AEN (active low) b) LOCK (active high) d) All of the a) BREQ (active low) a) daisy chaining b) independent request Prepared by B.Saravanya, APIII/IT Page 19

21 9 A set of address lines is driven by the controller in a) daisy chaining b) independent request c) polling d) none of the 10 The processors used in the multimicroprocessor are a) coprocessors b) independent processors c) coprocessors or independent processors d) none of the 11 The processor that executes the instructions fetched for it by the host processor is a) microprocessor b) coprocessor c) independent processor d) coprocessor and independent processor 12 The processor that asks for bus access or may itself fetch the instructions and execute them is a) microprocessor b) coprocessor c) independent processor d) coprocessor and independent processor 13 In tightly coupled systems, the microprocessors share a) common clock b) bus control logic c) common clock and bus control logic d) none of the 14 Communication between processors using a common system bus and common memory takes place in a) loosely coupled system b) tightly coupled system c) tightly and loosely coupled system d) none of the 15 The bus arbitration is handled by an external circuit in a) loosely coupled system b) tightly coupled system c) tightly and loosely coupled system d) none of the 16 The loosely coupled system has an advantage of a) more number of CPUs can be added b) system structure is modular c) more fault-tolerant and suitable for parallel applications 17 In a tightly coupled system, when a processor is using the bus then the local bus of other processors is in a) hold state b) high impedance state c) halt state d) low impedance state 18 The disadvantage of loosely coupled system is a) complex due to additional hardware b) less portable c) more expensive 19 To indicate the completion of task allocated in a closely (tightly) coupled system, the microprocessor uses a) status bit in memory b) interrupts the host c) status bit in memory or interrupts the host d) clock pulse 20 The is able to address the physical memory of a) 8 MB b) 16 MB c) 24 MB d) 64 MB 21 The is able to operate with the clock frequency of a) 12.5 MHz b) 10 MHz c) 8 MHz 22 The management of the memory system required to ensure the smooth execution of the running process is done by a) control unit b) memory c) memory management unit d) bus interface c) polling c) coprocessors or independent processors b) coprocessor c) independent processor c) common clock and bus control logic b) tightly coupled system a) loosely coupled system b) high impedance state c) status bit in memory or interrupts the host b) 16 MB c) memory management unit Prepared by B.Saravanya, APIII/IT Page 20

22 unit 23 The fetching of program from secondary memory to place it in physical memory, during the execution of CPU is called a) mapping b) swapping in c) swapping out d) pipe lining 24 The process of making the physical memory free by storing the portion of program and partial results in the secondary storage called a) mapping b) swapping in c) swapping out d) pipe lining 25 The memory that is considered as a large logical memory space, that is not available physically is a) logical memory b) auxilary memory c) imaginary memory d) virtual memory 26 Memory management deals with a) data protection b) unauthorized access prevention c) segmented memory 27 The memory management and protection mechanisms are disabled when the is operated in a) normal mode b) real address mode c) virtual address mode 28 The memory management and protection mechanisms are enabled with advanced instruction set when is operated in a) normal mode b) real address mode c) virtual address mode 29 The is an upward object code compatible with 8086 or 8088 when operated in a) normal mode b) real address mode c) virtual address mode d) real and virtual address mode 30 The CPU of contains a) 16-bit general purpose registers b) 16-bit segment registers c) status and control register 31 The bits that are modified according to the result of the execution of logical and arithmetic instructions are called a) byte addressable bit b) control flag bits c) status flag bit d) none of the 32 The flags that are used for controlling machine operation are called a) status flags b) control flags c) machine controlled flags 33 The additional field that is available in is a) I/O Privilege field b) nested task flag c) protection enable 34 The unit that is responsible for calculating the address of instructions, and data that the CPU wants to access is a) bus unit b) address unit c) instruction unit d) control unit 35 The process of fetching the instructions in advance, and storing in the queue is called b) swapping in c) swapping out d) virtual memory b) real address mode c) virtual address mode d) real and virtual address mode c) status flag bit b) control flags b) address unit c) instruction pipelining Prepared by B.Saravanya, APIII/IT Page 21

23 a) mapping b) swapping c) instruction pipelining d) storing 36 The CPU must flush out the prefetched instructions immediately following the branch instruction in a) conditional branch b) unconditional branch c) conditional and unconditional branches d) none of the 37 The device that interface and control the internal data bus with the system bus is a) data interface b) controller interface c) data and control interface d) data transreceiver 38 The register bank of Execution Unit of is used as a) for storing data b) scratch pad c) special purpose registers 39 Which of the following is not an interrupt generated by 80286? a) software interrupts b) hardware or external interrupts c) INT instruction d) none of the 40 For which of the following instruction does the return address point to instruction causing exception? a) divide error exception b) bound range exceeded exception c) invalid opcode exception 41 The instruction that comes into action, if the trap flag is set is a) maskable interrupt b) non-maskable interrupt c) single step interrupt d) breakpoint interrupt 42 The interrupt that has the highest priority among the following is a) Single step b) NMI (non-maskable interrupt) c) INTR d) Instruction exception 43 The interrupt that has the lowest priority among the following is a) Processor extension segment overrun b) INTR c) INT instruction d) NMI 44 The LOCK (active low) is activated automatically by hardware using a) XCHG signal b) Interrupt acknowledge c) Descriptor table access d) All of the 45 The pin that is used to insert wait states in a bus cycle is a) WAIT b) BHE (active low) c) READY (active low) d) WAIT(active low) 46 To filter the output, a 0.047microfarads, 12V capacitor is connected between the pins a) CAP and ground b) Output pin and ground c) CAP and Vcc d) NMI and ground 47 The signal that causes the to perform the processor extension interrupt while executing the WAIT and ESC instructions is a) BUSY (active low) b) PEACK (active low) c) PEREQ d) ERROR (active low) 48 In real addressing mode, the addresses a physical memory of a) 16 MB b) 8 MB c) 2 MB d) 1 MB 49 The reserves fixed area of physical memory for a) system initialization b) interrupt vector table c) system initialization and interrupt vector table b) unconditional branch d) data transreceiver d) none of the c) single step interrupt d) Instruction exception c) INT instruction d) All of the c) READY (active low) a) CAP and ground d) ERROR (active low) d) 1 MB c) system initialization and interrupt vector table Prepared by B.Saravanya, APIII/IT Page 22

24 d) none of the 50 In the real mode, the memory that is reserved for interrupt vector table is a) first 2 KB of memory b) first 1 KB of memory c) last 2 KB of memory d) last 1 KB of memory 51 In the real mode, the memory that is reserved for system initialization is a) from 004FFH to 0FFFFH b) from 004FFH to 05FFFH c) from FFFF0H to FFFFFH d) from FFF00H to FFFFFH 52 When is reset, it always starts its execution in a) protected virtual addressing mode b) real addressing mode c) either real or protected virtual address modes d) none of the 53 The in real addressing mode performs a) initialization of IP b) enables interrupts c) sets up descriptor table 54 In real address mode, while addressing the physical memory, the uses the signal a) HLDA b) BHE (active low) c) CAP d) HOLD 55 The procedure of fetching the chosen program segments or data from the secondary storage into the physical memory is a) mapping b) swapping c) unswapping d) pipe lining 56 The ability of to address the virtual memory per task is a) 1MB b) 1GB c) 1TB d) none of the 57 The descriptors that are used for subroutines and interrupt service routines are a) data segment descriptors b) gate descriptors c) code segment descriptors d) system segment descriptors 58 A descriptor is used to carry out a) transfer of control b) task switching c) to store privilege level and segment limit 59 The descriptor that is used for special system data segments, and control transfer operations is a) data segment descriptors b) gate descriptors c) code segment descriptors d) system segment descriptors 60 A code segment descriptor contains a) 16-bit segment limit b) first 1 KB of memory c) from FFFF0H to FFFFFH b) real addressing mode b) BHE (active low) b) swapping b) 1GB b) gate descriptors d) system segment descriptors Prepared by B.Saravanya, APIII/IT Page 23

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26 UNIT III I/O Interfacing Memory Interfacing and I/O interfacing - Parallel communication interface Serial communication interface D/A and A/D Interface - Timer Keyboard /display controller Interrupt controller DMA controller Programming and applications Case studies: Traffic Light control, LED display, LCD display, Keyboard display interface and Alarm Controller. Course Course Outcome statement Blooms Outcome Level CO3 Develop I/O interfacing with 8086 Microprocessor K2 PART A S.No Questions K-Level Competence 1 How 8086 memory is divided? Explain it K1 Remember 2 List down the procedure for memory interfacing K1 Remember What is the need for I/O interfacing? Mention the methods K1 Remember 3 of interfacing used in Compare Memory mapped I/O and I/O mapped I/O in 8086 K1 Remember Recall the advantages and disadvantages of memory mapped K1 Remember 5 I/O used in 8086 Recall the advantages and disadvantages of I/O mapped I/O K1 Remember 6 used in What are the requirements to be satisfied by I/O interface? K1 Remember 8 What is programmable peripheral interface? K1 Remember List down the features of 8255A programmable peripheral K1 Remember 9 interface 10 Illustrate the pin configuration of 8255A interface 11 Explain the modes of operation of What are the operating modes of port A of 8255? K1 Remember 13 What are the operating modes of port C of 8255? K1 Remember 14 Explain the working of handshake input port 15 Explain the working of handshake output port 16 Illustrate the control word format of What are the types of I/O modes in 8255 K1 Remember 18 What is the function of mode 0 in 8255 K1 Remember 19 Explain the salient features of Mode 1 of Recall the features of mode 2 of 8255 interface 21 Explain the registers used in serial communication interface 22 Explain the types of serial communication interface Compare asynchronous and synchronous serial 23 communication 24 What is USART? K1 Remember 25 What are the salient features of 8251A PCI? K1 Remember 26 Explain the operating modes of 8251A PCI 27 Illustrate the functional block diagram of 8251A USART 28 What is the function of read/write control logic of 8251 K1 Remember Prepared by B.Saravanya, APIII/IT Page 25

27 USART 29 Recall the function of transmitter section of 8251 K1 Remember 30 List down the function of receiver section of 8251 USART K1 Remember 31 What is the function of modem control of 8251 USART 32 Illustrate the mode word format of 8251 with a neat sketch Illustrate the command word format of 8251 with a neat 33 sketch What information can be obtained from the status word of 8251? Illustrate the status word format of 8251 USART 36 What is the function of programmable interval timer? 37 List down the features of INTEL Illustrate the pin diagram of INTEL Illustrate the functional block diagram of INTEL Illustrate the control word format of Illustrate the read back control word format of Illustrate the status word format of List down the operating modes of 8254 K1 Remember 44 What is the function of mode 0 of 8254 K1 Remember 45 List down the function of mode 1 of 8254 K1 Remember 46 Explain the function of mode 2 of Recall the function of mode 3 of 8254 K1 Remember 48 Compare mode 4 and mode 5 of What is the function of GATE signal in timer 8254? K1 Remember What will be the frequency of the square wave generated by K1 Remember 50 a 8254 timer in mode-3? 51 What are the tasks involved in keyboard interface? K1 Remember List down the seven segment display code of 0,1,2,3,4 for K1 Remember 52 common cathode LED List down the seven segment display code of 5,6,7,8,9 for K1 Remember 53 common cathode LED List down the seven segment display code of 0,1,2,3,4 for K1 Remember 54 common anode LED List down the seven segment display code of 5,6,7,8,9 for K1 Remember 55 common anode LED 56 Recall the features of INTEL 8279 K1 Remember 57 Illustrate the pin diagram of INTEL Explain about keyboard section of INTEL 8279 List down the salient features of display section of INTEL K1 Remember What is the function of scan section of INTEL 8279? K1 Remember List down the functions of CPU interface section of INTEL K1 Remember Illustrate the control word format for write display RAM of Explain the control word format of display write inhibit/blanking of 8279 Prepared by B.Saravanya, APIII/IT Page 26