DESIGN AND IMPLEMENTATION OF SDR SDRAM CONTROLLER IN VHDL. Shruti Hathwalia* 1, Meenakshi Yadav 2

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1 ISSN IJESR/November 2014/ Vol-4/Issue-11/ Shruti Hathwalia et al./ International Journal of Engineering & Science Research DESIGN AND IMPLEMENTATION OF SDR SDRAM CONTROLLER IN VHDL ABSTRACT Shruti Hathwalia* 1, Meenakshi Yadav 2 1 Dept. of EECE, ITM University, Gurgaon, Haryana, India. 2 Asst Prof, Dept. of EECE, ITM University, Gurgaon, Haryana, India. With the ongoing advancements in the present VLSI industry System-on-Chip (SoC) is allowed to integrate multiple complex functions into a single chip, but still demand a single and shared main off-chip SDRAM for data storage. Consequently, the main memory controller has become an important factor in determining the overall system performance. It is a tough job to choose a memory controller that meets the exact demands of the whole system design. The Single Data Rate (SDR) SDRAM controller is to receive read and write requests, to generate the proper commands and to control the data bus of SDRAM. A 32-bit length Linear Feedback Shift Register (LFSR) is generates random number patterns automatically and those patterns are fed to the SDRAM and stored in it. The core controller then performs read/write operations to access the data stored in the memory banks. The core also performs all initialization and refresh functions. In this paper, we emphasised the designing of SDRAM controller architecture and its interfacing with LFSR and SDR SDRAM. The design is described using VHDL language and simulations, resource utilization and power analysis are done in Xilinx ISE 14.5 and Modelsim 10.1b. Keywords: SDR SDRAM, Controller, LFSR. 1. INTRODUCTION 1.1 Overview The (SDR) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability. SDR SDRAM is faster than the predecessors EDO RAM & FPM RAM which took typically 2-3 clocks to transfer 1 word of data. DRAM controller is basically used for controlling the functionality of the SDRAM for data fetching in a system design. The controller acts as a local interface between the host and SDRAM. As, a 32- bit Linear feedback shift register (LFSR) is chosen as the host which generates random number patterns and those patterns are entered into memory for storage. 1.2 Motivation Designing any SDRAM controller is dependent on the logic that is associated with the command timing and execution. SDRAMs are not straightforward devices. This paper deals with the designing a 32 bit length Linear Feedback Shift Register (LFSR) which is considered as host that generates random number patterns and those patterns are accepted by the SDRAM controller using a simple local interface and translate them to the command sequences required by SDR SDRAM devices. Although, the Single Data Rate (SDR) is quite old generation of SDRAM but it is still used on some embedded platforms because its interfacing with the controller and other peripherals is simple, allowing implementation not needing too much focus on the peculiarities of the signal integrity and write/read levelling needed in latest generations of SDRAM. 1.3 Applications Applications of LFSRs also include generating pseudo-random numbers, pseudo-noise sequences, fast digital counters, and whitening sequences. SDRAM controller with LFSR interfacing is intended for embedded applications, cryptography, bank security, digital consumer applications etc. Also, SDRAM is considered as the core component that is used in high speed processing of large volumes of data. Therefore, SDRAM is used for *Corresponding Author 799

2 the computer s main memory, and is actually the more common RAM found in PCs. There are many more applications of SDRAM and LFSR in our day- to day life. 2. SDRAM CONTROLLER 2.1 SDRAM Controller Architecture The general purpose of the SDRAM Controller is to control the Synchronous Dynamic Random Access Memory (SDRAM) access. It gets the memory access requests from Memory controller via several types of ports such as: Read ports, Write ports and Read/Write ports. Then it schedules them to achieve high throughput/low latency. Finally it forwards them to SDRAM. The SDRAM controller is capable of either 16-bit or 32-bit data path, and supports byte, half-word and word access. Bursts can be used for both write and read access. The SDRAM controller is said to be the most important connecting link between the SDRAM and the User requesting to read/write from the SDRAM. The controller must keep complete detailed history of the SDRAM in order to handle the request of the Host correctly on time. This includes: a) All currently active rows and banks in the SDRAM. b) Operations that were not finished in the SDRAM and the cycles remaining. c) The current state of the SDRAM. Each request of the host is accepted and handled by the controller. The controller determines when can the SDRAM handle the request and therefore acts accordingly. Controller also translates each request of the Host into commands needed for the SDRAM to handle the request and sends the appropriate control signals, waiting between each command for the appropriate amount of cycles. 2.2 SDR SDRAM Controller Systems The Single Data Rate (SDR) SDRAM Controller Core is designed for high memory applications with high clock rates.the core of the controller accepts commands using a simple local interface and translates them to the command sequences required by SDR SDRAM devices. The core also performs all initialization and refreshing operations and also uses bank management methods to check the status of each SDRAM bank at different intervals of time. The banks are opened or closed according to the necessity, minimizing delays. At one time, total 8 banks are managed. Cascading of access is also supported by chaining together read or write requests. Thus there is no delay between the requests, providing 100% memory throughput. 2.3 Features of SDR SDRAM Controller i. SDR SDRAM controller simplifies the command interface of SDRAM to standard system read/write interface. ii. Internal state machine built is for SDRAM power-on initialization. iii. Read/write cycle access time optimized automatically according to the SDRAM timing specification and the mode it is configured to. iv. Dedicated auto-refresh request input and acknowledge output for SDRAM refresh. v. Easily configurable to support different CAS latency and burst length. vi. It has system clock PLL feature, which allows slower system clock to be used. The system interface clock does not need to be the same as the SDRAM clock. vii. With the support of the system I/O feature available in all Lattice devices, the system interface can be in any I/O standards supported by the device. Copyright 2013 Published by IJESR. All rights reserved 800

3 Fig 1: SDR SDRAM Controller System 3. LINEAR FEEDBACK SHIFT REGISTER (LFSR) A Linear Feedback Shift Register is a sequential shift register with combinational logic that causes it to pseudorandomly cycle through a sequence of binary values. Linear feedback shift registers have multiple uses in digital systems design. LFSR is a shift register whose input bit is a linear function of its previous state. The most commonly used linear function of single bits is XOR. Thus, an LFSR is most often a shift register whose input bit is driven by the exclusive-or (XOR) of some bits of the overall shift register value. The initial value of the LFSR is called the seed. Because the register has a finite number of possible states, it must eventually enter a repeating cycle. However, an LFSR with a well-chosen feedback function can produce a sequence of bits which appears random and which has a very long cycle. Figure 2 shows the basic architecture of a 4 bit LFSR. 3.1 Theory of Operation Fig 2: Basic block diagram of LFSR Feedback around an LFSR's shift register comes from a selection of points (taps) in the register chain and constitutes XORing these taps to provide tap(s) back into the register. Register bits that do not need an input tap, operate as a standard shift register. It is this feedback that causes the register to loop through repetitive sequences of pseudo-random value. The choice of taps determines how many values there are in a given sequence before the sequence repeats. The implemented LFSR uses a one-to-many structure, rather than a many-to-one structure, since this structure always has the shortest clock-to-clock delay path. The bits in the LFSR state which influence the input are called taps. A maximum-length LFSR produces an m- sequence (i.e. it cycles through all possible 2n -1 states within the shift register except the state where all bits are zero), unless it contains all zeros, in which case it will never change. The sequence of numbers generated by this method is random. The period of the sequence is (2n - 1), where n is the number of shift registers used in the design bit LFSR 32-bit LFSR with maximum length feedback polynomial X 32 + X 22 + X 2 + X for which = 429,49,67,295 random outputs. The circuit diagram for 32-bit LFSR with maximum length polynomial is shown in Figure 3. Copyright 2013 Published by IJESR. All rights reserved 801

4 4. SYSTEM DESIGN Fig 3: Circuit Diagram of 32- Bit LFSR The main motive of this thesis work is to design a SDRAM controller which does local interfacing between a 32- bit LFSR acting as a host and Single Data Rate SDRAM.A 32 bit length Linear Feedback Shift Register (LFSR) is considered as host which generates random number patterns automatically and those patterns are accepted by the SDRAM controller using a simple local interface and translate them to the command sequences required by SDR SDRAM devices. Here in Figure 2, the schematic diagram of the top module of system design is presented. Each block/ IP is designed individually and then interfacing is done. Fig 4: Top Module of System Design 5. SIMULATIONS & RESULTS After synthesizing the VHDL design and implementing it by using XILINX ISE 14.5 and the device Spartan 3A, considering the number of banks is 4, we got this implementation report as follows: Number of Slices: 58 out of 5,888 Number of Slice Flip-Flops: 37 out of 11,776 Number of 4 input LUTs: 86 out of 11,776 Number of bonded IOBs: 37 out of Timing Summary Speed Grade: -4 Minimum period: 5.148ns Maximum Frequency: MHz Minimum input arrival time before clock: 3.793ns Maximum output required time after clock: 8.509ns Copyright 2013 Published by IJESR. All rights reserved 802

5 Maximum combinational path delay: No path found In this paper, first of all a 32- Bit LFSR is designed. Then, a 4 banked SDR SDRAM is designed. Thereafter, SDRAM controller is designed in order to interface the LFSR & SDR SDRAM and perform read/write operations on the data produced accordingly Bit Linear Feedback Shift Register Fig 5: RTL Schematic of a 32- Bit LFSR The pseudo random patterns of 32 bit are generated as follows. 4.2 SDRAM A 4 banked SDRAM is designed as follows: Fig 6: Simulation result of 32-Bit LFSR Fig 7: Simulation result of SDR SDRAM Copyright 2013 Published by IJESR. All rights reserved 803

6 4.3 SDRAM Controller Fig 8: Simulation result of Controller 4.4 Interfacing of SDRAM with SDR SDRAM Controller Fig 9: Simulation result of interfacing of SDRAM with SDR SDRAM Controller 4.5 Complete System Design When the 32-bit random patterns are generated by LFSR and given as input data to SDRAM, the controller first writes the data followed by reading operations. Fig 10: Simulation result of complete system design Copyright 2013 Published by IJESR. All rights reserved 804

7 Fig 11: RTL Schematic of Top Module System Design Table 1: On-chip Power Analysis Table 2: Power Supply Summary On-Chip Power (mw) Used Available Utilization Clocks Logic Signals IOS Static Power Total Total Dynamic Static Power Supply Power (mw) CONCLUSION Fig 12: Synthesis report of the system design In this paper, the design and implementation of a memory controller for SDR SDRAM system is done. As we are considering the data path of 32 bit, therefore it was required to design and interface a 32-bit data length Linear Feedback Shift Register. We drew the following conclusions from the above work: 1. The integration work was successfully performed and tested. The memory controller is synthesized with Xilinx ISE 14.5 and results are tabulated. Copyright 2013 Published by IJESR. All rights reserved 805

8 2. It is very much clear that the random test pattern of 32 bits is generated by LFSR, this data is stored in SDRAM and read/ write operations are performed by the controller. 3. The 32 bit LFSR takes a lot of simulation time 85.9 sec with 20 ns clock period for generating 429,49,67,295 random outputs. 4. The overall power consumption of the design is mw & frequency is MHz. 5. When comparison of the results of the proposed design is done with the previous already presented work it was found that the present design is more feasible, operating at higher frequency and power consumption is also low. 6. The main motive of designing the proposed controller was to check whether the data stored in SDRAM is obtained at output as it is at any point of time. Also, at one time only operation can be carried out, whether read or write. 7. The benefit of this single data rate controller is its simple schematic with fewer number of buffers in the circuit reduces the amount of delay and operates at higher frequencies that other DDRx SDRAMs. 6.1 Limitations of the design SDR SDRAM does not support BURST TERMINATE command. Also, burst write is not supported by SDR SDRAM LFSR generator cannot handle LFSRs which length is larger than the size of the variable of the largest type. 6.2 Future Work Instead of Single Data Rate SDRAM, any other generation of SDRAM can be used for storing data and interfacing with LFSR in the similar manner. Doing this would lead to simultaneous operations of read and write taking place thus reducing the time for accessing data stored. The 32 bit LFSR takes a lot of simulation time for generating 429, 49, 67,295 random outputs, so 8 bit or 16 bit LFSR can also be used for generating test patterns for practical use. The design can be easily modified for different system requirements. REFERENCES [1] Arathy S et.al. Design and Characterization of SDRAM Controller IP Core with Built In Refined ECC Module. International Journal of Scientific & Engineering Research (IJSER) 2012; 3(12). [2] Mehta R et.al. Implementation of a SDRAM Controller for System on Chip. Journal of Information, Knowledge and Research in Electronics and Communication Engineering 2013; 2(2): [3] Bibay P et.al. Design and Implementation of DDR SDRAM Controller using Verilog. International Journal of Science and Research (IJSR) 2013;2(1): [4] Sharma AC et.al. Construct High-Speed SDRAM Memory Controller Using Multiple FIFO's for AHB Memory Slave Interface. International Journal of Emerging Technology and Advanced Engineering (IJETAE) 2013; 3(3): [5] Architecture and Component Selection for SDR Applications, June2007, < [6] Rixner S et al. Memory access scheduling. Proceedings of the 27 th annual international symposium on Computer architecture, ISCA 00, 2000; [7] Shao J, Davis BT. A burst scheduling access reordering mechanism. Proceedings of the 13 th International Symposium on High Performance Computer Architecture. HPCA, 2007; [8] Burchard A et. al. A real-time streaming memory controller. Proceedings of the conference on Design, Automation and Test in Europe (DATE), 2005; [9] Macian C. et.al. Beyond performance: secure and fair memory management for multiple systems on a chip. Proceedings of the International Conference on Field-Programmable Technology (FPT), 2003; Copyright 2013 Published by IJESR. All rights reserved 806

9 [10] Heithecker S, Ernst R. Traffic shaping for an FPGA based SDRAM controller with complex QoC requirements. Proceedings of the Design Automation Conference, DAC 05, June 2005; [11] Mutlu O, Moscibroda T. Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared dram systems. Proceedings of the 35 th International Symposium on Computer Architecture (ISCA), 2008; [12] Whitty S, Ernst R. A bandwidth optimized SDRAM controller for the morpheus reconfigurable Architecture. Proceedings of IEEE International Symposium on Parallel and Distributed Processing (IPDPS), 2008; 1 8. [13] Nesbit KJ et. al. Fair queuing memory systems. Proceedings of 39 th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Dec. 2006; [14] Srinivasan K, Salminen E. A memory subsystem model for evaluating network-on-chip performance, White Paper Copyright 2013 Published by IJESR. All rights reserved 807

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