3. The MC6802 MICROPROCESSOR

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Damon Johnston
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1 3. The MC6802 MICROPROCESSOR This chapter provides hardware detail on the Motorola MC6802 microprocessor to enable the reader to use of this microprocessor. It is important to learn the operation and interfacing of the MC6802 microprocessor first. Once you learn MC6802, transition to the other microprocessors (i.e. 6809, 68000, 8080, 8085A, 8086) or to the microcontrollers (i.e. 68HC08, 68HC11, 8051 AT89C51, AT89C52, PIC16F877) manufactured by any of the IC houses is easy. 1

2 3.1 Pin Diagrams and Features Pin Diagrams: Figure 3-1 illustrates the MC6802 microprocessor package and pin diagram. The MC6802 is packaged in 40-pin dual in-line package (DIP). This device operate from a single 5V supply. (V CC =+5V, V SS =0V or GND) Power dissipation of MC6802 is less than 1.5 W. 2

3 FIGURE 3-1 Package and pin diagram of the Motorola MC6802 microprocessor 3

4 Features: 1. On-chip clock circuit x8 bit (128 byte) on-chip RAM (00 to 7FH) bytes of RAM are retainable (00H to 1FH) 4. Software-compatible with the MC Standard TTL-compatible inputs and outputs 6. 8-bit word size bit memory addressing 8. Interrupt capability 4

5 3.2 Bus and Control Signals Proper operation of the MPU requires that certain control and timing signals be provided to accomplish specific functions and the other signal lines be monitored to determine the state of the processor. Busses: Address Bus (A 0..A 15 ), Data Bus (D 0..D 7 ) Bus Control Signals: Enable (E), Valid Memory Address (VMA), Read/Write (R/W) MPU Control Signals: Reset (RESET), Halt (HALT), Interrupt Request (IRQ), Non-Maskable Interrupt (NMI), Memory Ready (MR). 5

6 FIGURE 3-2 Bus and control signals of the MC6802 microprocessor 6

7 1) Address Bus (A0-A15) Sixteen pins are used for the address bus. The outputs are capable of driving one standard TTL load and 90pF. These lines do not have three-state capability. 7

8 2) Data Bus (D0-D7) Eight pins are used for the data bus. It is bidirectional, transferring data to and from the memory and peripheral devices. It also has three-state output buffers capable of driving one standard TTL load and 130 pf. Data bus will be in the output mode when the internal RAM is accessed and RE will be high. This prohibits external data entering the MPU. External RAM at 0000H to 007FH must be disabled when internal RAM is accessed. It should be noted that the internal RAM is fully decoded from 0000H to 007FH. 8

9 3) Halt (HALT) When this input is in the low state, all activity in the machine will be halted. This input is level sensitive. In the HALT mode, the machine will stop at the end of an instruction, bus available will be at a high state (BA=1), valid memory address will be at a low state (VMA=0). The address bus will display the address of the next instruction. HALT should be tied high if not used. 9

10 4) Read/Write (R/W) This TTL-compatible output signals indicate to the peripherals and memory devices that whether the MPU is in a read (high) or write (low) state. The normal standby state of this signal is read (high). When the processor is halted, it will be in the read state. This output is capable of driving one standard TTL load and 90 pf. 10

11 5) Valid Memory Address (VMA) This output indicates to peripheral devices that there is a valid address on the address bus. In normal operation, this signal should be utilized for enabling peripheral interfaces such as the PIA (6821) and ACIA (6850). This signal is not three-state. One standard TTL load and 90 pf may be directly driven by this active high signal. 11

12 6) Bus Available (BA) The bus available signal will normally be in the low state; when activated, it will go to the high state indicating that the microprocessor has stopped and that the address bus is available (but not in a three-state condition). This will occur if the HALT line is in the low state or the processor is in the WAIT state as a result of the execution of a WAIT instruction. At such time, all three-state output drivers will go to their off-state and other outputs to their normally inactive level. The processor is removed from the WAIT state by the occurrence of a maskable (mask bit I=0) or nonmaskable interrupts. This output is capable of driving one standard TTL load and 30 pf. 12

13 7) Ram Enable (RE) A TTL compatible RAM enable input controls the on-chip RAM of the MC When placed in the high state, the on-chip memory is enabled to respond to the MPU controls. In the low state, RAM is disabled. 13

14 8) Enable (E) This signal is used to enable the memory or I/O device. This pin supplies the clock for the MPU and the rest of the system. This is a single phase TTL-compatible clock. This clock may be conditioned by a memory read signal. This output is capable of driving one standard TTL load and 130 pf. 14

15 The MC6802 Bus Timing

16 16

17 17

18 9) Crystal Connection Inputs (EXTAL, XTAL) These inputs are used for the internal oscillator that may be crystal controlled. These connections are for a parallel resonant fundamental crystal (see figure 3-3). A divide-by-four circuit has been added so a 4 MHz crystal may be used in lieu of a 1 MHz crystal for a most cost-effective system. 18

19 FIGURE 3-3 Crystal specifications 19

20 10) Memory Ready (MR) MR is a TTL-compatible input signal controlling the stretching of E. When MR is high, E will be in normal operation. When MR is low, E will be stretched integral numbers of half periods, thus allowing interface to slow memories. MR should be tied high (connected directly to V CC ) if not used. 20

21 11) V CC Standby This pin supplies the dc voltage to the first 32 bytes of RAM as well as the RAM Enable (RE) control logic. Thus, retention of data in this portion of the RAM on a power-up, powerdown, or standby condition is guaranteed. 21

22 12) Interrupt Request (IRQ) A low level on this input requests that an interrupt sequence be generated within the machine. The processor will wait until it completes the current instruction at is being executed before it recognizes the request. At that time, if the interrupt mask bit in the condition code register is not set (I=0), the machine will begin an interrupt sequence. 22

23 IRQ sequences: 1) The index register (X), program counter (PC), accumulators (A, B) and condition code register (CCR) are stored away on the stack. 2) Next the MPU will respond to the interrupt request by setting the interrupt mask bit high (I=1) so that no further interrupts may occur. 3) At the end of the cycle, a 16-bit vectoring address, which is located in memory locations FFF8H and FFF9H is loaded which causes the MPU to branch to an interrupt routine in memory. 23

24 NOTEs: 1) The HALT line must be in the high state for interrupts to be serviced. 2) Interrupts will be latched internally while HALT is low. 3) A nominal 3 k (or 3.3k standard ) pullup resistor to V CC should be used for wire-or and optimum control of interrupts. 4) IRQ may be tied directly to V CC If not used. 24

25 13) Reset (RESET) This input is used to reset and start the MPU from a power-down condition, resulting from a power failure or an initial start-up of the processor. When this line is low, the MPU is inactive and the information in the registers will be lost. If a high level is detected on the input, this will signal the MPU to begin the restart sequence. This will start execution of a routine to initialize the processor from its reset condition. 25

26 NOTEs: 1) All the higher order address lines will be forced high. 2) For the restart, the last two (FFFEH, FFFFH) locations in memory will be used to load the program that is addressed by the program counter. 3) During the restart routine, the interrupt mask bit in the Conditon Code Register (CCR) is set (I=1) and must be reset (I=0) before the MPU can be interrupted by (IRQ). Power-up and reset timing are shown in figure

27 Figure 3-4 Power-up and reset timing 27

28 14) Non-Maskable Interrupt (NMI) A low-going edge on this input requests that a non-maskable interrupt sequence be generated within the processor. As with the interrupt request signal, the processor will complete the current instruction that, is being executed before it recognizes the NMI signal. The interrupt mask bit in the condition code register has no effect on the NMI. 28

29 The index register (X), program counter (PC), accumulators (A, B), and condition code registers (CCR) are stored away on the stack. At the end of the cycle, a 16-bit vectoring address which is located in memory locations FFFCH and FFFDH is loaded causing the MPU to branch to an interrupt service routine in memory. A nominal 3 k pullup resistor to VCC should be used for wire-or and optimum control of interrupts. NMI may be tied directly to VCC if not used. 29

30 Inputs IRQ and NMI are hardware interrupt lines that are sampled when E is high (E=1) and will start the interrupt routine on a low E (E=0) following the completion of an instruction. Figure 3-5 is a flowchart describing the major decision paths and interrupt vectors of the microprocessor. 30

31 Figure 3-5 Flowchart and vector table of the MC6802 MPU 31

2. List the five interrupt pins available in INTR, TRAP, RST 7.5, RST 6.5, RST 5.5.

2. List the five interrupt pins available in INTR, TRAP, RST 7.5, RST 6.5, RST 5.5. DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING EE6502- MICROPROCESSORS AND MICROCONTROLLERS UNIT I: 8085 PROCESSOR PART A 1. What is the need for ALE signal in