Controller Implementation--Part II

Transcription

1 Controller Implementation--Part II Alternative controller FSM implementation approaches based on: Classical Moore and Mealy machines Time-State: Divide and Conquer Jump counters Microprogramming (ROM) based approaches» Branch sequencers» Horizontal microcode» Vertical microcode CS 5 - Fall 25 Lec #5: Microprogramming - Branch Sequencers Concept Implement Next State Logic via ROM Address ROM with current state and inputs Problem: ROM doubles in size for each additional input Note: Jump counter trades off ROM size vs. external logic Only jump states kept in ROM Even in hybrid approach, state + input subset form ROM address Branch Sequencer: between the extremes Next State stored in ROM Each state limited to small number of next states Always a power of 2 Observe: only a small set of inputs are examined in any state CS 5 - Fall 25 Lec #5: Microprogramming - 2

2 Branch Sequencers 4 Way Branch Sequencer I n p u t s Mux Mux β α a a a2 a3 a4 a5 x x x x 64 Word ROM Z Y X W C S o i n g t n r a o l l s N α β α β α β α β W X Y Z state Current State selects two inputs to form part of ROM address These select one of four possible next states (and output sets) Every state has exactly four possible next states CS 5 - Fall 25 Lec #5: Microprogramming - 3 Branch Sequencer Processor CPU Design Example s<3> s<2> s<> s<> S3 S2 S S G E5 E4 AC<5> E3 AC<5> E2 E E E9 E8 EOUT E7 \α E6 E5 IR<5> E4 IR<4> E3 E2 + Wait E Wait E + S3 S2 S S 5 E5 5 G E4 E3 E2 E E E9 E8 E7 E6 E5 E4 E3 E2 E E EOUT \β Alpha, Beta multiplexer input setup CS 5 - Fall 25 Lec #5: Microprogramming - 4

3 Example Processor FSM ROM ADDRESS ROM CONTENTS (Reset, Current State, a, b) Next State Register Transfer Operations RES X X (IF) PC MAR, PC + PC IF (IF) (IF) MAR Mem, Read, Request IF (IF2) MAR Mem, Read, Request (IF) Mem MBR IF2 (IF2) (OD) MBR IR OD (LD) IR MAR (ST) IR MAR, AC MBR (AD) IR MAR (BR) IR MAR CS 5 - Fall 25 Lec #5: Microprogramming - 5 Example Processor FSM ROM ADDRESS ROM CONTENTS (Reset, Current State, a, b) Next State Register Transfer Operations LD X X (LD) MAR Mem, Read, Request LD (LD2) Mem MBR (LD) MAR Mem, Read, Request LD2 X X (RES) MBR AC ST X X (ST) MAR Mem, Write, Request, MBR Mem ST (RES) (ST) MAR Mem, Write, Request, MBR Mem AD X X (AD) MAR Mem, Read, Request AD (AD2) (AD) MAR Mem, Read, Request AD2 X X (RES) MBR + AC AC BR (RES) (RES) IR PC CS 5 - Fall 25 Lec #5: Microprogramming - 6

4 Branch Sequencers α and β MUX Control Alternative Horizontal Implementation α β α β α β α β A A A2 A3 n- n- n- n- Datapath Control Signals I N P U T S M U M X U X α β bit n : MUX 4: MUX bit bit n bit state register Input MUX controlled by encoded signals, not state Much fewer inputs than unique states! In example FSM, input MUX can be 2:! Adding length to ROM word saves on bits vs. doubling words Vertical format: (4 + 4) x 64 = 52 ROM bits Horizontal format: (4 + 4 x 4 + 2) x 6 = 52 ROM bits CS 5 - Fall 25 Lec #5: Microprogramming - 7 Microprogramming How to organize the control signals Implement control signals by storing 's and 's in a ROM Horizontal vs. vertical microprogramming Horizontal: ROM output for each control signal Vertical: encoded control signals in ROM, decoded externally some mutually exclusive signals can be combined helps reduce ROM length CS 5 - Fall 25 Lec #5: Microprogramming - 8

5 Microprogramming Register Transfer/Microoperations 4 Register Transfer operations become 22 Microoperations: PC ABUS IR ABUS MBR ABUS RBUS AC AC ALU A MBUS ALU B ALU ADD ALU PASS B MAR Address Bus MBR Data Bus ABUS IR ABUS MAR Data Bus MBR RBUS MBR MBR MBUS PC PC + PC ABUS PC Read/Write Request AC RBUS ALU Result RBUS CS 5 - Fall 25 Lec #5: Microprogramming - 9 Horizontal Microprogramming Horizontal Branch Sequencer α, β Mux bits 4 x 4 Next State bits 22 Control operation bits α mux β mux 4 bits total Next States A A A2 A3 PC ABUS IR ABUS MBR ABUS RBUS AC AC ALU A MBUS ALU B ALU ADD ALU PASS B MAR Address Bus MBR Data Bus ABUS IR ABUS MAR Data Bus MBR RBUS MBR MBR MBUS PC PC + PC ABUS PC Read/Write Request AC RBUS ALU Result RBUS CS 5 - Fall 25 Lec #5: Microprogramming -

6 Horizontal Microprogramming Moore Processor ROM Current State (Address) RES () IF () IF () IF2 () IF3 () OD () LD () LD () LD2 () ST () ST () AD () AD () AD2 () BR () BR () α mux β mux Next States A A A2 A3 Alpha inputs: = Wait, Beta inputs: = AC<5>, PC ABUS IR ABUS MBR ABUS RBUS AC AC ALU A MBUS ALU B = IR<5> = IR<4> ABUS IR CS 5 - Fall 25 Lec #5: Microprogramming - ALU ADD ALU PASS B MAR Address Bus MBR Data Bus ABUS MAR Data Bus MBR RBUS MBR MBR MBUS PC PC + PC ABUS PC Read/Write Request AC RBUS ALU Result RBUS Horizontal Microprogramming Advantages: most flexibility -- complete parallel access to datapath control points Disadvantages: very long control words -- + bits for real processors NOTE: Not all microoperation combinations make sense! Output Encodings: Group mutually exclusive signals Use external logic to decode Example: Æ PC, PC + Æ PC, ABUS Æ PC mutually exclusive Save ROM bit with external 2:4 Decoder CS 5 - Fall 25 Lec #5: Microprogramming - 2

7 Horizontal Microprogramming Partially Encoded Control Outputs C O N T R O L R O M ALU ADD ALU PASS B MAR Address Bus MBR Data Bus ABUS MAR RBUS MBR Read/Write Request AC RBUS 2 2 2:4 DEC 2:4 DEC RBUS AC AC ALU A MBUS ALU B MBR MBUS ALU Result RBUS MBR ABUS ABUS IR PC PC + PC ABUS PC PC ABUS IR ABUS Data Bus MBR CS 5 - Fall 25 Lec #5: Microprogramming - 3 Vertical Microprogramming More extensive encoding to reduce ROM word length Typically use multiple microword formats: Horizontal microcode -- next state + control bits in same word Separate formats for control outputs and "branch jumps" may require several microwords in a sequence to implement same function as single horizontal word In the extreme, very much like assembly language programming CS 5 - Fall 25 Lec #5: Microprogramming - 4

8 Vertical Microprogramming Branch Jump Compare indicated signal to or Branch Jump Format Type Condition Select Condition Compare 2 6 Next Address = Wait = AC<5> = IR<5> = IR<4> Register Transfer Source, Destination, Operation ROM Bits Register Transfer Format : NO OP : PC ABUS : IR ABUS : MBR MBUS : MAR M : AC RBUS : ALU Res RBUS Source Destination Operation : NO OP : RBUS AC : MBUS IR : ABUS MAR : M MBR : RBUS MBR : ABUS PC : MBR M CS 5 - Fall 25 Lec #5: Microprogramming - 5 : NO OP : ALU ADD : ALU PASS B : PC : PC + PC : Read : Write Vertical Microprogramming ROM ADDRESS SYMBOLIC CONTENTS BINARY CONTENTS RES RT PC MAR, PC + PC IF RT MAR M, Read BJ Wait=, IF IF RT MAR M, M MBR, Read BJ Wait=, IF IF2 RT MBR IR BJ Wait=, IF2 RT IR MAR OD BJ IR<5>=, OD BJ IR<4>=, ST LD RT MAR M, Read LD RT MAR M, M MBR, Read BJ Wait=, LD LD2 RT MBR AC BJ Wait=, RES BJ Wait=, RES CS 5 - Fall 25 Lec #5: Microprogramming - 6

9 Vertical Microprogramming ROM ADDRESS SYMBOLIC CONTENTS BINARY CONTENTS ST RT AC MBR RT MAR M, MBR M, Write ST RT MAR M, MBR M, Write BJ Wait=, RES BJ Wait=, ST OD BJ IR<4>=, BR AD RT MAR M, Read AD RT MAR M, M MBR, Read BJ Wait=, AD AD2 RT AC + MBR AC BJ Wait=, RES BJ Wait=, RES BR BJ AC<5>=, RES RT IR PC BJ AC<5>=, RES 3 words x ROM bits = 3 bits total versus 6 x 38 = 68 bits horizontal CS 5 - Fall 25 Lec #5: Microprogramming - 7 Vertical Programming Controller Block Diagram ROM Address T SRC DST OP Reset ALU ADD ALU PASS B 2 3:8 3 DEC 4 PC + PC 5 Read 6 Write Enb 7 3:8 DEC Enb RBUS AC ABUS IR ABUS MAR M MBR RBUS MBR ABUS PC MBR M PC Read/Write Request Wait AC<5> IR<5> IR<4> Cond Logic LD CLR µpc CNT PC ABUS IR ABUS 2 3:8 3 MBR ABUS DEC 4 MAR M 5 AC RBUS 6 ALU Res RBUS Enb 7 Reset Clk CS 5 - Fall 25 Lec #5: Microprogramming - 8

10 Vertical Microprogramming Condition Logic Condition Selector Condition Comparator Microinstruction Type LD Wait AC<5> IR<5> IR<4> 4: MUX Microinstruction Type CNT CS 5 - Fall 25 Lec #5: Microprogramming - 9 Vertical Microprogramming Writeable Control Store Part of control store addresses map into RAM» Allows assembly language programmer to implement own instructions» Extend "native" instruction set with application specific instructions» Requires considerable sophistication to write microcode» Not a popular approach with today's processors Make the native instruction set simple and fast Write "higher level" functions as assembly language sequences CS 5 - Fall 25 Lec #5: Microprogramming - 2

11 Controller Implementation Summary-- Part II Control Unit Organization Register transfer operation Classical Moore and Mealy machines Time State Approach Jump Counter Branch Sequencers Horizontal and Vertical Microprogramming CS 5 - Fall 25 Lec #5: Microprogramming - 2