Quick Reference Card. Timing and Stack Verifiers Supported Platforms. SCADE Suite 6.3

Transcription

1 Timing and Stack Verifiers Supported Platforms SCADE Suite 6.3

2 About Timing and Stack Verifiers supported platforms Timing and Stack Verifiers Supported Platforms SCADE Suite Timing Verifier and SCADE Suite Stack Verifier are powered by AbsInt s ait/stackanalyzer. This reference card provides information on the main characteristics of the SCADE Suite Timing and Stack Verifiers for supported processor platforms. Contents 1. Timing Verifier Supported Platforms 3 PowerPC MPC5xx 3 PowerPC MPC55xx 3 PowerPC MPC603e 4 PowerPC MPC755s 5 TriCore 5 NEC V850 6 LEON2/ Stack Verifier Supported Platforms 7 All PowerPC (PPC) Family 7 TriCore 1766/1796/ NEC V850 Family 7 LEON2/3 7 Esterel Technologies - SCADE Suite 1-2

3 1. Timing Verifier Supported Platforms Timing Verifier supports the following platforms: PowerPC 1 MPC5xx 32-bit pipelined processor Supports single and double precision floating point operations Supports external memory (up to 4 GB) Out-of-order execution, in-order completion MPC555: Core clock up to 40 MHz 448 KB Flash EEPROM memory 26 KB of SRAM MPC565: Core clock up to 56 MHz 1 MB of internal FLASH memory (divided into 2 blocks of 512 KB) 36 KB SRAM PowerPC MPC55xx 32-bit pipelined processor In-order execution, in-order completion Supports scalar and vector single precision floating point operations Supports external memory (up to 512 MB) MPC5553: Core clock up to 132 MHz 8 KB unified cache 1536 KB internal FLASH memory 64 KB internal SRAM No support for external memory in 208 pin package Only 16-bit external memory bus in 324 pin package MPC5554: Core clock up to 132 MHz 32 KB unified cache 2 MB internal FLASH memory 64 KB internal SRAM 1. IBM PowerPC (PPC) family Esterel Technologies - SCADE Suite 1-3

4 MPC5561: Core clock up to 132 MHz Supports VLE (16-bit instructions) 32 KB unified cache 1 MB internal FLASH memory 192 KB internal SRAM MPC5566: Core clock up to 144 MHz Supports VLE (16-bit instructions) 32 KB unified cache 3 MB internal FLASH memory 128 KB internal SRAM MPC5567: Core clock up to 132 MHz Supports VLE 8 KB unified cache 2 MB internal FLASH memory 80 KB internal SRAM PowerPC MPC603e PowerPC603e core supporting a configurable memory controller with two backends for static memory and DDR memory operating in 60x bus compatible mode (as, e.g., present in the MPC8260, MPC8270, MPC8280) 32bit pipelined processor out-of-order execution, in-order completion Supports single and double precision floating point operations Supports external memory (up to 4 GB) 16 KB instruction cache (LRU replacement algorithm) 16 KB data cache (LRU replacement algorithm) 5 independent execution units (Integer unit, Load/Store unit, Floating-point unit, System register unit, Branch processing unit) 64-bit data bus and 32-bit address bus 1 level of speculative execution Esterel Technologies - SCADE Suite 1-4

5 PowerPC MPC755s PowerPC755 core supporting a configurable memory controller with two backends for static memory and DDR memory 32bit pipelined processor out-of-order execution, in-order completion Supports single and double precision floating point operations Supports external memory (up to 4 GB) 32 KB instruction cache (PLRU(!) replacement algorithm) 32 KB data cache (PLRU(!) replacement algorithm) 6 independent execution units (2 Integer units, Load/Store unit, Floating-point unit, System register unit, Branch processing unit) 64-bit data bus and 32-bit address bus 2 levels of speculation, first level supports speculative execution, second level for branch prediction TriCore 32-bit micro-controller Supports single-precision floating point arithmetic TriCore 1796 Core clock up to 150 MHz 16 KB instruction cache (LRU replacement policy) 48 KB code scratch-pad RAM 64 KB internal SRAM 2 MB internal program FLASH 128 KB internal data FLASH Supports external memory (up to 246 MB) TriCore 1797 Core clock up to 180 MHz 16 KB instruction cache (LRU replacement policy, configurable) 4 KB data cache (LRU replacement policy, the number of writeback events is bounded automatically, the costs of all write-back events have to be added manually to the raw WCET bound) Up to 24 KB code scratch-pad RAM (configurable) Up to 124 KB internal SRAM (configurable) 2 MB internal program FLASH 64 KB internal data FLASH Supports external memory (up to 246 MB) TriCore 1766 Core clock up to 80 MHz 8 KB instruction cache (LRU replacement policy) 16 KB code scratch-pad RAM 56 KB internal SRAM 1504 KB internal program FLASH 32 KB internal data FLASH Esterel Technologies - SCADE Suite 1-5

6 NEC V850 NEC V850E1 Family 32-bit RISC architecture 5-stage pipeline on-chip flash memory for code and data, internal RAM external memory controller various periphery (e.g., DMA, CAN, FlexRay, timer, CRC), depending on actual device single precision floating point unit, depending on actual device devices supported by a³: V850E/PHO3 (µpd70f3441, µpd70f3483), V850E1/FK3 (µpd70f3469), FOREST (PD70F3407, PD70F3409, PD70F3410, PD70F3429, PD70F3431) NEC V850E2[R,M] Family 32-bit RISC architecture 7-stage superscalar E2 pipeline with three independent sub units dual core architecture, depending on actual device; only singlecore mode is supported by a³ on-chip code flash memory, internal RAM external memory controller, depending on actual device various periphery (e.g., DMA, CAN, Ethernet, FlexRay, timer, CRC), depending on actual device floating point unit with single and double precision operation processor protection functionality (e.g., memory access protection, peripheral devices protection) devices supported by a³: umbrella chip (µpd70f3501f1), VFOREST (μpd76f0134, μpd76f0197, μpd76f0198, μpd76f0199) LEON 32-bit pipelined SPARC v8 compliant processor Separate instruction and data caches (1 KB to 64 KB, LRU replacement policy) Supports single- and double-precision floating point arithmetic LEON2 Core clock up to 165 MHz 8/16/32-bit memory controller for external PROM and SRAM 32-bit PC133 SDRAM controller LEON3 Core clock up to 400 MHz Supports SPARC v8e extensions 8/16/32-bit memory controller for external PROM and SRAM Esterel Technologies - SCADE Suite 1-6

7 2. Stack Verifier Supported Platforms Stack Verifier supports the following platforms: All PowerPC (PPC) Family PPC is valid for Stack analysis with all PowerPC targets The following instruction sets are supported: Common Book E Embedded environment Variable length encoding (VLE) Signal processing engine (SPE) TriCore 1766/1796/1797 TriCore instruction set NEC V850 Family Stack analysis is supported for V850E1 (without FPU) and V850E2[M,R] targets LEON2/3 SPARC v8 instruction set Esterel Technologies - SCADE Suite 1-7

8 Contact Information Submit questions to Technical Support at Contact one of our Sales representatives at Direct general questions about Esterel Technologies to Discover the latest news on our products and technology at Copyright 2012 Esterel Technologies SA. All rights reserved. SCADE,SCADE Suite, SCADE Suite Timing Verifier, and SCADE Suite Stack Verifier are trademarks or registered trademarks of Esterel Technologies. ait/stackanalyzer is a copyright of AbsInt Angewandte Informatik. All other trademarks and tradenames are the property of their respective owners. Esterel Technologies releases this information with full intent to be 100% accurate however information contained herein is subject to change without notice and Esterel Technologies assumes no responsibility or liability as a result of any inaccuracies. Revision: SC-aiT-TSV-QRC /01/12