3D SYSTEM INTEGRATION TECHNOLOGY CHOICES AND CHALLENGE ERIC BEYNE, ANTONIO LA MANNA

Transcription

1 3D SYSTEM INTEGRATION TECHNOLOGY CHOICES AND CHALLENGE ERIC BEYNE, ANTONIO LA MANNA

2 OUTLINE 3D Application Drivers and Roadmap 3D Stacked-IC Technology 3D System-on-Chip: Fine grain partitioning Conclusion 3D Landscape 2

3 APPLICATION DRIVERS Facebook 3

4 APPLICATION DRIVERS More Data; Faster Data Increased Power Consumption 4

5 APPLICATION DRIVERS More Data; Faster Data 3D Stacked IC s 3D-SIC Interposer stacking 5

6 MAIN APPLICATIONS DRIVERS 3D INTEGRATION TECHNOLOGY DRAM DRAM Logic Logic Memory cube Offers low delay, low power and high bandwidth interconnect. High volume applications: drives the technology platforms 6

7 MAIN APPLICATIONS DRIVERS 3D INTEGRATION TECHNOLOGY DRAM DRAM Logic Logic Close to market introduction but delayed with respect to original timelines: osupply chain readiness: wide I/O memory supply, unclear business models otechnology readiness and cost of ownership, CoO. Memory cube ohigh performance applications: high power: requires the use of an intermediate interposer technology = additional cost: needs to be offset by additional integration opportunities. 7

8 High Power Low Volume High performance Low Power High Volume Consumer 3D APPLICATION ROADMAP Memory cube DRAM on Logic Heterogeneous Mixed Analog/Digital DRAM on Logic Logic/DRAM on CSP Si interposer Mixed node 3D-SOC Analog/ MEMS/Sensors Digital Logic Analog E/O Logic fabric N+1 N/N-1 Heterogeneous smart system integration Optical Module DRAM Logic DRAM Logic/ ASPs/Analog/IO DRAM Logic OIO Passive interposer Processing unit with high bandwidth electrical I/O integrated on lite - active Silicon Interposer Processing unit with optical I/O integrated on lite -active Silicon Interposer 8

9 OUTLINE 3D Application Drivers and Roadmap 3D Stacked-IC Technology 3D System-on-Chip: Fine grain partitioning Conclusion 3D Landscape 9

10 3DSIC: STACKED IC INTEGRATION High density die-die interconnect: vertical (3D) or lateral interconnect on interposer substrate ( 2.5D ) Technologies are available for successful integration Key challenges: Cost effective integration schemes Technology maturity Business models 10

11 3D TECHNOLOGY: FROM TSV TO STACKED PACKAGE FEOL process Via middle TSV BEOL process Wafer thinning, TSV reveal & backside processing Via last TSV 3D Stacking (D2D; D2W; W2W) Stack Packaging 11

12 3D TECHNOLOGY: MAIN CHALLENGES FROM TSV TO STACKED PACKAGE FEOL process Via middle TSV BEOL process Wafer thinning, TSV reveal & backside processing Via last TSV Via Middle TSV POR process at 5µm Ø x 50 µm Si thickness Reliable process at 3µm Ø x 50 µm Si thickness Potential scaling to 2µm Ø x 40 µm Si thickness Cost effective, reliable temporary thin wafer carrier system. Proposed solutions and materials still evolving Via Last TSV: low thermal budget, Si TTV, M1 contact Scaling to 5µm Ø x 50 µm Si thickness 3D Stacking (D2D; D2W; W2W) Stack Packaging Die level: Interconnect pitch scaling, assembly yield and productivity (throughput). Wafer level: Wafer-to-wafer overlay, Bonding yield Electrical interconnect method and yield. CPI : 3D stack or interposer to package stacking Thermal control 12

13 VIA MIDDLE Cu TSV PROCESS AFTER FEOL / BEFORE BEOL Si Si imec POR process: o 5 µm diameter; o 50 µm deep; o Aspect ratio 10 13

14 3D- TSV SCALING ROADMAP 10µm Ø, 100µm deep, AR 10:1 5µm Ø, 50µm deep AR 10:1 3µm Ø, 50µm deep AR 17:1 2µm Ø, 40µm deep AR 15:1 20:1 Ø AR Depth Ø AR Depth 30µm 40µm In combination with integration on advanced device nodes 14

15 DIE-TO-DIE OR DIE-TO-WAFER STACKING - Scaling to 20µm µbump PITCH 12.5µm 7.5µm Cu Sn Ni 20µm Cu Sn Cu pad Cu pad 12.5µm 7.5µm 15

16 DIRECT CU TSV-TO-CU PAD STACKING 6 die stack (20 µm pitch) - TSV Cu TSV liner 5µm Backside Passivation 20µm 16

17 OUTLINE 3D Application Drivers and Roadmap 3D Stacked-IC Technology 3D System-on-Chip: Fine grain partitioning Conclusion 3D Landscape 17

18 HIGH DENSITY 3D-INTEGRATION 3D-SOC : 3D System-on-chip, through heterogeneous integration SOC Node N Node N+1 Digital logic takes full advantage of scaling Efficient use wafer area Node N/N+1 Digital Logic, SRAM Analog functionality I/O drivers High density SRAM on logic Mixed node, heterogeneous technology Wafer-Wafer bonding High density Wafer-wafer interconnects: Pitch scaling 5µm 2 µm 1 µm 0.5µm 18

19 3D ARCHITECTURE EXPLORATION EXAMPLE IMEC S SOC 3MF AVC/H264 ENCODER L2I1 L2D1 L2I2 L2D2 L2I1 L2D1 AD#1 AD#2 AD#3 L2D2 AD#6 AD#5 AD#4 L2I2 AD#1 AD#2 AD#1 AD#1 AD#2 AD#3 AD#2 L1#1 AD#3 AD#3 L1#2 L1#3 L1#6 AD#6 AD#5 L1#5 AD#6 AD#6 AD#4 L1#4 AD#5 AD#5 AD#4 AD#4 3D-SIC 3D SOC / CONFIDENTIAL 19

20 BEOL ELECTRONIC SYSTEM INTERCONNECT WIRING HIERARCHY On-chip Wiring Hierarchy System-level wiring hierarchy Traditional view Global Inter - mediate Local FEOL ITRS 20

21 3D SOC W2W BONDING Both wafers have FEOL and BEOL processing Top wafer has FEOL and some BEOL processing Bottom wafer has FEOL and BEOL processing Contact pitch 5µm 1µm Minimal processing after bonding: via reveal or via last Contact pitch 2µm 0.5µm Critical processing after bonding: High AR small TSV - via to top and bottom wafer metalization One or more BEOL layers after wafer stacking 21

22 3D-SOC - W2W HYBRID BONDING TSV Oxide-oxide bonding Cu Cu connection 22

23 2 ND TIER FEOL PROCESSING POST WAFER BONDING Top wafer: only unpattern semiconductor device layer Bottom wafer has FEOL and some BEOL processing Simplified bonding process: no overlay problem Critical processing after bonding: Device fabrication second tier with very low thermal budget (with Cu/low-k BEOL tier 1 present) When connecting at fine pitch: Most of the BEOL layers to be processed after wafer stacking 23

24 OUTLINE 3D Application Drivers and Roadmap 3D Stacked-IC Technology 3D System-on-Chip: Fine grain partitioning Conclusion 3D Landscape 24

25 3D LANDSCAPE 3D-SIC 3D-SOC 3D-IC wiring level Global Semi-global Intermediate Local FEOL 2-tier stack 2 nd FEOL after stacking Multi-tier FEOL TSV Pitch µm µm TSV after stack TSV after stack No TSV Contact Pitch: Rel. density: Stacking Method µbump pitch: µm Cu TSV Cu pad: µm D2D, D2W (W2W) Stacked die B2F / F2F 5 1 µm µm 0.5 µm (Overlay 2 nd tier defined by W2W alignment/bonding) W2W (D2W) Contact at bond interface F2F W2W Contact after stacking F2F nm W2W Si layer-to-wafer stacking 2 nd Tier Device fab. after stacking < 100 nm > (Overlay 2 nd tier defined by litho scanner alignment) Monolithic Device-level stacking 25

26 3D LANDSCAPE 3D-SIC 3D-SOC 3D-IC wiring level Global Semi-global Intermediate Local FEOL 2-tier stack 2 nd FEOL after stacking Multi-tier FEOL TSV Pitch µm µm TSV after stack TSV after stack No TSV Contact Pitch: Rel. density: Stacking Method µbump pitch: µm Cu TSV Cu pad: µm D2D, D2W (W2W) Stacked die B2F / F2F 5 1 µm µm 0.5 µm (Overlay 2 nd tier defined by W2W alignment/bonding) W2W (D2W) Contact at bond interface F2F W2W Contact after stacking F2F nm W2W Si layer-to-wafer stacking 2 nd Tier Device fab. after stacking < 100 nm > (Overlay 2 nd tier defined by litho scanner alignment) Monolithic Device-level stacking 26

27 IMEC 3D SYSTEM INTEGRATION PROGRAM LOGIC IDM MEMORY IDM FOUNDRIES FABLESS 3D PROGRAM OSAT EDA MATERIAL SUPPLIERS TECHNOLOGY SUPPLIER EQUIPMENT SUPPLIERS Lam RESEARCH 27

28 Thanks!