INTRODUCTION & INSTRUCTIONS
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1 INTRODUCTION & INSTRUCTIONS Dr. Bill Yi Santa Clara University (Based on text: David A. Patterson & John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 3 rd Ed., Morgan Kaufmann, 2007) (Also based on presentation: Dr. Nam Ling, COEN210 Lecture Notes) 1
2 COURSE CONTENTS Introduction Instructions Computer Arithmetic Processor: Datapath Processor: Control Pipelining Techniques Memory Input/Output Devices 2
3 INTRODUCTION Overview the Computer Systems Evolution of Memory and Processor Historical Perspective Levels of Representation 3
4 A Desktop Computer A desktop computer (left figure) Motherboard, I/O interface board, board for memory chips, power supply, disk drives (right figure) 4
5 Inside a PC Patterson & Henessey, Morgan Kaufmann
6 PC Motherboard Intel Pentium 4 processor - upper left, covered by metal fins (heat sink) Main memory DRAM middle, small board perpendicular to mother board (DIMMs) The rest mostly connectors for external I/O devices 6
7 Processor Chip - 1 Earlier Intel Pentium Chip Data cache Control Branch Instruction cache Bus Integer datapath Floatingpoint datapath 7
8 Processor Chip - 2 Intel Pentium 4 Intel Pentium 4 die photo (Henessey & Patterson, Morgan Kaufmann 2003) Intel Pentium 4 with 3 GHz - package (intel 2003) 8
9 Processor Chip - 3 Intel Pentium 4 9
10 Hardware / Software Hardware: physical components System software: operating system, compiler,... Application software: PowerPoint, spreadsheet,... Application software System software Hardware 10
11 Five Classic Components of a Computer + Network Datapath: performs arithmetic & logic operation Control: tells datapath, memory, I/O what to do according to instructions Memory: stores programs + data cache (SRAM): small & fast DRAM: main memory optical disk (CD, DVD), magnetic disk, FLASH, magnetic tapes: secondary, nonvolatile Input: inputs instructions, data, etc.; e.g. keyboard, mouse (electromech optical), disk... Output: outputs results, information, etc.; e.g. monitor (flat-panel LCDs or CRT), printer, disk, Input CPU Control Datapath Memory Output Network: communicates with other computers, resource sharing, non-local accesses; e.g. LAN, Internet,... Network 11
12 A Historical Perspective 1946: J. Presper Eckert & John Mauchly (U. Penn.) announced ENIAC (Electronic Numerical Integrator and Calculator). It used vacuum tubes and performed 1900 adds/sec John von Neumann joined Eckert & Mauchly and built EDVAC (Electronic Discrete Variable Automatic Computer), a stored-program computer 1948: U. Manchester built Mark-I, first operational, stored-program computer 1949: Maurice Wilkes (Camb. U.) built EDSAC (Electronic Delay Storage Automatic Calculator), first full-scale, operational, stored-program computer 1940s: Other pioneers include Konrad Zuse (Germany), Alan Turing (UK) 1940s: Howard Aiken (Harvard) built Mark-III & Mark-IV, with separate memories for instructions & data, hence Harvard Architecture 1947: Whirlwind started at MIT, using magnetic core memory 1951: 1st successful commercial computer, UNIVAC I (Universal Automatic Computer), built and sold (Remington-Rand / Eckert-Mauchly Computer Corp.) 1952: IBM shipped IBM
13 A Historical Perspective 1964: IBM Syst/360. IBM/360 architectures dominated large computer market 1965: DEC unveiled PDP-8, 1st commercial minicomputer 1971: Intel invented 1st microprocessor, Intel : Seymour Cray at CDC announced CDC 6600, 1st supercomputer 1976: Cray announced Cray-I, then fastest supercomputer No single fountainhead for personal computer 1977: Apple II by Steve Jobs & Steve Wozniak set standards for low cost, high volume 1981: IBM announced IBM PC and became the best-selling computer of any kind; its success gave Intel the most popular microprocessor and Microsoft the most popular operating system 1990s: Multimedia, networks, Internet, embedded processors, graphics, etc : Wireless & mobile (e.g. cell phone), 3-D graphics, multimedia (e.g. video), Internet, GHz processors, embedded, dual-core, quad-core, multi-core, etc. 90s, : Architectural techniques: Superscalar, dynamic pipelining, speculative execution, VLIW, multithreading, multi-core arch, etc. 13
14 Intel 80x86 History 1978: Intel announced bit architecture (an extension to bit) 1980: Intel announced 8087 floating point co-processor 1982: Intel announced 80286, with address-space extended to 24 bits 1985: Intel announced 80386, a 32-bit architecture 1989: Intel 80486, with improved performance, pipelining 1992: Intel Pentium, improved performance 1995: Intel Pentium Pro, improved performance (> 100 MHz) 1997: MMX extension, set of instructions to accelerate multimedia & communication applications 1998: Intel Pentium II 1999: Intel Pentium III 2000: Intel Pentium III > 1 GHz, competition from AMD, Pentium IV (11/00) 2002: Intel Pentium IV > 3 GHz (3.06 GHz) with multithreading and 0.13 micron technology 2005: Intel Pentium D (dual-core version of Pentium 4 Extreme) - 2 independent execution units onto same processor : Intel Quad-Core, 65 nm technology 14
15 Technology Trends
16 Technology Trends - 2 Moore s law: transistor capacity doubles every months 16
17 Multithreading & Multi-core CPUs Threads (threads of execution) - a program forks itself into 2 or more simultaneously (or pseudo-simultaneously) running tasks Multiple threads can be executed in parallel on many computers: Single processor - by time slicing when a single processor switches between different threads, so fast as to give the illusion of simultaneity Multiprocessor or multi-core system - achieved via multiprocessing, different threads & processes run simultaneously on different processors or cores. Multi-core CPUs: Multi-chip approach - cores are made by different chips that are put together in a single package. Cores communicate using front side bus. L2 cache is separated Monolithic approach - Cores are manufactured in only one chip, do not need to use front side bus. Memory cache is shared between the two cores. Better performance 17
18 Levels of Representation High level language program Compiler Assembly language program Assembler Object: Machine language modu. Linker temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) Object: Library routine (machine lang.) Executable: Machine language prog. Loader Memory 18
19 INSTRUCTIONS Instruction Type Instruction Format Addressing Modes 19
20 Introduction Instruction: Words of machine s language Instruction Set: Set of instruction RISC (Reduced Instruction Set Computer) Design Principles: Principle 1: Simplicity favors regularity Principle 2: Smaller is faster Principle 3: Good design demands good compromises Principle 4: Make the common case fast We ll be working with MIPS architecture Used by NEC, Nintendo, Cisco, Silicon Graphics, Sony, 20
21 MIPS Instruction Set Arch.: Registers Registers - 32 general purpose registers, 3 special purpose registers, each 32 bits $zero (0): constant 0 $at (1): reserved for assembler $v0-v1 (2-3): values for results & expression evaluation $a0-a3 (4-7): arguments $t0-t7 (8-15): temporaries $s0-s7 (16-23): saved $t8-t9 (24-25): more temporaries $gp (28): global pointer $sp (29): stack pointer $fp (30): frame pointer $ra (31): return address Registers $0 - $31 PC Hi Lo 3 special purpose registers PC: program counter Hi, Lo: for multiply and divide 21
22 MIPS Instruction Set Arch.: Memory Word length = 32 bits Memory: byte addressable, Big Endian 1 word = 4 bytes Each address is to a byte Registers are smaller than memory, but with faster access time Note: Word unit of access in a computer Big-endian uses leftmost or big end byte as word address Little-endian uses rightmost or little end byte as word address Register 32 bits Memory 8 bits 22
23 Registers vs. Memory Arithmetic instructions operands must be registers, Only 32 registers provided Compiler associates variables with registers What about programs with lots of variables Control Input Memory Datapath Output Processor I/O 23
24 Instructions Load and store instructions Example: C code: A[12] = h + A[8]; MIPS code: lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 48($s3) Can refer to registers by name (e.g., $s2, $t2) instead of number Store word has destination last Remember arithmetic operands are registers, not memory! Can t write: add 48($s3), $s2, 32($s3) 24
25 Our First Example Can we figure out the code? swap(int v[], int k); { int temp; temp = v[k] v[k] = v[k+1]; v[k+1] = temp; } swap: muli $2, $5, 4 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31 25
26 MIPS Instruction Types Arithmetic & logic (AL) add $s1, $s2, $s3 # $s1 $s2 + $s3 sub $s1, $s2, $s3 # $s1 $s2 - $s3 each AL inst. has exactly 3 operands, all in registers addi $s1, $s2, 100 # s1 $s the constant is kept in the instruction itself Data transfer (load & store) lw $s1, 100($s2) # $s1 memory [$s2+100] (load word) sw $s1, 100($s2) # memory[$s2+100] $s1 (store word) lb $s1, 100($s2) # $s1 memory [$s2+100] (load byte) sb $s1, 100($s2) # memory[$s2+100] $s1 (store byte) load/store bytes commonly used for moving characters (ASCII) 26
27 MIPS Instruction Types Conditional Branch beq $s2, $s3, L1 # branch to L1 if $s2 = $s3 bne $s2, $s3, L1 # branch to L1 if $s2 $s3 beq $s1, $s2, 25 # branch to PC (=4x25) if $s1 = $s2 slt $s2, $s3, $s4 # if ($s3) < ($s4) then $s2 1; # else $s2 0 (set on less than) Unconditional Branch j Loop # go to Loop (jump) j 2500 # go to 4x2500=10000 (jump) jr $t1 # go to $t1 (jump register) jal Proc1 # $ra PC + 4; go to Proc1 (jump & link) 27
28 Compiling a High Level Language Assignment statement (operands in registers, operands in memory) Assignment statement (operands with variable array index) If-then-else statement Loop with variable array index While loop Case / switch statement Procedure that doesn t call another procedure Nested procedures Using strings Using constants Putting things together 28
29 Compiling a High Level Language Arithmetic instructions useful for assignment statements Data transfer instructions useful for arrays or structures Conditional branches useful for if-then-else statements & loops Unconditional branches Case / switch statements, procedure calls and returns 29
30 Basic Blocks A basic block is a sequence of instructions without branches except possibly at the end, and without branch targets or branch labels, except possibly at the beginning One of the first early phases of compilation is breaking the program into basic blocks 30
31 Procedure Call Use the following registers $a0-a3: to pass parameters $v0-v1: to return values for results & expression evaluation $ra: return address $sp: stack pointer (points to top of stack) $fp: frame pointer Use the following instructions jal ProcedureAddress # it jumps to the procedure address and saves # the return address (PC + 4) in register $ra jr $ra # return jump; jump to the address stored in register $ra Use stack a part of memory to save the registers needed by the callee 31
32 Nested Procedures Use stack to preserve values ($a0-a3, $s0-s7, $sp, $ra, stack above $sp, and $fp & $gp if need to use them) No need to preserve $t0-t9, $v0-v1, stack below $sp Frame pointer serves as stable base register within procedure for local references Procedure frame (activation record): High address $fp $fp $sp $fp Arg. registers $sp Return address Saved registers Local arrays & structures Low address $sp 32
33 Instruction Format All instructions are 32 bits 3 types of formats: R-type (Regular) I-type (Immediate) J-type (Jump) Fields (# of bits) op (6): opcode (basic operation) rs (5): 1st register source operand rt (5): 2nd register source opd. rd (5): register destination opd. shamt (5): shift amount funct (6): function (select specific variant of operation in op field) Op rs rt rd shamt funct Op rs rt address/immediate Op target address address/immediate (16) target address (26) 33
34 Instruction Format (Examples) - 1 R-type Examples: add $t0, $s2, $t0 sub $s1, $s2, $s3 slt $s1, $s2, $s3 jr $ra #0s in rt, rd, and shamt fields I-type Examples: lw $s1, 100($s2) #100 appears in address/immediate field sw $s1, 100($s2) #100 appears in address/immediate field beq $s1, $s2, 25 # 25 appears in address/immediate field (eqv. to 100) J-type Examples: j 2500 #2500 appears in target address field (eqv. to 4x2500=10000) jal 2500 #2500 appears in target address field (eqv. to 4x2500=10000) 34
35 Instruction Format (Examples) - 2 R-type Example: add $t0, $s2, $t0 Op=0 rs=18 rt=8 rd=8 shamt=0 funct= I-type Example: lw $s1, 100($s2) Op=35 rs=18 rt= J-type Example: j 2500 Op=
36 Motivation for I-type I Instructions For many operations, one operand = constant C compiler gcc: 52% Spice 69% Design principle: Make the common case fast 36
37 J-Type Instructions Example: j 200# go to location 800 (=200*4) Other J type instruction: jal 200 # jump & link, go to location 800 (=200*4) # $31(ra) PC
38 Assembly Language vs. Machine Language Assembly provides convenient symbolic representation much easier than writing down numbers e.g., destination first Machine language is the underlying reality e.g., destination is no longer first Assembly can provide pseudoinstructions e.g., move $t0, $t1 exists only in Assembly would be implemented using add $t0, $t1, $zero When considering performance you should count real instructions 38
39 Overview of MIPS Simple instructions all 32 bits wide Very structured, no unnecessary baggage Only three instruction formats R I J op rs rt rd shamt funct op rs rt 16 bit address op 26 bit address Addresses are not 32 bits How do we handle this with load and store instructions 39
40 Addresses in Branches and Jumps Instructions: bne $t4,$t5,label beq $t4,$t5,label j Label Formats: Next instruction is at Label if $t4 $t5 Next instruction is at Label if $t4=$t5 Next instruction is at Label I J op rs rt 16 bit address op 26 bit address 40
41 Addresses in Branches Instructions: bne $t4,$t5,label beq $t4,$t5,label Formats: Next instruction is at Label if $t4 $t5 Next instruction is at Label if $t4=$t5 I op rs rt 16 bit address Could specify a register (like lw and sw) and add it to address Use Instruction Address Register (PC = program counter) Most branches are local (principle of locality) Jump instructions just use high order bits of PC Address boundaries of 256 MB 41
42 Addressing Modes Register addressing operand is in a register, e.g. add $s1, $s2, $s3 Base or displacement addressing operand at memory location [register + constant (base)] e.g. 2nd operand in lw $t0, 200($s1) Immediate addressing operand is a constant within instruction e.g. 3rd operand in addi $s1, $s2, 10 PC-relative addressing address = PC (+4) + constant in instruction (*4) e.g. 3rd operand in bne $s0, $s1, Exit Pseudodirect addressing address = PC upper bits concatenated with 26-bit address in inst. 42
43 Addressing Modes 1. Immediateaddressing op rs rt Immediate 2. Register addressing op rs rt rd... funct Registers Register 3. Base addressing op rs rt Address Memory Register + Byte Halfword Word 43
44 Addressing Modes 4. PC-relative addressing op rs rt Address Memory PC + Word 5. Pseudodirect addressing op Address Memory PC Word 44
45 Other Issues MIPS assembler accepts this pseudoinstruction even though it is not found in MIPS architecture: move $t0, $t1 #$t0 $t1 it translates it to: add $t0, $zero, $t1 Other pseudoinstructions: mult, blt, bge, etc. Assembler keeps track of addresses of labels in symbol table Details of assembler, linker, & loader are given in Appendix A Details of MIPS instruction set & architecture in Appendix A % frequency of instruction execution Instruction Class gcc frequency spice frequency Arithmetic 48% 50% Data Transfer 33% 41% Conditional branch 17% 8% Jump & proc. call 2% 1% 45
46 Instruction Set Architecture Classes Use of accumulator (a default register): 1 address instruction; e.g. add A: acc acc + mem[a] e.g. EDSAC, IBM 701, DEC PDP-8, MC 6800, Intel 8008 Use of stack: 0 address instruction; e.g. add: top(stack) top(stack) + next_top(stack) Use of general purpose registers: 2 address instruction; e.g. add A, B: A A + B 3 address instruction; e.g. add A,B,C: A B + C load/store (reg/reg): e.g. MIPS, Sun s SPARC, MC PowerPC, DEC Alpha memory/memory: e.g. DEC VAX memory/register: e.g. DEC VAX, IBM 360, DEC PDP-11, MC 68000, Intel
47 RISC vs. CISC RISC -- Reduced Instruction Set Computer -- philosophy (instruction sets measured by how well compilers used them) Emphasis on software Single-clock, reduced instruction only Register to register: LOAD and STORE are independent instructions Low cycles per second Large code sizes Spends more transistors on memory registers CISC Complex Instruction Set Computer -- Emphasis on hardware Includes multi-clock complex instructions Memory-to-memory: LOAD and STORE incorporated in instructions Small code sizes, high cycles per second Transistors used for storing complex instructions 47
48 Chapter Summary Instruction Types Instruction Format Addressing Modes Classes of Instruction Set Architecture RISC vs. CISC 48
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