Inf2C - Computer Systems Lecture Processor Design Single Cycle
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1 Inf2C - Computer Systems Lecture Processor Design Single Cycle Boris Grot School of Informatics University of Edinburgh
2 Previous lectures Combinational circuits Combinations of gates (INV, AND, OR, NOR..) Output: function of the input only (memory-less) Sequential circuits Output: function of the input and prev inputs Basic memory element: SR-latch (cross-coupled NORs) Clock: synchronizes the operation of the circuit Operation: current states + inputs go through combinational logic. Next states stored in a register on a rising clock edge. Hardware Finite State Machines (FSMs) Registers for states + comb l logic for transitions & outputs Inf2C Computer Systems Boris Grot 2
3 Lecture 9: Processor design single cycle Motivation: Learn how to design a simple processor Two main parts: Datapath: performs the data operations as commanded by the program instructions Control: controls the datapath, memory and I/O according to the program instructions Using: Combinational and sequential circuits described in previous lectures Inf2C Computer Systems Boris Grot 3
4 Design steps / Lecture outline Step 1: Determine the components required by understanding main processor functions Step 2: Build the datapath Step 3: Build the control Show the execution of a few instructions on the designed machine Inf2C Computer Systems Boris Grot 4
5 Main processor functions Fetch instruction from instruction memory Read the register operands Use the ALU for computation Arithmetic, memory address, branch target address Access data memory for load/store Store the result of computation or loaded data into the destination register Update the Program Counter (PC) Inf2C Computer Systems Boris Grot 5
6 Instruction Fetch: common to all insts 32-bit register Fetch the current instruction from instruction memory 32-bit word Inf2C Computer Systems Boris Grot 6
7 Instruction Fetch: common to all insts Concurrent actions! 32-bit register Increment PC by 4 for next instruction Inf2C Computer Systems Boris Grot 7
8 R-Format Instructions 1. Read two register operands 2. Perform arithmetic/logical operation 3. Write register result A bundle of N wires (N=5 here) Register File Inf2C Computer Systems Boris Grot 8
9 Load/Store Instructions 1. Read register operands 2. Calculate address using 16-bit offset Use ALU, but sign-extend offset 3. Read (for load) or write (for store) the memory 4. Load only: update destination register Inf2C Computer Systems Boris Grot 9
10 Branch Instructions (BEQ, BNE) 1. Read register operands 2. Compare operands Use ALU, subtract and check Zero output 3. Calculate target address Sign-extend the immediate (offset) Shift left 2 places (word align) Add to PC + 4 Already calculated by instruction fetch Inf2C Computer Systems Boris Grot 10
11 Branch Instructions Just re-routes wires Sign-bit wire replicated 16 times Inf2C Computer Systems Boris Grot 11
12 Putting It Together: Simplified Datapath Inf2C Computer Systems Boris Grot 12
13 Simplified Datapath Can t just join wires together à Use multiplexers Inf2C Computer Systems Boris Grot 13
14 Full Datapath Inf2C Computer Systems Boris Grot 14
15 Full Datapath Instruction Fetch Inf2C Computer Systems Boris Grot 15
16 Full Datapath R-type/Load/Store datapath Inf2C Computer Systems Boris Grot 16
17 Full Datapath Branch resolution Inf2C Computer Systems Boris Grot 17
18 How to design the control part For all control signals determine which value selects what operation, input, etc. Make truth table of control signal values for each instruction, or instruction group Convert table to combinational circuit Inf2C Computer Systems Boris Grot 18
19 Designing the Main Control Unit Control signals derived from instruction fields R-type Load/ Store Branch 0 rs rt rd shamt funct 31:26 25:21 20:16 15:11 10:6 5:0 35 or 43 rs rt address 31:26 25:21 20:16 15:0 4 rs rt address 31:26 25:21 20:16 15:0 opcode always read read, except for load write for R-type and load sign-extend and add Inf2C Computer Systems Boris Grot 19
20 Datapath with Control Inf2C Computer Systems Boris Grot 20
21 Datapath and control truth table Instruction RegDst ALUSrc Memto- Reg Reg Write Mem Read Mem Write Branch ALUOp1 ALUOp0 R-format lw sw X 1 X beq X 0 X Inf2C Computer Systems Boris Grot 21 Don t Care
22 ALU control ALU operation: Data transfers (ld/st) add Branches sub All other determined by funct field, I[5:0] derived from opcode R-type 0 rs rt rd shamt funct 31:26 25:21 20:16 15:11 10:6 5:0 Inf2C Computer Systems Boris Grot 22
23 ALU control ALU control is hierarchical: Main control specifies which of the 3 op types Add, Sub, or based on Funct bits Second level provides actual ALU control signal ALU operation 0000 AND 0001 OR 0010 add 0110 subtract 0111 set-on-less than actual ALU Control signals Inf2C Computer Systems Boris Grot 23
24 R-type instruction execution Inf2C Computer Systems Boris Grot 24
25 lw execution Inf2C Computer Systems Boris Grot 25
26 beq (taken) execution Inf2C Computer Systems Boris Grot 26
27 Don t fall behind! Read the textbook (Chapter 4 in 4/e & 5/e) Multi-cycle datapath (next lecture): on Learn Tutorials next week Inf2C Computer Systems Boris Grot 27
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