Chapter 7. Microarchitecture. Copyright 2013 Elsevier Inc. All rights reserved.

Transcription

1 Chapter 7 Microarchitecture 1

2 Figure 7.1 State elements of MIPS processor 2

3 Figure 7.2 Fetch instruction from memory 3

4 Figure 7.3 Read source operand from register file 4

5 Figure 7.4 Sign-extend the immediate 5

6 Figure 7.5 Compute memory address 6

7 Figure 7.6 Write data back to register file 7

8 Figure 7.7 Determine address of next instruction for PC 8

9 Figure 7.8 Write data to memory for sw instruction 9

10 Figure 7.9 Datapath enhancements for R-type instruction 10

11 Figure 7.10 Datapath enhancements for beq instruction 11

12 Figure 7.11 Complete single-cycle MIPS processor 12

13 Figure 7.12 Control unit internal structure 13

14 Figure 7.13 Control signals and data flow while executing or instruction 14

15 Figure 7.14 Single-cycle MIPS datapath enhanced to support the j instruction 15

16 Figure 7.15 Critical path for lw instruction 16

17 Figure 7.16 State elements with unified instruction/data memory 17

18 Figure 7.17 Fetch instruction from memory 18

19 Figure 7.18 Read source operand from register file 19

20 Figure 7.19 Sign-extend the immediate 20

21 Figure 7.20 Add base address to offset 21

22 Figure 7.21 Load data from memory 22

23 Figure 7.22 Write data back to register file 23

24 Figure 7.23 Increment PC by 4 24

25 Figure 7.24 Enhanced datapath for sw instruction 25

26 Figure 7.25 Enhanced datapath for R-type instructions 26

27 Figure 7.26 Enhanced datapath for beq instruction 27

28 Figure 7.27 Complete multicycle MIPS processor 28

29 Figure 7.28 Control unit internal structure 29

30 Figure 7.29 Fetch 30

31 Figure 7.30 Data flow during the fetch step 31

32 Figure 7.31 Decode 32

33 Figure 7.32 Data flow during the decode step 33

34 Figure 7.33 Memory address computation 34

35 Figure 7.34 Data flow during memory address computation 35

36 Figure 7.35 Memory read 36

37 Figure 7.36 Memory write 37

38 Figure 7.37 Execute R-type operation 38

39 Figure 7.38 Branch 39

40 Figure 7.39 Complete multicycle control FSM 40

41 Figure 7.40 Main controller states for addi 41

42 Figure 7.41 Multicycle MIPS datapath enhanced to support the j instruction 42

43 Figure 7.42 Main controller state for j 43

44 Figure 7.43 Timing diagrams: (a) single-cycle processor, (b) pipelined processor 44

45 Figure 7.44 Abstract view of pipeline in operation 45

46 Figure 7.45 Single-cycle and pipelined datapaths 46

47 Figure 7.46 Corrected pipelined datapath 47

48 Figure 7.47 Pipelined processor with control 48

49 Figure 7.48 Abstract pipeline diagram illustrating hazards 49

50 Figure 7.49 Abstract pipeline diagram illustrating forwarding 50

51 Figure 7.50 Pipelined processor with forwarding to solve hazards 51

52 Figure 7.51 Abstract pipeline diagram illustrating trouble forwarding from lw 52

53 Figure 7.52 Abstract pipeline diagram illustrating stall to solve hazards 53

54 Figure 7.53 Pipelined processor with stalls to solve lw data hazard 54

55 Figure 7.54 Abstract pipeline diagram illustrating flushing when a branch is taken 55

56 Figure 7.55 Abstract pipeline diagram illustrating earlier branch decision 56

57 Figure 7.56 Pipelined processor handling branch control hazard 57

58 Figure 7.57 Pipelined processor handling data dependencies for branch instructions 58

59 Figure 7.58 Pipelined processor with full hazard handling 59

60 Figure 7.59 MIPS single-cycle processor interfaced to external memory 60

61 Figure 7.60 Assembly and machine code for MIPS test program 61

62 Figure 7.61 Contents of memfile.dat 62

63 Figure 7.62 Datapath supporting overflow and undefined instruction exceptions 63

64 Figure 7.63 Datapath supporting mfco 64

65 Figure 7.64 Controller supporting exceptions and mfc0 65

66 Figure 7.65 Cycle time and instruction time versus the number of pipeline stages 66

67 Figure bit branch predictor state transition diagram 67

68 Figure 7.67 Superscalar datapath 68

69 Figure 7.68 Abstract view of a superscalar pipeline in operation 69

70 Figure 7.69 Program with data dependencies 70

71 Figure 7.70 Out-of-order execution of a program with dependencies 71

72 Figure 7.71 Out-of-order execution of a program using register renaming 72

73 Figure 7.72 Packed arithmetic: four simultaneous 8-bit additions 73

74 Figure microprocessor chip 74

75 Figure microprocessor chip 75

76 Figure microprocessor chip 76

77 Figure 7.76 Pentium microprocessor chip 77

78 Figure 7.77 Pentium III microprocessor chip 78

79 Figure 7.78 Pentium 4 microprocessor chip 79

80 Figure 7.79 Core Duo microprocessor chip 80

81 Figure 7.80 Core i7 microprocessor chip (Source: Courtesy Intel) 81

82 UNN Figure 1 82