Chapter 1: Basics of Microprocessor [08 M]

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1 Microprocessor: Chapter 1: Basics of Microprocessor [08 M] It is a semiconductor device consisting of electronic logic circuits manufactured by using either a Large scale (LSI) or Very Large Scale (VLSI) Integration Technique. It includes the ALU, register arrays and control circuits on a single chip. The microprocessor has a set of instructions, designed internally, to manipulate data and communicate with peripherals. This process of data manipulation and communication is determined by the logic design of the microprocessor called the architecture. List of Intel Microprocessors: Year Name Bit Size (Pentium) Pentium Pro Pentium II Pentium III Pentium IV Itanium 64 Salient Features of 8085 Microprocessor: is an 8-bit microprocessor i.e. it can accept or provide (read or write) 8- bit data simultaneously. It can read or write or perform arithmetic and logical operations on 8 bit data at a time. - It is single chip NMOS (N-type Metal Oxide semiconductor) device implemented with 6200 transistors. - It is 40 pin IC - It requires a single +5V power supply. - It provides on-chip clock generator so 8085 microprocessor does not require external clock generator. - It has an 8-bit data bus and 16-bit address bus - Normally the 8085 operates at clock frequency of 3MHz o Maximum Clock Frequency 5 MHz o Minimum Clock Frequency 500 KHz - Provides 5 Hardware interrupts and 8 software Interrupts - Provides two serial I/O lines hence serial peripherals can be interfaced with 8085 directly. Microprocessor & Programming [MAP-17431] M.S.Karande Page 1 of 10

2 - Can generate 8-bit I/O address so 2^8=256 input and 256 outport can be accessed. - Provides 74 instructions with 5 addressing modes (Register, Direct, Immediate, Indirect and Implied) - Requires a two phase 50% duty cycle TTL Clock R/W Memory CPU SYSTEM BUS DATA AND PROGRAMS I/O Microprocessor Architecture CPU REGISTERS I N ALU T E R TIMING AND F CONTROL A UNIT C E µp MEMORY I/O SYSTEM BUS µp is a sequential circuit hence it has clock Interface: Set of pins through which it is connected to system bus and system bus is connected to memory and I/O. Registers are set of flip-flops used to store Instruction and Data. Microprocessor & Programming [MAP-17431] M.S.Karande Page 2 of 10

Architecture of 8085 Microprocessor is divided into different groups as: ALU: Arithmetic and Logic Unit It performs following arithmetic and logical operations: ARITHMETIC OPERATIONS LOGICAL

3 Architecture of 8085 Microprocessor is divided into different groups as: ALU: Arithmetic and Logic Unit It performs following arithmetic and logical operations: ARITHMETIC OPERATIONS LOGICAL OPERATIONS ADDITION AND SUBTRACTION OR INCREMENT DECREMENT EXOR NOT CLEAR COMPARE SHIFT/ROTATE COMPLEMENT Register Array: Classification is done in two ways First Classificationi) General Purpose Registers such as (B, C, D, E, H, L) ii) Special Purpose Registers such as Accumulator, Program Counter, Flag Register and Stack Pointer. Second Classificationi) User Accessible Registers (All Above Registers) ii) User Not Accessible Registers (IR (Instruction Register), Temp Reg) Accumulator Temp Registers General Purpose Registers Register Pairs: BC, DE and HL Stack Pointer Program Counter Accumulator (A) Accumulator is an 8-bit register associated with the ALU denoted by A. It is used to hold one of the operands of an arithmetic/ logical operation. It serves as one input to the ALU. The other operand for an arithmetic or logical operation must be stored either in the memory or in one of the general purpose registers. The final result of an arithmetic /logical operation is placed in the accumulator. General Purpose Registers The 8085 Microprocessor contains 6 8-bit general purpose registers. They are: B, C, D, E, H & L Registers. Microprocessor & Programming [MAP-17431] M.S.Karande Page 3 of 10

4 To hold 16-bit data a combination of two 8 bit registers can be employed. The combination of two 8-bit register is known as Register Pair. The valid register pairs in the 8085 are: B-C, D-E & H-L. The programmer cannot form a register pair by selecting any two registers of his choice. Program Counter (PC) It is a 16- bit special purpose register It is used to hold the memory address of the next instruction to be executed. It keeps the track of memory address of the instruction in a program while they are being executed. The microprocessor increment the contents of the program counter during the execution of an instruction so that it points to the address of the next instruction in the program at the end of the execution of an instruction. Stack Pointer (SP) SP is a 16-bit register holds the address of the top element of data stored in the stack. 2997H 2998H 2999H Stack Pointer=2997H Instruction Register (IR) and Decoder The instruction register and the decoder are part of the ALU. When an instruction is fetched from memory, it is loaded in the instruction register. The decoder decodes the instruction and establishes the sequence of events to follow. The instruction register is not programmable and cannot be accessed through any instruction. Temporary Registers Two additional registers called temporary registers W and Z are there. These registers are used to hold 8-bit data during the execution of some instructions. However because they are used internally, they are not available to the programmer. Flag Register (PSW/Status Flag) The flags are affected by the arithmetic and logic operations in the ALU. Sign Flag Used for indicating the sign of the data in the accumulator The sign flag is set if negative (1 negative) The sign flag is reset if positive (0 positive) Microprocessor & Programming [MAP-17431] M.S.Karande Page 4 of 10

5 Zero Flag Is set if result obtained after an operation is Carry Flag -Is set if there is a carry or borrow from arithmetic operation - Flag is reset if the result is not zero Carry Borrow Auxiliary Carry Flag In an arithmetic operation when a carry is generated by digit D3 and passed on to digit D4, the AC flag is set. The flag is used only internally for BCD (Binary Coded Decimal) operations and is not available for the programmer to change the sequence of a program with a jump instruction. Is set if there is a carry out of bit 3 Parity Flag After an arithmetic /logical operation, if the result has an even number of 1 s the flag is set. If it has an odd number if 1 s the flag is reset. Is set if parity is even Is cleared if parity is odd For eg data byte even parity Timing and Control Unit It coordinates and control all internal units and generated the control signals necessary for communication between the microprocessor and peripherals. This unit synchronizes all the microprocessor operations with the clock. Interrupt Control Group This block accepts different interrupt request input such as TRAP, RST 7.5, RST 6.5, INTR When a valid interrupt request is present it informs control logic to take action in response to each signal Maskable Interrupts are 1. INTR (Lowest Priority) 2. RST RST RST 5.5 Non-Maskable interrupts are TRAP (Highest Priority) For INTR, it generates INTA signal to acknowledge the same. Microprocessor & Programming [MAP-17431] M.S.Karande Page 5 of 10

Serial I/O Control Group SID:- Serial Input Data It receives serial data from external devices to the accumulator SOD :-Serial Output data SOD pin is used to transmit data serially from accumulator

6 Serial I/O Control Group SID:- Serial Input Data It receives serial data from external devices to the accumulator SOD :-Serial Output data SOD pin is used to transmit data serially from accumulator to the external devices connected to the pin. Pin Diagram and Description: 8085 is implemented in 40 pin Dual Inline Package [DIP] All the signals can be calssified into 6 groups: 1) Address Bus 2) data Bus 3) Control and Status Signals 4) Power Supply and Frequency Signals 5) Externally initiated signals and 6) Serial I/O Ports. 1) Address Bus: The 8085 has 16 signal lines (pins) that are used as the address bus however these lines are split into two segments A15-A8 and AD7-AD0. The signal lines, A15-A8 are unidirectional and used for the most significant bits called the high order address of 16-bit address. The signal lines AD7-Ad0 are used for dual purpose. 2) Multiplexed Address/Data Bus The signal lines AD7-AD0 are bidirectional: they serve a dual purpose. They are used as the low order address bus as well as the data bus. In executing an instruction during the earlier part of the cycle, these lines are used as the low order address bus. During the later part of the cycle these lines are used as the data bus. (This is known as multiplexing the bus) Microprocessor & Programming [MAP-17431] M.S.Karande Page 6 of 10

7 Microprocessor & Programming [MAP-17431] M.S.Karande Page 7 of 10

8 3) Control and Status Signals i) RD (Read): This is active low, output control signal used to read data from memory or an I/O Device. ii) WR (Write): This is an active low, output control signal used to write data to memory or an I/O Device iii) ALE (Address Latch Enable): This is an output signal used to inform that the content on AD0-AD7 lines is lower order 8-bit address of 16-bit address when ALE goes high. When ALE =0 it indicates the content on AD0-AD7 lines is 8-bit data ALE High Address Low Data iv) IO/M : It is status signal which distinguishes between memory and I/O operations High-> I/O operation Low -> Memory Operation v) S1 and S0: These are status signals which distinguishes various operations given in table 4) Power Supply and Clock Frequency: The power supply and frequency signals are as follows: i) Vcc: +5V Power Supply ii) Vss: Ground Reference iii) X1, X2: These are clock input pins connected to the crystal, LC or RC circuit (Inductive Capacitor Network /Resistor Capacitor circuit) The crystal frequency is divided by two and used as operating frequency. iv) CLK (out): Clock Output This signal can be used as the system clock for other devices. Microprocessor & Programming [MAP-17431] M.S.Karande Page 8 of 10

9 5) Externally Initiated Signals including Interrupts i) INTR (Input) Interrupt Request: INTR is active high level triggered general purpose interrupt. ii)inta (Output) Interrupt Acknowledge: This is used to acknowledge an interrupt iii) RST 7.5, RST 6.5, RST 5.5 (Inputs) Restart interrupts These are active high Maskable Hardware interrupts RST 7.5 is edge triggered interrupt. RST 6.5 and RST 5.5 are level triggered interrupts. When RST 7.5,RST 6.5 and RST 5.5 occurs then the microprocessor transfer program control to vector address 003CH,0034H and 002C respectively. iv) TRAP (Input) This is a non-maskable interrupt and has the highest priority. v) HOLD and HLDA HOLD (Input): This signal indicates that a peripheral such as a DMA (Direct Memory controller) is requesting the use of the address and data buses. HLDA (Output) Hold Acknowledge: This signal acknowledges the HOLD request indicating transfer of buses. HLDA 8085 HOLD All Buses DMA DRQ Peripheral Device vi) READY (Input): It is used by the microprocessor to check whether a peripheral is ready or not for data transfer. If READY pin is high then the microprocessor completes the operation and proceeds for next operation When READY pin is low, the microprocessor will wait until it goes high This signal is used to synchronize slower peripheral with faster processor. vii) RESET IN: Reset Input This is an active low input reset signal used to reset microprocessor. When the signal on this pin goes low, the program counter is set to zero and microprocessor is reset buses are tri-stated. viii) RESET OUT: This signal indicates that the microprocessor is being reset. The signal can be used to reset other devices. 6) Serial I/O Ports (SID and SOD): 8085 has two signals to implement the serial transmission: SID (Serial input data) and SOD (Serial Output Data). In serial transmission data bits are sent over a single line one bit at a time such as transmission over telephone lines. Microprocessor & Programming [MAP-17431] M.S.Karande Page 9 of 10

10 Software Interrupts of 8085 microprocessor are: 1) RST 0 2) RST 1 3) RST 2 4) RST 3 5) RST 4 6) RST 5 7) RST 6 8) RST 7 Differentiate between NMI and MI Sr. No NMI(Non-Maskable Interrupt) MI (Maskable Interrupt) 1 These interrupts cannot be avoided by Microprocessor 2 These interrupts are edge as well as level triggered These interrupts can be avoided by Microprocessor These interrupts may be either edge or level triggered 3 Response Time is fast Response Time is slow 4 No instruction is available for masking Instructions are available for masking and non-masking 5 Eg TRAP Eg RST 7.5,RST 6.5,RST 5.5 etc Microprocessor & Programming [MAP-17431] M.S.Karande Page 10 of 10

Basics of Microprocessor

Unit 1 Basics of Microprocessor 1. Microprocessor Microprocessor is a multipurpose programmable integrated device that has computing and decision making capability. This semiconductor IC is manufactured