UNIT-I. 1.Draw and explain the Architecture of a 8085 Microprocessor?

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1 UNIT-I INTRODUCTION TO MICROPROCESSOR A common way of categorizing microprocessors is by the no. of bits that their ALU can work with at a time. (i) The first commercially available microprocessor was the INTEL 4004, produced in It has 3200 PMOS transistors. It is a 4-bit device used in calculator. (ii) In 1972, Intel came out with the 8008 which is 8-bit. (iii) In 1974, Intel announced the 8080, which had a larger instruction set then used NMOS transistors, so it operated much faster than the The 8080 is referred to as a Second generation Microprocessor (iv) Next Motorola came out with the MC6800, another 8-bit CPU The 6800 had the advantage that it req. only a +5v supply rather than -5v, +5v 5+12 v (v) Next is the MOS technology 6502 CPU used in Apple II microcomputer, and zilogz80, used as CPU in the Radio shack TRS-80 micro computer (vi) Dedicated or Embedded controllers: In 1976, Intel introduced the 8048, which contains an 8-bit CPU, RAM, ROM and some I/O parts all in one 40-pin package. These devices are often referred to as Microcontrollers. (vii) Bit Slice Processors: An advanced micro devices 2900 family of devices. It includes 4-bit ALUS, MUXS. The term slice comes from the fact that these parts can be connectd in parallel to work. (viii) General Purpose CPUS: After Motorola came out with MC6800, Intel produced the 8085, an up grade of 8080 that required +5V supply. Motorola then produced MC6809 (8-bit) In 1978, Intel came out with the 8086, which is16-bit processor. Next Motorola came out with 16-bit MC The last evolution s 32-bit processor, Intel 80386, MC Draw and explain the Architecture of a 8085 Microprocessor? The salient features of 8085 µp are: It is a 8 bit microprocessor. It is manufactured with N-MOS technology. It has 16-bit address bus and hence can address up to 216 = bytes (64KB) memory locations through A0-A15. The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 AD7.

2 Data bus is a group of 8 lines D0 D7. It supports external interrupt request. A 16 bit program counter (PC) A 16 bit stack pointer (SP) Six 8-bit general purpose register arranged in pairs: BC, DE, HL. It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock There are five H/W Interrupts, in order of decreasing priority: TRAP RST 7.5 RST 6.5 RST 5.5 INTR TRAP is unmaskable The FLAG Register:

3 The sign flag: The bit 7 (MSB) of the 8-bits is used for the sign of data in the accumulator, then the numbers can be used in the range -128 to positive 1 negative The zero flag: If the result obtained after executing an instruction is zero. ZF = 1 Other wise ZF = 0 If result is zero, and carry is present then both ZF=1 and CF = 1 (iii) The carry flag: In both addition and subtraction involving two 8-bit no.s, Addition: overflow from higher order bit substation: Borrow DF is set to 1. The Auxiliary carry flag (AC): This flag is used in BCD arithmetic. This is set for an over flow out of bit 3. The parity flag: Parity is defined by the no. of 1 s present in the Accumulator. If parity is even, P 1 If parity is odd, P 0 The Accumulator, the flag reg. and f a few temporary registers constitute the ALU. The FLAG Register: The sign flag: The bit 7 (MSB) of the 8-bits is used for the sign of data in the accumulator, then the numbers can be used in the range -128 to positive 1 negative The zero flag: If the result obtained after executing an instruction is zero. ZF = 1 Other wise ZF = 0 If result is zero, and carry is present then both ZF=1 and CF = 1 (iii) The carry flag: In both addition and subtraction involving two 8-bit no.s, Addition: overflow from higher order bit substation: Borrow

4 DF is set to 1. The Auxiliary carry flag (AC): This flag is used in BCD arithmetic. This is set for an over flow out of bit 3. The parity flag: Parity is defined by the no. of 1 s present in the Accumulator. If parity is even, P 1 If parity is odd, P 0 The Accumulator, the flag reg. and f a few temporary registers constitute the ALU. THE 8086 MICRO PROCESSOR FAMILY The Intel 8086 is a 16-bit Micro processor. The term 16-bit means that its ALU, its internal registers, and most of its instructions are designed to work with16-bit binary words. It has 16-bit data bus, so it can read data from or write data to memory and ports either 16 bits or 8-bits at a time. It has 20-bit address bus, so it can address 220 ( 1,048,576) memory locations. Each of the 1,048,576 memory addresses of the 8086 rep. a byte wide location. The Intel 8088 has same ALU, the same registers, and the same instruction set as (8086: 16-bit add.bus and 8-bit data bus) The Intel is an improved version of 8086 and is an improved version of The Intel is a 16-bit, advanced version of 8086 which was specifically designed for used in a multiuser or multi tasking computer. Next Intel is a 32-bit up which can directly address up to 4 GB of memory. Lastly 80486, is an evolutionary step up from the

5 2.Explain thepin description of 8086? The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged in a 40 pin CERDIP or plastic package. The 8086 operates in single processor or multiprocessor configuration to achieve high performance. The pins serve a particular function in minimum mode (single processor mode ) and other function in maximum mode configuration (multiprocessor mode ). The 8086 signals can be categorised in three groups. o The first are the signal having common functions in minimum as well as maximum mode. o The second are the signals which have special functions for minimum mode o The third are the signals having special functions for maximum mode. The following signal descriptions are common for both modes. AD15-AD0 : These are the time multiplexed memory I/O address and data lines. o Address remains on the lines during T1 state, while the data is available on the data bus during T2, T3, Tw and T4. These lines are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles.

6 A19/S6,A18/S5,A17/S4,A16/S3 : These are the time multiplexed address and status lines. o During T1 these are the most significant address lines for memory operations. o During I/O operations, these lines are low. o During memory or I/O operations, status information is available on those lines for T2,T3,Tw and T4. o The status of the interrupt enable flag bit is updated at the beginning of each clock cycle. o The S4 and S3 combinely indicate which segment register is presently being used for memory accesses as in below fig. o These lines float to tri-state off during the local bus hold acknowledge. The status line S6 is always low. o The address bit are separated from the status bit using latches controlled by the ALE signal. S4 S3 0 0 Indication Alternate Data Stack Code or None Data Whole word Upper byte from or to even address Lower byte from or to even address BHE/S7 : The bus high enable is used to indicate the transfer of data over the higher order ( D15-D8 ) data bus as shown in table. It goes low for the data transfer over D15- D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of data bus. The status information is available during T2, T3 and T4. The signal is active low and tristated during hold. It is low during T1 for the first pulse of the interrupt acknowledge cycle. RD Read : This signal on low indicates the peripheral that the processor is performing memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of any read cycle. The signal remains tristated during the hold acknowledge. READY : This is the acknowledgement from the slow device or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the the signal is active high.

7 INTR-Interrupt Request : This is a triggered input. This is sampled during the last clock cycles of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by resulting the interrupt enable flag. This signal is active high and internally synchronized. TEST : This input is examined by a WAIT instruction. If the TEST pin goes low, execution will continue, else the processor remains in an idle state. The input is synchronized internally during each clock cycle on leading edge of clock. CLK- Clock Input : The clock input provides the basic timing for processor operation and bus control activity. Its an asymmetric square wave with 33% duty cycle. M/IO 28 O STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to distinguish a memory access from an I/O access. M/IO becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle (M e HIGH, IO e LOW). M/IO floats to 3-state OFF in local bus ``hold acknowledge''. WR 29 O WRITE: indicates that the processor is performing a write memory or write I/O cycle, depending on the state of the M/IO signal. WR is active for T2, T3 and TW of any write cycle. It is active LOW, and floats to 3-state OFF in local bus ``hold acknowledge''. INTA 24 O INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3 and TW of each interrupt acknowledge cycle. ALE 25 O ADDRESS LATCH ENABLE: provided by the processor to latch the address into the 8282/8283 address latch. It is a HIGH pulse active during T1 of any bus cycle. Note that ALE is never floated. DT/R 27 O DATA TRANSMIT/RECEIVE: needed in minimum system that desires to use an 8286/8287 data bus transceiver. It is used to control the direction of data flow through the transceiver. Logically DT/R is equivalent to S1 in the maximum mode, and its timing is the same as for M/IO. (T e HIGH, R e LOW.) This signal floats to 3-state OFF in local bus ``hold acknowledge''. DEN 26 O DATA ENABLE: provided as an output enable for the 8286/8287 in a minimum system which uses the transceiver. DEN is active LOW during each memory and I/O access and for INTA cycles. For a read or INTA cycle it is active from the middle of T2 until the middle of T4, while for a write cycle it is active from the beginning of T2 until the middle of T4. DEN floats to 3- state OFF in local bus ``hold acknowledge''. HOLD, 31, 30 I/O HOLD: indicates that another master is requesting a local bus ``hold.'' To be HLDA acknowledged, HOLD must be active HIGH. The processor receiving the ``hold'' request will issue HLDA (HIGH) as an acknowledgement in the middle of a T4 or Ti clock cycle. Simultaneous with the issuance of HLDA

8 the processor will float the local bus and control lines. After HOLD is detected as being LOW, the processor will LOWer the HLDA, and when the processor needs to run another cycle, it will again drive the local bus and control lines. Hold acknowledge (HLDA) and HOLD have internal pull-up resistors. The same rules as for RQ/GT apply regarding when the local bus will be released. HOLD is not an asynchronous input. External synchronization should be provided if the system cannot otherwise guarantee the setup time. 3.Draw and explain the Architecture of a 8086 Microprocessor? 8086 Internal Architecture: 8086 has two blocks BIU and EU. The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes instructions from the instruction system byte queue. Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register. BUS INTERFACE UNIT: It provides a full 16 bit bidirectional data bus and 20 bit address bus. The bus interface unit is responsible for performing all external bus operations. Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control. The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture. This queue permits prefetch of up to six bytes of instruction code. When ever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction. These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle. After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output.

9 The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. If the queue is full and the EU is not requesting access to operand in memory. These intervals of no bus activity, which may occur between bus cycles are known as Idle state. If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle. The BIU also contains a dedicated adder which is used to generate the 20bit physical address that is output on the address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address. For example: The physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register. The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write. EXECUTION UNIT The Execution unit is responsible for decoding and executing all instructions. The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O and perform the operation specified by the instruction on the operands. During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction. If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue. When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions. Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue.

10 GENERAL PURPOSE REGISTERS 8086 CPU has 8 general purpose registers, each register has its own name: AX - the accumulator register (divided into AH / AL): 1. Generates shortest machine code 2. Arithmetic, logic and data transfer 3. One number must be in AL or AX 4. Multiplication & Division 5. Input & Output BX - the base address register (divided into BH / BL). CX - the count register (divided into CH / CL): 1. Iterative code segments using the LOOP instruction 2. Repetitive operations on strings with the REP command 3. Count (in CL) of bits to shift and rotate DX - the data register (divided into DH / DL): 1. DX:AX concatenated into 32-bit register for some MUL and DIV operations 2. Specifying ports in some IN and OUT operations

11 SI - source index register: 1. Can be used for pointer addressing of data 2. Used as source in some string processing instructions 3. Offset address relative to DS DI - destination index register: 1. Can be used for pointer addressing of data 2. Used as destination in some string processing instructions 3. Offset address relative to ES BP - base pointer: 1. Primarily used to access parameters passed via the stack 2. Offset address relative to SS SP - stack pointer: 1. Always points to top item on the stack 2. Offset address relative to SS 3. Always points to word (byte at even address) 4. An empty stack will had SP = FFFEh

12 FLAGS REGISTER Flags Register - determines the current state of the processor. They are modified automatically by CPU after mathematical operations, this allows to determine the type of the result, and to determine conditions to transfer control to other parts of the program. Generally you cannot access these registers directly. 1. Carry Flag (CF) - this flag is set to 1 when there is an unsigned overflow. For example when you add bytes (result is not in range ). When there is no overflow this flag is set to Parity Flag (PF) - this flag is set to 1 when there is even number of one bits in result, and to 0 when there is odd number of one bits. 3. Auxiliary Flag (AF) - set to 1 when there is an unsigned overflow for low nibble (4 bits). 4. Zero Flag (ZF) - set to 1 when result is zero. For non-zero result this flag is set to Sign Flag (SF) - set to 1 when result is negative. When result is positive it is set to0. (This flag takes the value of the most significant bit.) 6. Trap Flag (TF) - Used for on-chip debugging. 7. Interrupt enable Flag (IF) - when this flag is set to 1 CPU reacts to interrupts from external devices. 8. Direction Flag (DF) - this flag is used by some instructions to process data chains, when this flag is set to 0 - the processing is done forward, when this flag is set to 1the processing is done backward. 9. Overflow Flag (OF) - set to 1 when there is a signed overflow. For example, when you add bytes

13 4. ExplainMinimum Mode 8086 System with timing diagrams? A minimum mode of 8086 configuration depicts a stand alone system of computer where no other processor is connected. This is similar to 8085 block diagram with the following difference. The Data transceiver block which helps the signals traveling a longer distance to get boosted up. Two control signals data transmit/ receive are connected to the direction input of transceiver (Transmitter/Receiver) and DEN* signal works as enable for this block. Read Cycle Timing Diagram for Minimum Mode In the bus timing diagram, data transmit / receive signal goes low (RECEIVE) for Read operation. To validate the data, DEN* signal goes low. The Address/ Status bus carries A16 to A19 address lines during BHE* (low) and for the remaining time carries Status information. The Address/Data bus carries A0 to A15 address information during ALE going high and for the remaining time it carries data. The RD* line going low indicates that this is a Read operation. The curved arrows indicate the relationship between valid data and RD* signal. The T W is Wait time needed to synchronize the fast processor with slow memory etc. The Ready pin is checked to see whether any peripheral needs more time for data transmission.

14 Write Cycle Timing Diagram for Minimum Operation This is the same as Read cycle Timing Diagram except that the DT/R* line goes high indicating it is a Data Transmission operation for the processor to memory / peripheral. Again DEN* line goes low to validate data and WR* line goes low, indicating a Write operation.

15 Bus Request & Bus Grant Timings in Minimum Mode System The HOLD and HLDA timing diagram indicates in Time Space HOLD (input) occurs first and then the processor outputs HLDA (Hold Acknowledge).

16 5. Explain the Maximum Mode 8086 System with timing diagrams? In the maximum mode of operation of 8086, wherein either a numeric coprocessor of the type 8087 or another processor is interfaced with The Memory, Address Bus, Data Buses are shared resources between the two processors. The control signals for Maximum mode of operation are generated by the Bus Controller chip The three status outputs S0*, S1*, S2* from the processor are input to The outputs of the bus controller are the Control Signals, namely DEN, DT/R*, IORC*, IOWTC*, MWTC*, MRDC*, ALE etc. These control signals perform the same task as the minimum mode operation. However the DEN is an active HIGH signal which has to be converted to active LOW by means of an inverter.

17 Memory Read Timing in Maximum Mode Here MRDC* signal is used instead of RD* as in case of Minimum Mode S0* to S2* are active and are used to generate control signal. Memory Write Timing in Maximum Mode Here the maximum mode write signals are shown. Please note that the T states correspond to the time during which DEN* is LOW, WRITE Control goes LOW, DT/R* is HIGH and data output in available from the processor on the data bus.

18 RQ / GT Timings in Maximum Mode Request / Grant pin may appear that both signals are active low. But in reality, Request signal goes low first (input to processor), and then the processor grants the request by outputting a low on the same pin.

UNIT II OVERVIEW MICROPROCESSORS AND MICROCONTROLLERS MATERIAL. Introduction to 8086 microprocessors. Architecture of 8086 processors

UNIT II OVERVIEW MICROPROCESSORS AND MICROCONTROLLERS MATERIAL. Introduction to 8086 microprocessors. Architecture of 8086 processors OVERVIEW UNIT II Introduction to 8086 microprocessors Architecture of 8086 processors Register Organization of 8086 Memory Segmentation of 8086 Pin Diagram of 8086 Timing Diagrams for 8086 Interrupts of