CMPEN 411 VLSI Digital Circuits. Lecture 01: Introduction
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1 CMPEN 411 VLSI Digital Circuits Kyusun Choi Lecture 01: Introduction CMPEN 411 Course Website link at: [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L01 S1
2 How Do the Pieces Fit Together? Application Operating System Memory system Compiler Instr. Set Proc. Digital Design Circuit Design Firmware Datapath & Control I/O system Instruction Set Architecture Coordination of many levels of abstraction Under a rapidly changing set of forces Design, measurement, and evaluation CMPEN 411 L01 S2
3 Course Contents Introduction to digital integrated circuits CMOS devices and manufacturing technology. CMOS logic gates and their layout. Propagation delay, noise margins, and power dissipation. Combinational (e.g., arithmetic) and sequential circuit design. Memory circuit design. Course goals Ability to design and implement CMOS digital circuits and optimize them with respect to different constraints: size (cost), speed, power dissipation, and reliability Course prerequisites EE 310. Electronic Circuit Design CMPEN 471. Logic Design of Digital Systems CMPEN 411 L01 S3
4 Background from CMPEN 471 and EE 310 Basic circuit theory resistance, capacitance, inductance MOS gate characteristics Hardware description language VHDL or verilog Use of modern EDA tools simulation, synthesis, validation (e.g., Synopsys) schematic capture tools (e.g., LogicWorks) Logic design logical minimization, FSMs, component design CMPEN 411 L01 S4
5 Course Structure CMPEN 411 L01 S5 Design and tool intensive class Industrial Standard toolset for layout - Online documentation and tutorials HSPICE for circuit simulation unix (Sun/Solaris) operating system environment Lectures: 2 weeks on the CMOS inverter 3 weeks on static and dynamic CMOS gates 2 weeks on C, R, and L effects 2 week on sequential CMOS circuits 2 weeks on design of datapath structures 2 weeks on memory design 1 week on design for technology scaling, trends Schedule is on-line syllabus
6 What is the most important invention for the last 50 years? CMPEN 411 L01 S6
7 The evolution of IC When was the first transistor invented? A B C D The inventors were in which company? A. IBM B. Bell Lab C. TI D. Motorola CMPEN 411 L01 S7
8 The evolution of IC When was the first transistor invented? Modern-day electronics began with the invention in 1947 of the transfer resistor, also known as the bi-polar transistor by Bardeen et.al at Bell Laboratories CMPEN 411 L01 S8
9 The evolution of IC When was the first IC invented? A B C D The inventor was with which company? A. IBM B. Bell Labs C. TI D. Motorola CMPEN 411 L01 S9
10 The evolution of IC When was the first IC (integrated circuit) invented? In 1958 the integrated circuit was born when Jack Kilby at Texas Instruments successfully interconnected, by hand, several transistors, resistors and capacitors on a single substrate CMPEN 411 L01 S10
11 Transistor Revolution Transistor Bardeen et.al. (Bell Labs) in 1947 Bipolar transistor Schockley in 1949 First bipolar digital logic gate Harris in 1956 First monolithic IC Jack Kilby in 1958 First commercial IC logic gates Fairchild 1960 CMPEN 411 L01 S11
12 MOSFET Technology MOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935 CMOS 1960 s, but plagued with manufacturing problems (used in watches due to their power limitations) PMOS in 1960 s (calculators) NMOS in 1970 s (4004, 8080) for speed CMOS in 1980 s preferred MOSFET technology because of power benefits BiCMOS, Gallium-Arsenide, Silicon-Germanium SOI, Copper-Low K, strained silicon, High-k gate oxide... CMPEN 411 L01 S12
13 CMPEN 411 VLSI Digital Circuits Kyusun Choi VLSI Chip Pictures CMPEN 411 L01 S13
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17 Fig. 12 Increase in wafer sizes, showing the increased number of dice (chips) per wafer available when increasing the wafer area. (a) 100-mm (4-in.) wafer. (b) 150-mm (6-in.) wafer. (c) 300-mm (12-in.) wafer. (Intel Corp.) Fig. 7 Person with lint-free garments in a vertical laminar-flow clean room for integrated-circuit fabrication with 300-mm (12-in.) wafer. (Personnel do not handle wafers in this manner. This was done just for the photograph.) (Intel Corp.) CMPEN 411 L01 S17
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29 Fig. 1. Cross-section of a 64-bit high-speed processor in a 90nm technology. (Courtesy: IBM) CMPEN 411 L01 S29
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36 Programmable Logic Gate Array CMPEN 411 L01 S36
37 Programmable Logic Gate Array CMPEN 411 L01 S37
38 Programmable Logic Gate Array CMPEN 411 L01 S38
39 Programmable Logic Gate Array CMPEN 411 L01 S39
40 Programmable Logic Gate Array CMPEN 411 L01 S40
41 Programmable Logic Gate Array CMPEN 411 L01 S41
42 CMPEN 411 L01 S42
43 Worldwide Semiconductor Revenue Source: ISSCC 2003 G. Moore No exponential is forever, but forever can be delayed CMPEN 411 L01 S43
44 Transistors shipped per year How many transistors you can buy with 1$? CMPEN 411 L01 S44
45 Average Transistor Price by Year CMPEN 411 L01 S45
46 1 Wafer in 1964 vs. 300 mm (12 ) Wafer in 2003 CMPEN 411 L01 S46
47 The IC in 1961 vs. Intel Pentium 4 in 2004 CMPEN 411 L01 S47
48 Moore s Law In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 months (i.e., grow exponentially with time). Amazingly visionary million transistor/chip barrier was crossed in the 1980 s transistors, 108 KHz clock (Intel 4004) Million transistors (Ultra Sparc III) Million, 2 GHz clock (Intel P4) Million, 3.4Ghz (Intel P4 Prescott) Feb Million, IBM Cell processor, Billion, 1.6Ghz (Intel Itanium-2)-2006, Sept. CMPEN 411 L01 S48
49 Moore s Law plot (from his original paper) CMPEN 411 L01 S49
50 Transistors (MT) Moore s Law in Microprocessors # transistors on lead microprocessors double every 2 years X growth in 1.96 years! CMPEN 411 L01 S P6 Pentium proc Year Courtesy, Intel
51 # of Transistors per Die Source: ISSCC 2003 G. Moore No exponential is forever, but forever can be delayed CMPEN 411 L01 S51
52 Intel 4004 Microprocessor (10000 nm) transistors 13.5 mm2 108k Hz CMPEN 411 L01 S52
53 Intel Pentium 4 Prescott (2004) 90 nm Area: 112 mm2 125 M transistors L1-Instruction: 16K L1-Data: 16K L2: 1MB CMPEN 411 L01 S53
54 Two chips you are seeing today Microprocessor 366MHz 40mm2 3.65M ASIC (Application Specific IC) 40Mhz 10 mm2 500K CMPEN 411 L01 S54
55 CMPEN 411 L01 S55 IBM Cell Overview IBM/Toshiba/Sony joint project years, 400 designers, 3/9/2001, $400M, 234 million transistors, 4+ Ghz, 256 Gflops (billions of floating pointer operations per second) P P U S P U S P U S P U S P U S P U S P U S P U S P U M I C R R A C B I C MIB Cell Prototype Die (Pham et al, ISSCC 2005)
56 State-of-the Art: Lead Microprocessors Freq Transistors Die size Power Date (HZ) mm2 Server IBM Power G 180M 267 N/A 2003 Itanium 2 1.5G 410M W 2003 IBM Power 5 2G 276M 389 N/A 2004/2 PC IBM Power PC G 58M W 2003/6 Pentium 4 3.2G 55M W 2003/6 AMD Athlon G 105M W 2003/9 Pentium 4 (Prescott) 3.4G 125M W 2004/2 (All use 0.13 um technology except Pentium 4 Prescott, which uses 90 nm tech) Pentium nm (2001) 1.7 G Hz 42 M transistors 217 mm2 Pentium nm (2003) 3.2G Hz 55 M Transistors 131 mm2 Pentium 4 90 nm (2004) 3.4 Hz 125 M Transistors 112 mm2 Pentium on 65nm (2005/2006) 250 Million Pentium on 45nm (2007) 400 to 500 Million CMPEN 411 L01 S56
57 State-of-the Art: Lead Microprocessors (up to date) 300mm wafer and Pentium 4 IC. Photos courtesy of Intel. CMPEN 411 L01 S57
58 Die size (mm) Die Size Growth 100 Die size grows by 14% to satisfy Moore s Law P6 Pentium proc 1 CMPEN 411 L01 S Year Courtesy, Intel
59 Frequency (Mhz) Clock Frequency Lead microprocessors frequency doubles every 2 years X every 2 years P6 Pentium proc CMPEN 411 L01 S Year Courtesy, Intel
60 Power (Watts) Power Dissipation Lead Microprocessors power continues to increase 100 P6 Pentium proc Year Power delivery and dissipation will be prohibitive CMPEN 411 L01 S61 Courtesy, Intel
61 Power Density (W/cm2) Power Density Rocket Nozzle 100 Nuclear Reactor Hot Plate P6 Pentium proc Year Power density too high to keep junctions at low temp CMPEN 411 L01 S62 Courtesy, Intel
62 Power Density (W/cm2) Power Density Rocket Nozzle 100 Nuclear Reactor Hot Plate P6 Pentium proc Year Power density too high to keep junctions at low temp CMPEN 411 L01 S63 Courtesy, Intel
63 ITRS The International Technology Roadmap for Semiconductors (ITRS) is the industry s prediction for the future of semiconductors. It is mostly an extrapolation of existing trends. The ITRS is often slow. CMPEN 411 L01 S64
64 Technology Directions: Old SIA Roadmap Year Feature size (nm) Mtrans/cm Chip size (mm 2 ) Signal pins/chip Clock rate (MHz) Wiring levels Power supply (V) High-perf power (W) Battery power (W) CMPEN 411 L01 S65
65 Technology Scaling Technology shrinks by ~0.7 per generation With every generation can integrate 2x more functions on a chip; chip cost does not increase significantly Cost of a function decreases by 2x But How to design chips with more and more functions? Design engineering population does not double every two years Hence, a need for more efficient design methods Exploit different levels of abstraction CMPEN 411 L01 S66
66 Design Abstraction Levels SYSTEM + MODULE GATE CIRCUIT V in V out S n+ G DEVICE D n+ CMPEN 411 L01 S67
67 Design Productivity Crisis Year Tech. (nm) Complexity Frequency 3 Yr. Design Staff Size Staff Costs M Tr. 400 MHz 210 $90 M M Tr. 500 MHz 270 $120 M M Tr. 600 MHz 360 $160 M M Tr. 800 MHz 800 $360 M 1996: 100 person in P6 team 2007: 1600 person in P10 team Question:?? Person in P38 team? Answer: Every inhabitant of our planet We need to improve the productivity via design automation CMPEN 411 L01 S69
68 Major Design Challenges Microscopic issues ultra-high speeds power dissipation and supply rail drop growing importance of interconnect noise, crosstalk reliability, manufacturability clock distribution Macroscopic issues time-to-market design complexity (millions of gates) high levels of abstractions reuse and IP, portability systems on a chip (SoC) tool interoperability CMPEN 411 L01 S70
69 Testing and Faults CMPEN 411 L01 S71 1/7/2015 L12: Testing 71
70 Chip Technology CMPEN 411 L01 S72 1/7/2015 L12: Testing 72
71 Chip Technology CMPEN 411 L01 S73 1/7/2015 L12: Testing 73
72 Chip Technology CMPEN 411 L01 S74 1/7/2015 L12: Testing 74
73 Chip Technology CMPEN 411 L01 S75 1/7/2015 L12: Testing 75
74 Chip Technology CMPEN 411 L01 S76 1/7/2015 L12: Testing 76
75 Chip Technology CMPEN 411 L01 S77 1/7/2015 L12: Testing 77
76 Chip Technology GHz frequency CMPEN 411 L01 S78 1/7/2015 L12: Testing 78
77 Testing and Faults CMPEN 411 L01 S79 1/7/2015 L12: Testing 79
78 Testing and Faults CMPEN 411 L01 S80 1/7/2015 L12: Testing 80
79 Testing and Faults CMPEN 411 L01 S81 1/7/2015 L12: Testing 81
80 Testing and Faults CMPEN 411 L01 S82 1/7/2015 L12: Testing 82
81 Testing and Faults CMPEN 411 L01 S83 1/7/2015 L12: Testing 83
82 Testing and Faults CMPEN 411 L01 S84 1/7/2015 L12: Testing 84
83 Testing and Faults CMPEN 411 L01 S85 1/7/2015 L12: Testing 85
84 Testing and Faults CMPEN 411 L01 S86 1/7/2015 L12: Testing 86
85 Testing and Faults CMPEN 411 L01 S87 1/7/2015 L12: Testing 87
86 Testing and Faults CMPEN 411 L01 S88 1/7/2015 L12: Testing 88
87 Testing and Faults CMPEN 411 L01 S89 1/7/2015 L12: Testing 89
88 Testing and Faults CMPEN 411 L01 S90 1/7/2015 L12: Testing 90
89 Testing and Faults CMPEN 411 L01 S91 1/7/2015 L12: Testing 91
90 Wafer Cost Chip Yield CMPEN 411 L01 S92 1/7/2015 L12: Testing 92
91 Testing and Faults CMPEN 411 L01 S93 1/7/2015 L12: Testing 93
92 Testing and Faults CMPEN 411 L01 S94 1/7/2015 L12: Testing 94
93 Testing and Faults CMPEN 411 L01 S95 1/7/2015 L12: Testing 95
94 Testing and Faults CMPEN 411 L01 S96 1/7/2015 L12: Testing 96
95 Wafer Cost Yield = 6/12 = 50% Yield = 57/64 = 89% Wafer Cost = $10,000 CMPEN 411 L01 S97 1/7/2015 L12: Testing 97
96 Wafer Cost CMPEN 411 L01 S98 1/7/2015 L12: Testing 98
97 Wafer Cost CMPEN 411 L01 S99 1/7/2015 L12: Testing 99
98 Wafer Cost CMPEN 411 L01 S100 1/7/2015 L12: Testing 100
99 Wafer Cost CMPEN 411 L01 S101 1/7/2015 L12: Testing 101
100 Wafer Cost CMPEN 411 L01 S102 1/7/2015 L12: Testing 102
101 Wafer Cost CMPEN 411 L01 S103 1/7/2015 L12: Testing 103
102 Fault Cost: Testing and Faults Wafer $ $ 0.1 Packaged Chip $0.1 - $1 Board $1 - $10 System $ Field $100 - $1000 CMPEN 411 L01 S104 1/7/2015 L12: Testing 104
103 Pentium Bug: Testing and Faults X 1/ = Due to faulty floating point number divide look-up table CMPEN 411 L01 S105 1/7/2015 L12: Testing 105
104 Next Lecture and Reminders Next lecture Design metrics - Reading assignment 1.3 Reminders CMPEN 411 L01 S106
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