Heterogeneous SoCs. May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 1

Transcription

1 COSCOⅣ Heterogeneous SoCs M HASEGAWA TORU M IDONUMA TOSHIICHI May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 1

2 Contents Background Heterogeneous technology May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 2

3 Background Moore s Law today May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 3

4 Background System-on-a-Chip A computer system is realized on a chip Due to the improvement of the integration technology Metris Small area High performance Low power Demerits Complex design Decrease of yield May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 4

5 Background ARM SoC Block Diagram Reference: Wikipedia May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 5

6 Background Roadmap of SoC May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 6

7 Background Inflections in Processor Design May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 7

8 Background Homogeneous Using the same kind processor Main architecture in recently Major processor are corei7, Xeon, SPARC64 VII, and etc. Fig. Intel Xeon Phi 5110P May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 8

9 Background Heterogeneous Next generation architecture Using the different kind processor Difference of architecture Fast CPU + slow CPU CPU + GPU ARM + FPGA etc Purpose Optimize the efficiency of CPU core Keep the single thread performance and extract the high performance of multi threads May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 9

10 Heterogeneous Technology HETEROGENEOUS SYSTEM ARCHITECTURE(HSA) May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 10

11 What is HSA? The HSA Foundations launched mid 2012 HSA is a new, open architecture specification HSAIL virtual (parallel) instruction set HSA memory model HSA dispatcher and run-time Provide an optimized platform architecture for heterogeneous programming models such as OpenCL, C++AMP, et al May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 11

12 What is HSA? Processor design that makes it easy to harness the entire computing power of an APU for faster and more power-efficient devise, tablets, smartphones and cloud servers GPU PARALLEL WORKLOADS huma(memory) HAS CPU SERIAL WORKLOADS APU ACCELERATED PROCESSING UNIT May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 12

13 State-of-the-art Heterogeneous Processor May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 13

14 HSA Running Model May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 14

15 HSA Software Stack Make GPU easily accessible Support mainstream languages Expandable to domain specific languages Make compute offload efficient Eliminate memory copying Low-latency dispatch Make it ubiquitous Drive-standard through HAS Foundation Open Source key components Optimized Compiler Technology Leverage llvm frame work HASIL as new IR for heterogeneous computing May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 15

16 Key HSA Point HETEROGENEOUS UNIFORM MEMORY ACCESS( HUMA) HQ(HETEROGENEOUS QUEING) May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 16

17 Understating UMA Original meaning of UMA is Uniform Memory Access Refers to how to processing cores in a system view and access memory All processing cores in a true UMA system share a single memory address space Introduction of GPU compute created Non-Uniform Memory Access(NUMA) Require data to be managed across multiple heaps with different address spaces Add programming complexity due to frequent copies, synchronization, and address translation HAS restores the GPU to Uniform memory Access Heterogeneous computing replace GPU Computing May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 17

18 Introducing huma CPU UMA Memory CPU CPU CPU APU NUMA CPU Memory CPU CPU CPU GPU Memory GPU GPU APU With HSA huma CPU CPU CPU Memory GPU GPU GPU May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 18

19 huma Key Features Coherent memory: Ensures CPU and GPU Caches both see An up-to-date view of data CPU Cache Physical Memory Virtual Memory GPU Cache Page-able memory: The GPU can seamlessly access virtual memory addresses that are not (yet) Present in physical memory Entire memory space: Both CPU and GPU can access and allocate any location in the system s virtual memory space May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 19

20 huma Features Access to Entire Memory Space Page-able memory Bi-directional Coherency Fast GPU access to system memory Dynamic Memory Allocation May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 20

21 What is hq? huma defines how processors inside an APU access memory hq defines how processors inside an APU interact with each other to handle computational tasks With hq, the relationship between the CPU and GPU changes May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 21

22 The Trouble With The Old Way of Queuing Application Application Task Queues CPU OS Service Kernel Driver OS-Managed Task Queue GPU CPU->CPU dispatch model is fast and direct CPU->GPU dispatch is through an OS service which adds large due to Kernel Mode transitions and scheduling overhead Kernel driver translates task packets to vendor specific format GPU can only consume tasks and cannot dispatch new tasks to itself or to the CPU May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 22

23 From Master/Slavs to All- Processors-Equal Application Task Queues Application Application Task Queues Application Task Queue enables reduced dispatch latency to GPU Powerful GPU dispatch model adds flexibility to create new work for GPU and/or CPU Application include ray-tracing, graphtraversal, recursive algorithms CPU GPU May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 23

24 hq Provides Direct to Hardware Application A Application B Application C Hardware Queue GPU Application codes to the hardware queue User mode queuing Hardware scheduling Low dispatch times Multiple Queues No Kernel Mode Drivers No Kernel Mode Transitions No Kernel Overhead! May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 24

25 HSA Solution Stack HAS Intermediate Language(HSAIL) The HAS design allows multiple hardware solutions to be exposed to software through a common standard low-level interface May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 25

26 Heterogeneous Technology SILICON PHONICS TECHNOLOGY May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 26

27 Silicon Photonics Technology(1/2) Photonics emit, detect, send, and control the light using the electronics Silicon it is a material for semiconductor Silicon Photonics approach to transfer large amounts of data using optical fiber compare the copper cable lower the power consumption accelerate the transfer time May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 27

28 Silicon Photonics Technology(2/2) The light converts to digital signal Use the phase shifter Path the waveguides of light Infrared(IR) can path the silicon, however it is transparence Components are waveguides, modulator, detection Intel researches this, and products the MXC MXC chooses SPT and New optical fiber ClearCurve, and has possibility are transfer rate is 1.6Tbps and miniaturization May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 28

29 Silicon Photonics Components Fig. Intel Silicon Photonics May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 29

30 Overview of Silicon Photonic Fig. Demonstration of a High Speed 4-Channel Integrated Silicon Photonics WDM Link with Hybrid Silicon Lasers May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 30

31 Transmitter Fig. Demonstration of a High Speed 4-Channel Integrated Silicon Photonics WDM Link with Hybrid Silicon Lasers May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 31

32 Receiver Fig. Demonstration of a High Speed 4-Channel Integrated Silicon Photonics WDM Link with Hybrid Silicon Lasers May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 32

33 Tx & Rx Packages chip Fig. Intel developed Tx & Rx chip May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 33

34 Estimation Data Rates Fig. Demonstration of a High Speed 4-Channel Integrated Silicon Photonics WDM Link with Hybrid Silicon Lasers May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 34

35 Photonics + CMOS-cicuit Fig. PHOTONICS RESEARCH GROUP, integrating a Tb/s optical interconnect layer into CMOS-systems May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 35

36 Thank you May 28, 2014 COMPUTER SYSTEM COLLOQUIUM 36