PIN DIAGRAM. Richa Upadhyay Prabhu. NMIMS s MPSTME January 19, 2016
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2 PIN DIAGRAM Richa Upadhyay Prabhu NMIMS s MPSTME richa.upadhyay@nmims.edu January 19, 2016 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
3 Pin Diagram of 8086 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
4 Pin Diagram of can operate in two modes : Minimum Mode : unique processor system with a single 8086 Maximum Mode : multiprocessor system with more than one 8086 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
5 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
6 Pin Diagram of 8086 Minimum mode Pin 33 (MN/MX) connect to +5V Pin are used as memory and I/O control signal The control signals are generated internally by the 8086/88 Maximum mode Pin 33 (MN/MX) connect to Ground Some control signals are generated externally by the 8288 bus controller chip Max mode is used when math processor is used. Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
7 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
8 Pin Diagram of 8086 AD 15 AD0 : Address Data Bus 16-bit multiplexed address and data bus During the 1st clock cycle AD 0 address AD 15 are the low order 16-Bit The 8086 has a total of 20 address line,the upper 4 lines are multiplexed with the state signal that is A 16 /S 3, A 17 /S 4, A 18 /S 5, A 19 /S 6. During the first clock period the entire 20-bit address is available on these line In the next cycle, AD 15 AD 0 contain the 16 bit data and S3,S4,S5,S6 become the status line Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
9 Pin Diagram of 8086 S 3 and S 4 are decoded as follows 00 extra segment 01 stack segment 10 code or no segment 11 data segment After the first clock cycle of an instruction execution, the A 17 /S 4 anda 16 /S 3 pins specify which segment register generates the segment portion of the 8086 address. Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
10 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
11 BHE/S 7 : is used as bus high enable during the 1st clock cycle of an instruction execution Used to enable data on the most significant half of data bus or can say used to distinguish between the low byte and the high byte of the data for the 16-bit external data bus of 8086 BHE is Low during T1 state of read, write and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus. Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
12 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
13 NMI : Non Maskable Interrupt; An edge triggered input, causes a type-2 interrupt. A subroutine is vectored to via the interrupt vector look up table located in system memory. NMI is not maskable internally by software. A transition from a LOW to HIGH on this pin initiates the interrupt at the end of the current instruction. This input is internally synchronized. Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
14 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
15 Pin Diagram of 8086 INTR (Interrupt Request) An active-high level-triggered input signal to the processor Sampled in the last clock cycle of each instruction In IBM PC, this is connected to the 8259 Interrupt controller Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
16 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
17 Pin Diagram of 8086 RESET : causes the processor to immediately terminate its present activity Active high signal came from 8284 Force the processor to stop any activities and to discard everything The signal must be active high for at least four clock cycles, Data after reset: CS: FFFFH, IP: 0000H, DS ES SS: 0000H Flags: Cleared, Queue: Empty Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
18 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
19 Generation of Control signals using RD, WR and IO/M pins Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
20 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
21 Pin Diagram of 8086 TEST READY TEST pin is examined by the WAIT instruction. If the TEST pin is Low, execution continues. Otherwise the processor waits in an idle state. This input is synchronized internally during each clock cycle on the leading edge of CLK. is the acknowledgement from the addressed memory or I/O device that it has completed the data transfer. The READY signal from memory or I/O is synchronized by the 8284 clock generator to form READY. This signal is active HIGH. Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
22 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
23 Pin Diagram of 8086 CLOCK (heart beat of CPU) Clock provides the basic timing for the processor and bus controller. It is asymmetric with 33 percent duty cycle to provide optimized internal timing Minimum frequency of 5 MHz is required 8284 clock generator chip must be connected to the 8086 clock pin, since it does not have on chip clock generator The crystal connected to 8284 must have a frequency 3 times the 8086 internal frequency Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
24 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
25 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
26 Pin Diagram of 8086 ALE : Address Latch Enable ALE is provided by the processor to latch the address into the 8282/8283 address latch. It is an active high pulse during T1 of any bus cycle. DT/ R: DATA Transmit/Receive In minimum mode, 8286/8287 transceiver is used for the data bus. DT/ R is used to control the direction of data flow through the transceiver. DEN : Data Enable It is provided as an output enable for the 8286/8287 in a minimum system which uses the transceiver Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
27 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
28 Pin Diagram of 8086 HOLD & HLDA (I/O): Hold and Hold Acknowledge Hold indicates that another master is requesting a local bus HOLD To be acknowledged, HOLD must be active HIGH. The processor receiving the HOLD request will issue HLDA (HIGH) as an acknowledgement in the middle of the T1-clock cycle. With the issue of HLDA, the processor will float the local bus and control lines Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
29 Pins Specific to Maximum mode only Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
30 Pin Diagram of 8086 S2, S1, S0 : Status Pins These pins are active during T4, T1 and T2 states and is returned to passive state 1,1,1 during T3 Are used by the 8288 bus controller to generate all memory and I/O operation access control signals Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
31 Pins Specific to Maximum mode only Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
32 Pin Diagram of 8086 QS0, QS1: Queue Status Queue Status is valid during the clock cycle after which the queue operation is performed QS0, QS1 provide status to allow external tracking of the internal 8086 instruction queue Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
33 Pins Specific to Maximum mode only Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
34 Pin Diagram of 8086 LOCK It indicates to another system bus master, not to gain control of the system bus while LOCK is active Low The LOCK signal is activated by the LOCK prefix instruction and remains active until the completion of the instruction This signal is active Low and floats to tri-state OFF during hold acknowledge Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
35 Pins Specific to Maximum mode only Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
36 Pin Diagram of 8086 RQ/GT0 and RQ/GT1 (I/O): Request/Grant Are used by other processors in a multi processor organization Local bus masters of other processors force the processor to release the local bus at the end of the processors current bus cycle Each pin is bi-directional and has an internal pull up resistors. Hence they may be left un-connected Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
37 8284 CLOCK GENERATOR Ancillary component to the 8086/8088 microprocessors The 8284 provides the following basic functions or signals: Clock generation (CLK) RESET synchronization READY synchronization TTL level peripheral clock (PCLK) Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
38 8284 CLOCK GENERATOR The 8088/8086 require a specific waveform for the system clock Fast rise and fall times ( 10ns ) Logic 0: -0.5 to 0.6 V Logic 1: 3.9 to 5.0 V Duty cycle of 33 33% duty cycle Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
39 8284 CLOCK GENERATOR Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
40 8284 CLOCK GENERATOR Input Pins RES (Reset In): from power supplier X1 and X2 (Crystal In): the crystal frequency must be 3 times the desired frequency for the microprocessor RDY1 and AEN1: provide a Ready signal to processor, which will insert a WAIT state to the CPU read/write cycle RDY2 and AEN2: For multiprocessor systems Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
41 8284 CLOCK GENERATOR Output Pins RESET: reset signal to the 8086/88, activated by RES OSC (oscillator): provide to the expansion slot CLK (clock): 1/3 of the crystal input, with a duty cycle of 33% PCLK: one-half of CLK (1/6 of crystal) with duty cycle of 50% and is TTL compatible. READY: connect to READY input of CPU to insert WAIT state Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
42 8284 CLOCK GENERATOR Output Pins F/C (Frequency/crystal select): If 1, an external clock is provided to the EFI input pin and if 0, an external crystal oscillator connected to X1 and X2 provides the clock EFI (External frequency Input ): Supplies the timing whenever the F/C is high. CSYNC (Clock Synchronization): Used whenever the EFI input provides synchronization in systems with multiple processors. If the internal crystal oscillator is used, Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
43 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
44 8282/8283 LATCH Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
45 8282/8283 LATCH CMOS octal latching bu er provides an eight bit parallel latch/bu er in a 20 pin package Basically de-multiplexing the data and addressing bus OE (Output Enable) connected to GND, the chip is selected STB (Strobe) is connected to the pin ALE (Address Latch Enable) of the processor and takes over the address data from the multiplexed address-/databus Latches are used to de-multiplex the address/data and address/status lines and commonly have output bu ers for driving external loads. Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
46 8282 LATCH Figure: Functional Diagram and Pin Diagram Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
47 8286 TRANSCEIVER Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
48 8286 TRANSCEIVER If a system includes several interfaces then to increase current sourcing/sinking capacities it is necessary to use drivers and receivers for data bus also Intel 8286 device is used to implement the transceiver block Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
49 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
50 8286 TRANSCEIVER If a system includes several interfaces then to increase current sourcing/sinking capacities it is necessary to use drivers and receivers for data bus also Intel 8286 device is used to implement the transceiver block It has 16- tri state elements, 8 receivers and 8 drivers That s why TWO 8286 are required to service 16 data lines of 8086 DT/R is connected to T input, which controls the direction of data flow Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
51 8286 TRANSCEIVER DT/R is connected to T input, which controls the direction of data flow When this signal is low, receivers are enabled, so that 8086 can read data from memory and I/O device When this signal goes high, drivers are enabled allowing 8086 to transfer(or write) data into memory and I/O device To enable output of transceiver its OE pin should be low, That s why it is connected to DEN pin of Since DEN signal goes low when CPU is ready to send or receive data Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
52 Basic Minimum mode configuration Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, / 51
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